DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claim 12 is objected to because of the following informalities: claim 12 recites: “on plurality of solder patterns” which should be changed to “on the plurality of solder patterns” for readability.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. U.S. Patent Application Publication 20210111153 A1.
Referring to claim 11, Lin discloses in Figs. 1G and 12 a semiconductor package comprising:
a redistribution substrate (110, Fig. 1G, para [33] (paragraph(s) [0033]); not-labeled redistribution substrate in Fig. 12);
a first lower semiconductor chip (120, Fig. 1G, para [38]; 620, Fig. 12, para [77]) disposed on a top surface of the redistribution substrate (110; said not-labeled redistribution substrate);
a plurality of conductive posts (copper 112, para [37]; not-labeled conductive posts, similar to conductive post 613, Fig. 10, which is similar to conductive post 112, para [76]) disposed on the top surface of the redistribution substrate (110; said not-labeled redistribution substrate), and including at least a portion laterally spaced apart from the first lower semiconductor chip (120; 620);
an upper semiconductor chip (150, para [39]; 23, para [88]) disposed on the first lower semiconductor chip (120; 620) and the plurality of conductive posts (112; said not-labeled conductive post); and
a plurality of solder patterns (low-temperature solder indium tin 152, Fig. 1G, para [42]; solder ball 180, Fig. 12, para [85]) disposed between a first conductive post of the conductive posts (112; said not-labeled conductive post) and the upper semiconductor chip (150; 23),
wherein the plurality of solder patterns (152; 180) include a different metal material (indium tin, para [42]) than the conductive posts (112, made of copper), and
the first conductive post (112; said not-labeled conductive post) is (inherently) configured to supply a voltage to the upper semiconductor chip (150; 23).
Referring to claim 13, Lin further discloses a second lower semiconductor chip (620, Fig. 12) laterally spaced apart from the first lower semiconductor chip (620) and the conductive posts (said not-labeled conductive post), and wherein the upper semiconductor chip (23) is disposed on the second lower semiconductor chip (620).
4. Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. U.S. Patent Application Publication 20220302002 A1.
Referring to claim 11, Kim discloses in Fig. 7 a semiconductor package comprising:
a redistribution substrate (110, para [21]);
a first lower semiconductor chip (121, para [21]) disposed on a top surface of the redistribution substrate (110);
a plurality of conductive posts (via 132, para [54], similar to via 113, which is formed of copper, para [26]) disposed on the top surface of the redistribution substrate (110), and including at least a portion laterally spaced apart from the first lower semiconductor chip (121);
an upper semiconductor chip (220, para [56]) disposed on the first lower semiconductor chip (121) and the plurality of conductive posts (132); and
a plurality of solder patterns (low-melting-point tin 214, para [58]) disposed between a first conductive post (132) of the conductive posts (132) and the upper semiconductor chip (220),
wherein the plurality of solder patterns (214) include a different metal material (tin, para [58]) than the conductive posts (132, made of copper), and
the first conductive post (132) is (inherently, via circuit 213 and wire WB, para [56, 57]) configured to supply a voltage to the upper semiconductor chip (220).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 15 is rejected under 35 U.S.C. §103 as being unpatentable over Kim et al. U.S. Patent Application Publication 20220302002 A1.
Referring to claim 15, Kim further discloses a passive device (170, para [21]) on a bottom surface of the redistribution substrate (110), wherein the passive device is electrically connected to the first conductive post (132) through the redistribution substrate (1100. Although Kim does not specifically disclose a relative position as claimed (the passive device vertically overlaps the first conductive post), the claimed relative position will not support the patentability of subject matter encompassed by the prior art (Kim indicates in Fig. 7 that the passive device 170 is positioned on a bottom surface of the redistribution substrate 110 where there is available space) unless there is evidence indicating such a relative position is critical.
Allowable Subject Matter
6. Claims 1-10 and 16-20 are allowable over the prior art of record.
Claims 12 and 14, insofar as in compliance with the claim objections detailed above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor package with all exclusive limitations as recited in claims 1, 12, 14 and 16, which may be characterized (claim 1), in that each of the plurality of first bumps, which are disposed between the conductive post and the upper semiconductor chip, includes a first pillar pattern and a first solder pattern disposed on the first pillar pattern, (claim 16), in that each of the first bumps, which are disposed between the conductive posts and the upper semiconductor chip, comprises a first pillar pattern and a first solder pattern disposed between the first pillar pattern and the conductive posts, (claim 12) a plurality of pillar patterns is disposed on the plurality of solder patterns and electrically connected to the upper semiconductor chip, and in that the plurality of solder patterns include a different metal material than the plurality of pillar patterns, and (claim 14) in that an upper interconnection structure is on the lower interconnection structure, and in that a width of the upper interconnection structure is less than a width of the lower interconnection structure.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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06-23-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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