DETAILED ACTION
Response to Amendments
Applicant’s amendment, filed 07/29/2026, for application number 18/664,838 has been received and entered into record. Claims 1 and 3 have been amended and Claims 5-7 have been cancelled. Therefore, Claims 1-4 are presented for examination. The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 07/29/2026 as to the previously-presented limitations of Claim 1 and the claim interpretation under 35 U.S.C. 112f have been fully considered but they are not persuasive.
Applicant’s arguments filed 07/29/2026 as to the newly-amended claim limitations have been fully considered but are moot due to the new rejection based on the references cited below.
Applicant argues that the Specification describes a “time difference computation unit,” “frequency offset computation unit,” “correction time interval computation unit,” and “storage unit,” with sufficient structural specificity. Examiner respectfully disagrees.
Specifically, Applicant argues that paragraph [0036] of published Specification US 2024/0388372 A1 describing the time difference computation unit computing the time difference TMD, paragraph [0040] describing the correction time interval computation unit computing the correction time interval CTI as CTI = TA2 - TA1, paragraph [0040] describing the frequency offset computation unit 44 computing frequency offset as FOF = (TMD + PHD)/CTI, and paragraph [0040] describing the storage unit storing the first input time TA1. Additionally, Applicant states each unit corresponds to well-understood computational and storage structures (for example, subtractors, adders, dividers, and registers) that are standard building blocks in digital circuit design.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function
Examiner notes while the recited paragraphs in the published Specification US 2024/0388372 A1 provides specific mathematical operations and data relationships, it remains unclear what structures would be performing these mathematical operations and data relationships. Examiner notes that the examples provided by the Applicant (subtractors, adders, dividers, and registers) were not provided in the Specification as presented, thus the units are still interpreted under 35 U.S.C. 112(f).
Applicant also argues that TAKAHASHI does not teach adjusting frequency based on the combination of an input-time/internal-time difference and a phase difference derived from the timestamp information. Specifically, Applicant argues that TAKAHASHI does not teach a single processing unit that computes a time difference between an input stamp time and an internal counter time and uses that together with a phase difference to adjust a single oscillation circuit’s frequency.
Examiner notes one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). That is, a single processing unit computing a time difference and using it together with a phase difference, is not disclosed by TAKAHASHI alone, but rather, the combination of references. Instead, the rejection relies on TAKAHASHI only to teach using a time difference together with a phase difference to adjust frequency.
No additional arguments were made as to the remaining references. As such, the rejection is maintained.
Allowable Subject Matter
Claim 3 is allowed.
Claim 4 would be allowed once the outstanding rejection under 35 U.S.C. 112 were overcome.
The following is an examiner’s statement of reasons for allowance:
SHIROTORI et al., US 2017/0063380 A1, discloses A real-time clock device comprising: an interface circuit that receives timestamp information (Fig. 1 illustrates a real-time clock device 1 having an interface circuit 90, a timing circuit 70, register 54, and control device 100; [0063] discloses the timing circuit 70 generates clock time information (information of year, month, day, hour, minute, second, and so on); the clock time information is assigned to a predetermined address of the register 54, and the control device 100 can access the address of the register 54 via the interface circuit 90 to retrieve the clock time information (i.e. the figure shows the interface circuit 90 having arrows to and from the timing circuit and register 54, therefore the interface circuit 90 can receive the timestamp information); a reference clock time information input to the interface circuit 90 (i.e. receiving timestamp information); [0115] discloses the clock time information (current time) generated by the timing circuit 70 (i.e. the timestamp information indicates a current input time));
an oscillation circuit that outputs an oscillation clock signal (Fig. 1 illustrates an oscillating circuit 10; [0047] discloses the output signal of the oscillating circuit 10 used as a clock signal (i.e. outputting an oscillation clock signal));
a frequency division circuit that divides a frequency of the oscillation clock signal to generate a frequency-divided clock signal (Fig. 1 illustrates a logic circuit 30 (i.e. a frequency division circuit); [0047-0048] disclose the logic circuit 30 divides the signal output from the oscillating circuit 10 (i.e. frequency of the oscillation signal) to generate a clock signal having an adjusted frequency (i.e. to generate a frequency-divided clock signal));
a time counter that generates information regarding an internal time based on the frequency-divided clock signal (Fig. 1 illustrates a timing circuit 70; [0063] discloses a timing circuit 70 that generates clock time information (i.e. generates information) based on the signal output by the logic circuit 30 (i.e. regarding internal time based on the frequency-divided clock signal));
and a processing circuit that performs processing of updating the information regarding internal time of the time counter based on an input time indicated by the input timestamp information (Fig. 1 illustrates an oscillation circuit 2 (i.e. a processing circuit); [0063] discloses the timing circuit 70 within the oscillation circuit 2 can correct or generate (i.e. performs processing of updating) the clock time information (i.e. the information regarding internal time) of the timing circuit 70 (i.e. the time counter) based on the reference clock time information input (i.e. based on an input time indicated by the input timestamp information)),
TAKAHASHI, US 2023/0077120 A1, discloses timestamp information indicating an input time ([0048] teaches a slave device that performs time synchronization using a synchronous ethernet signal and a time packet (i.e. timestamp information) received from a master device; [0032] teaches extracting time information from the time packets; the transmission delay time is calculated from a difference between the time (t1) when the master device transmits the time packet T1 (i.e. the time packet the slave device receives indicates an input time));
a phase comparator that compares phases of a reference signal for synchronization of the timestamp information and the frequency-divided clock signal and calculates a phase difference between the reference signal and the frequency-divided clock signal ([0048] teaches the time synchronization device 1 is a slave device that performs time synchronization using a synchronous ethernet signal and a time packet received from a master device (i.e. the slave device utilizes the ethernet signal and time information for synchronization); [0051] teaches a phase detector 101 (i.e. a phase comparator) that outputs a result of the comparison (i.e. compares phases and calculates a phase difference) between the phase of the received synchronous ethernet signal (i.e. a reference signal) and that of the divided signal (i.e. the frequency-divided clock signal) from the frequency divider 104);
adjusting a frequency based on a time difference between the input time and the internal time and the phase difference ([0051-0055] teach generating a time synchronization signal by using a calculated synchronization signal based on (i.e. adjusting a frequency based on) timing and frequency synchronization signals. The calculated synchronization signal being based on a combination of a time synchronization signal from a time difference obtained by comparing between (i.e. a time difference between) time packets received (i.e. the input time) and time of the divided signal (i.e. the internal time), and a frequency synchronization signal from a phase difference (i.e. the phase difference)).
However, none of the references, individually nor in combination, explicitly teach the processing circuit calculates a correction time interval based on a first input time indicated by the timestamp information that is input at a first timing, and a second input time indicated by the timestamp information that is input at a second timing after the first timing, and adjusts the frequency of the oscillation circuit based on the correction time interval, the time difference, and the phase difference, in combination with the remaining limitations as required by Claim 3.
Claim 4 depends on Claim 3 and is allowed over the prior art accordingly.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 2 and 4 are interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
In Claim 2, such limitations are: “a time difference computation unit that calculates the time difference between the input time and the internal time,” and “a frequency offset computation unit that calculates a frequency offset based on the time difference and the phase difference.”
In Claim 4, such limitations are: “a storage unit that stores the first input time,” “a correction time interval computation unit that calculates the correction time interval,” “a time difference computation unit that calculates the time difference between the second input time and the internal time,” and “a frequency offset computation unit that calculates a frequency offset based on the correction time interval, the time difference, and the phase difference.”
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the Specification shows there does not appear to provide any disclosure to the structure associated with a “time difference computation unit,” “frequency offset computation unit,” “storage unit,” or “correction time interval computation unit.” As such, the “time difference computation unit,” “frequency offset computation unit,” “storage unit,” or “correction time interval computation unit” are not interpreted to cover any particular structure.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The written description fails to disclose the corresponding structures, materials, or acts for performing the entire claimed functions of a “time difference computation unit that calculates the time difference between the input time and the internal time,” and “frequency offset computation unit that calculates a frequency offset based on the time difference and the phase difference,” of Claim 2.
The written description fails to disclose the corresponding structures, materials, or acts for performing the entire claimed functions of a “storage unit that stores the first input time,” “correction time interval computation unit that calculates the correction time interval,” “time difference computation unit that calculates the time difference between the second input time and the internal time,” and “frequency offset computation unit that calculates a frequency offset based on the correction time interval, the time difference, and the phase difference,” of Claim 4.
Claims 2 and 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, the claim limitations: a “time difference computation unit that calculates the time difference between the input time and the internal time,” and “frequency offset computation unit that calculates a frequency offset based on the time difference and the phase difference,” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structures, materials, or acts for performing the entire claimed functions and to clearly link the structures, materials, or acts to the functions. The Specification does not appear to provide definitions containing any structures associated with the limitations at issue. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Regarding Claim 4,the claim limitations: a “storage unit that stores the first input time,” “correction time interval computation unit that calculates the correction time interval,” “time difference computation unit that calculates the time difference between the second input time and the internal time,” and “frequency offset computation unit that calculates a frequency offset based on the correction time interval, the time difference, and the phase difference,” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structures, materials, or acts for performing the entire claimed functions and to clearly link the structures, materials, or acts to the functions. The Specification does not appear to provide definitions containing any structures associated with the limitations at issue. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over SHIROTORI et al., US 2017/0063380 A1, in view of TAKAHASHI, US 2023/0077120 A1, and further in view of AWEYA et al., US 2007/0097947 A1.
Regarding Claim 1, SHIROTORI discloses:
A real-time clock device comprising: an interface circuit that receives timestamp information indicating an input time (Fig. 1 illustrates a real-time clock device 1 having an interface circuit 90, a timing circuit 70, register 54, and control device 100; [0063] discloses the timing circuit 70 generates clock time information (information of year, month, day, hour, minute, second, and so on); the clock time information is assigned to a predetermined address of the register 54, and the control device 100 can access the address of the register 54 via the interface circuit 90 to retrieve the clock time information (i.e. the figure shows the interface circuit 90 having arrows to and from the timing circuit and register 54, therefore the interface circuit 90 can receive the timestamp information); a reference clock time information input to the interface circuit 90 (i.e. receiving timestamp information); [0115] discloses the clock time information (current time) generated by the timing circuit 70 (i.e. the timestamp information indicates a current input time));
an oscillation circuit that outputs an oscillation clock signal (Fig. 1 illustrates an oscillating circuit 10; [0047] discloses the output signal of the oscillating circuit 10 used as a clock signal (i.e. outputting an oscillation clock signal));
a frequency division circuit that divides a frequency of the oscillation clock signal to generate a frequency-divided clock signal (Fig. 1 illustrates a logic circuit 30 (i.e. a frequency division circuit); [0047-0048] disclose the logic circuit 30 divides the signal output from the oscillating circuit 10 (i.e. frequency of the oscillation signal) to generate a clock signal having an adjusted frequency (i.e. to generate a frequency-divided clock signal));
a time counter that generates information regarding an internal time based on the frequency-divided clock signal (Fig. 1 illustrates a timing circuit 70; [0063] discloses a timing circuit 70 that generates clock time information (i.e. generates information) based on the signal output by the logic circuit 30 (i.e. regarding internal time based on the frequency-divided clock signal));
and a processing circuit that performs processing of updating the information regarding internal time of the time counter based on an input time indicated by the input timestamp information (Fig. 1 illustrates an oscillation circuit 2 (i.e. a processing circuit); [0063] discloses the timing circuit 70 within the oscillation circuit 2 can correct or generate (i.e. performs processing of updating) the clock time information (i.e. the information regarding internal time) of the timing circuit 70 (i.e. the time counter) based on the reference clock time information input (i.e. based on an input time indicated by the input timestamp information)),
While SHIROTORI does disclose adjusting a frequency of the oscillation circuit ([0047-0048] disclose the logic circuit 30 within the oscillation circuit 2 (i.e. the processing circuit) adjusting the frequency of the oscillating circuit 10 (i.e. adjusting a frequency of the oscillation circuit) by method of changing the division ratio for dividing the frequency), SHIROTORI does not explicitly disclose timestamp information indicating an input time; adjusting a frequency of the oscillation circuit based on a time difference between the input time and the internal time and the phase difference; and a phase comparator that compares phases of a reference signal and the frequency-divided clock signal and calculates a phase difference between the reference signal and the frequency-divided clock signal.
However, TAKAHASHI teaches timestamp information indicating an input time ([0048] teaches a slave device that performs time synchronization using a synchronous ethernet signal and a time packet (i.e. timestamp information) received from a master device; [0032] teaches extracting time information from the time packets; the transmission delay time is calculated from a difference between the time (t1) when the master device transmits the time packet T1 (i.e. the time packet the slave device receives indicates an input time));
a phase comparator that compares phases of a reference signal for synchronization of the timestamp information and the frequency-divided clock signal and calculates a phase difference between the reference signal and the frequency-divided clock signal ([0048] teaches the time synchronization device 1 is a slave device that performs time synchronization using a synchronous ethernet signal and a time packet received from a master device (i.e. the slave device utilizes the ethernet signal and time information for synchronization); [0051] teaches a phase detector 101 (i.e. a phase comparator) that outputs a result of the comparison (i.e. compares phases and calculates a phase difference) between the phase of the received synchronous ethernet signal (i.e. a reference signal) and that of the divided signal (i.e. the frequency-divided clock signal) from the frequency divider 104);
TAKAHASHI further teaches the method of adjusting a frequency based on a time difference between the input time and the internal time and the phase difference ([0051-0055] teach generating a time synchronization signal by using a calculated synchronization signal based on (i.e. adjusting a frequency based on) timing and frequency synchronization signals. The calculated synchronization signal being based on a combination of a time synchronization signal from a time difference obtained by comparing between (i.e. a time difference between) time packets received (i.e. the input time) and time of the divided signal (i.e. the internal time), and a frequency synchronization signal from a phase difference (i.e. the phase difference)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SHIROTORI and TAKAHASHI before him before the effective filing date of the invention, to incorporate TAKAHASHI’s method of adjusting frequency based on time and phase difference into SHIROTORI’s real-time clock device to improve accuracy of time synchronization (TAKAHASHI [0011]).
However, the combination of SHIROTORI and TAKEHASHI do not explicitly disclose the reference signal being generated based on an input timing or an input end timing of the timestamp information.
AWEYA teaches the reference signal being generated based on an input timing or an input end timing of the timestamp information ([0016] teaches wherein the slave clock (i.e. the reference signal generation unit) generates the PLL Reference X(n) (i.e. generates the reference signal) based on each timestamp arrival (i.e. based on an input timing of the timestamp information)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SHIROTORI, TAKAHASHI, and AWEYA before him before the effective filing date of the invention, to incorporate AWEYA’s slave clock generating reference signals based on timestamp information into SHIROTORI and TAKAHASHI’s real-time clock device to synchronize the slave’s local clock to the transmitter’s clock (AWEYA [0005]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over SHIROTORI, in view of TAKAHASHI, in view of AWEYA, and further in view of DWIVEDI et al., US 2022/0039042 A1.
Regarding Claim 2, SHIROTORI, TAKAHASHI, and AWEYA disclose the real-time clock device of Claim 1. While SHIROTORI, TAKAHASHI, and AWEYA disclose:
a time difference computation unit that calculates the time difference between the input time and the internal time (TAKAHASHI [0052] teaches a time detector 201 (i.e. a time difference computation unit) that outputs a result of time comparison (i.e. calculating the time difference) between the time of the time packets (i.e. the input time) and time of the divided signal (i.e. the internal time));
a frequency offset computation unit that calculates a frequency offset based on the time difference and the phase difference (TAKAHASHI [0053] teaches the Digital Controlled Oscillator (DCO) 203 (i.e. a frequency offset computation unit) that outputs a calculation (i.e. calculates) as a synchronization signal (i.e. a frequency offset) by adding the time synchronization signal (i.e. the time difference) and the frequency synchronization signal (i.e. the phase difference));
adjusting the frequency of the oscillation circuit based on the frequency offset (SHIROTORI [0047-0048] disclose adjusting the frequency of the signal output from the oscillating circuit 10 (i.e. adjusting the frequency of the oscillation circuit); TAKAHASHI [0055] teaches the method of adjusting frequency by generating a time synchronization signal (i.e. signal where frequency is being adjusted) based on the calculated synchronization signal (i.e. based on the frequency offset)),
The combination of SHIROTORI, TAKAHASHI, and AWEYA do not explicitly disclose wherein the processing circuit includes: a time difference computation unit, a frequency offset computation unit, and a frequency adjustment circuit.
However, DWIVEDI also discloses the limitations: wherein the processing circuit includes: a time difference computation unit that calculates the time difference (Fig. 7 illustrates a processing circuitry 701 (i.e. the processing circuit) including a measuring module 712 (i.e. a time difference computation unit); [0097] teaches the measuring module 712 calculates the time differences between signals received (i.e. calculating the time difference));
a frequency offset computation unit that calculates a frequency offset (Fig. 7 illustrates an estimating module 713 (i.e. a frequency offset computation unit) within the processing circuitry 701; [0098] teaches the estimating module 713 estimates (i.e. calculates) the relative frequency offset (i.e. frequency offset));
and teaches and a frequency adjustment circuit that adjusts the frequency of the oscillation circuit based on the frequency offset (Fig. 7 illustrates an adjusting module 714 (i.e. a frequency adjustment circuit) within the processing circuitry 701; [0099] teaches the adjusting module 714 adjusts the clock based on the frequency offset).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SHIROTORI, TAKAHASHI, AWEYA, and DWIVEDI before him before the effective filing date of the invention, to incorporate DWIVEDI’s processing circuitry for synchronization into SHIROTORI, TAKAHASHI, and AWEYA’s real-time clock device using time and phase difference to improve time precision (DWIVEDI [0002]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Laurenz Advincula whose telephone number is (571)272-9211. The examiner can normally be reached T-F 8:30 AM - 5:30 PM EST.
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/L.A./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
