Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species 1A, in the reply filed on August 10, 2026 is acknowledged. The traversal is on the ground(s) that the device of claim 7 comprising “subtractively etched extended vias” cannot be formed by alternative processes (i.e., filling and planarizing trenches formed in a dielectric layer). This is not found persuasive because Mignot (US 20200357692 A1) teaches all limitations of claim 7 (see detailed below), wherein the “subtractively etched extended vias” are formed by patterning trenches in a dielectric material, filling the trenches with a conductive material, and planarizing the conductive material (see Figs. 3-6).
Claims 10 and 17-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention or species, there being no allowable generic or linking claim.
The requirement is still deemed proper and is therefore made FINAL.
Claim Interpretation
Claims 1 and 7 cite a “zero track skip” being disposed in a space between a longitudinal break of a metal line. The specification defines a “zero track skip” as a dielectric material defined and bounded by adjacent metal lines, which are interpreted as adjacent portions of a metal line comprising a gap or break.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-9 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mignot (US 20200357692 A1).
Regarding Claim 1, Mignot teaches a semiconductor device (shown Fig. 13), comprising:
a metal line (40) having a longitudinal break therein (shown Fig. 13) to provide a first portion of the metal line and a second portion of the metal line (see annotated below);
a first extended via (30, see annotated below) contacting an end of the first portion at a sidewall of the first extended via (shown Fig. 13);
a second extended via being offset from the first extended via and contacting an end of the second portion at a sidewall of the second extended via (see annotated below);
the first extended via and the second extended via defining a space therebetween (see annotated below); and
a zero track skip (portion of ILD 32) disposed within the space (shown Fig. 13).
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Regarding Claim 2, Mignot teaches the semiconductor device as recited in claim 1, wherein the metal line includes a thickness (a vertical distance as viewed in Fig. 13) and the first extended via includes a height (vertical distance shown Fig. 13) that extends through a portion of the thickness (shown Fig. 13).
Regarding Claim 3, Mignot teaches the semiconductor device as recited in claim 1, wherein the first extended via includes a height that traverses two metal levels (shown traversing metal levels 40 and 18 and extending to metal layer 20 in Fig. 13).
Regarding Claim 4, Mignot teaches the semiconductor device as recited in claim 1. Mapping to the first extended via and second extended via may further be swapped along with a first portion of the metal line and second portion of the metal line respectively, such that the second extended via includes a height that traverses two metal levels (shown Fig. 13).
Regarding Claim 5, Mignot teaches the semiconductor device as recited in claim 1, wherein the zero track skip is laterally bounded within the space between the first extended via and the second extended via (shown Fig. 13).
Regarding Claim 7, Mignot teaches the semiconductor device, comprising:
a pair of subtractively etched extended vias (see first extended via and second extended via annotated below, see also [0051] and Figs. 5-6 illustrating a subtractive etch of metal layer 30);
a dielectric layer (32) disposed on the pair of subtractively etched extended vias, the pair of subtractively etched extended vias having top portions that extend above the dielectric layer (see Fig. 11 showing portions of the dielectric layer being recessed to a level below top portions of the extended vias);
a first metal line portion (see annotated below) connected to a sidewall of one of the pair of subtractively etched extended vias (shown Fig. 13);
a second metal line portion (see annotated below) connected to a sidewall of another of the pair of subtractively etched extended vias (shown Fig. 13);
the top portions defining a space therebetween; and
a zero track skip (portion of dielectric layer 32) disposed within the space (shown Fig. 13).
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Regarding Claim 8, Mignot teaches the semiconductor device as recited in claim 7, wherein the first metal line portion and the second metal line portion include a thickness and the pair of subtractively etched extended vias include a height (a height of the first extended via) that extends through a portion of the thickness (shown Fig. 13).
Regarding Claim 9, Mignot teaches the semiconductor device as recited in claim 7, wherein the pair of subtractively etched extended vias include a height (a height of the first extended via) that traverses two metal levels (shown Fig. 13 traversing metal levels 40 and 18 and extending to metal layer 20).
Regarding Claim 11, Mignot teaches the semiconductor device as recited in claim 7, wherein the zero track skip is laterally bounded within the space (see annotated above).
Regarding Claim 12, Mignot teaches a semiconductor device (see Fig. 13), comprising:
a metal line (40) having an end portion (corresponding to trench 42, shown Fig. 13) on a metal level (conductive layer 40 being at a level Mx+1); and
an extended via (30) traversing a plurality of metal levels (traversing metal levels 40, 18 and extending to metal level 20) and being embedded in the end portion of the metal line on the metal level such that lateral portions of a top portion of the extended via are connected to the metal line (shown Fig. 13).
Regarding Claim 13, Mignot teaches the semiconductor device as recited in claim 12, wherein the metal line includes a thickness (shown Fig. 13) and the extended via includes a height that extends through the thickness in its entirety (shown Fig. 13).
Regarding Claim 14, Mignot teaches the semiconductor device as recited in claim 12, wherein the metal line includes a thickness and the extended via includes a height that extends through a portion of the thickness (shown Fig. 13).
Regarding Claim 15, Mignot teaches the semiconductor device as recited in claim 12, wherein the extended via includes a height that traverses two metal levels (shown Fig. 13 traversing metal levels 40, 18 and extending to metal level 20).
Regarding Claim 16, Mignot teaches the semiconductor device as recited in claim 12, wherein the extended via includes portions of the metal line on opposite sides of the extended via (shown Fig. 13).
Claim(s) 1-2 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson (US 10020223 B1).
Regarding Claim 1, Anderson teaches a semiconductor device (see Figs. 1 and 13), comprising:
a metal line (12 and conductive liner 34, see also annotated below) having a longitudinal break therein to provide a first portion (left side) of the metal line and a second portion (right side) of the metal line (shown Fig. 13);
a first extended via (44 left) contacting an end of the first portion at a sidewall of the first extended via (wherein outer sidewalls of vias are shown meeting the conductive liner at ends of the first portion and second portion in Fig. 13);
a second extended via (44 right) being offset from the first extended via and contacting an end of the second portion at a sidewall of the second extended via (shown Fig. 13);
the first extended via and the second extended via defining a space (Min INS, shown Fig. 1) therebetween; and
a zero track skip (middle portion of dielectric 36) disposed within the space (shown Fig. 13).
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Regarding Claim 2, Anderson teaches the semiconductor device as recited in claim 1, wherein the metal line includes a thickness and the first extended via includes a height that extends through a portion of the thickness (shown extending into at least a top portion of a thickness in Fig. 13).
Regarding Claim 5, Anderson teaches the semiconductor device as recited in claim 1, wherein the zero track skip is laterally bounded within the space between the first extended via and the second extended via (shown Fig. 13).
Regarding Claim 6, Anderson teaches the semiconductor device as recited in claim 1, wherein the first extended via and the second extended via have a same height (shown Fig. 13).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Briggs (US 20180114752 A1) teaches a semiconductor structure wherein skip-vias traverse metal layers while maintaining reduced spacing.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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