Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,8-11,16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akram et al (PG Pub 2016/0343823 A1).
Regarding claim 1, Akram teaches (see claim 16 below) a semiconductor device comprising a silicon carbide (SiC) body, comprising: a drift region of a first conductivity type; a body region of a second conductivity type; a source region of the first conductivity type; and a gate structure comprising a gate electrode and a gate dielectric that isolates the gate electrode from the SiC body, wherein:the gate structure is disposed adjacent to at least one of the source region, the body region or the drift region, the gate dielectric comprises a multilayer laminate structure comprising a first layer of a first dielectric material and a second layer of a second dielectric material.
Regarding claim 8, Akram teaches the semiconductor device according to claim 1, wherein the gate dielectric comprises at least two layers having the first dielectric material (silicon oxide interfacial layer, paragraph [0036], LaSiO or HfSiO as layer 144, paragraphs [0034] to [0038]) and at least two layers having a second dielectric material (142/146, AlO, for example, paragraphs [0034] to [0038]).
Regarding claim 9, Akram teaches the semiconductor device according to claim 1, wherein at least one of the gate dielectric or an interlayer dielectric comprises a third dielectric material layer comprising at least one of a Si-based material (paragraph [0038]), an Al-based material, or a high-k dielectric material.
Regarding claim 10, Akram teaches the semiconductor device according to claim 1, wherein the gate dielectric further comprises an interface dielectric layer (silicon oxide interfacial layer, paragraph [0036]) disposed between at least a portion of the SiC body and the first layer of the multilayer laminate structure.
Regarding claim 11, Akram teaches the semiconductor device according to claim 10, wherein the interface dielectric layer comprises silicon oxide (silicon oxide interfacial layer, paragraph [0036]).
Regarding claim 16, Akram teaches a semiconductor device comprising a silicon carbide (SiC) body (paragraph [0018]), comprising: a drift region (120, fig. 1) of a first conductivity type (paragraph [0034]); a body region (130) of a second conductivity type paragraph [0034]); a source region (150) of the first conductivity type (paragraph [0035]); and a gate structure comprising a gate electrode (148, paragraph [0036]) and a gate dielectric (140, paragraph [0036]) that isolates the gate electrode from the SiC body, wherein: the gate structure is disposed adjacent to at least one of the source region, the body region or the drift region; the gate dielectric comprises a multilayer laminate structure comprising a first layer of a first dielectric material (142/146 or interfacial layer, paragraph [0037]) comprising silicon oxide (paragraph [0037]) and a second layer of a second dielectric material (paragraph [0038]); and the gate dielectric comprises layers of the first dielectric material as the first and the last layers of the multilayer laminate structure (fig. 1).
Claim(s) 1,4,15,18, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oka et al (PG Pub 2016/0260832 A1).
Regarding claim 1, Oka teaches a semiconductor device comprising a silicon carbide (SiC) body (paragraph [0128] and claim 13), comprising: a drift region (111, fig. 2, paragraph [0051]) of a first conductivity type; a body region (112, paragraph [0052]) of a second conductivity type; a source region (113, paragraph [0053]) of the first conductivity type; and a gate structure comprising a gate electrode (142, paragraph [0060]) and a gate dielectric (122, paragraph [0051], figs. 2 and 3) that isolates the gate electrode from the SiC body, wherein: the gate structure is disposed adjacent to at least one of the source region, the body region or the drift region, the gate dielectric comprises a multilayer laminate structure comprising a first layer (SiO2 131, paragraph [0078]) of a first dielectric material and a second layer (ZrON 132, paragraph [0059]) of a second dielectric material.
Regarding claim 4, Oka teaches the semiconductor device according to claim 1, wherein:the gate structure comprises a gate trench disposed in the SiC body and adj icent to the source region, the gate trench having a depth that is greater than a depth of the body region and that is less than a depth of the drift region, the gate dielectric is disposed in the gate trench on a sidewall of the gate trench an a bottom surface of the gate trench; and the gate electrode is disposed on the gate dielectric (fig. 2).
Regarding claim 15, Oka teaches the semiconductor device according to claim 1, wherein the thickness of layers in the multilayer laminate structure varies across the thickness of at least one of the gate dielectric or an interlayer dielectric (paragraphs [0070][0071]).
Regarding claim 18, Oka teaches the semiconductor device according to claim 15, wherein:the gate structure comprises a gate trench disposed in the SiC body and adjacent to the source region, the gate trench having a depth that is greater than a depth of the body region and that is less than a depth of the drift region; the gate dielectric is disposed in the gate trench on a sidewall of the gate trench and a bottom surface of the gate trench; and the gate electrode is disposed on the gate dielectric (figs. 2 and 3).
Regarding claim 19, Oka teaches (see claim 1) a method for manufacturing a semiconductor device including a silicon carbide (SiC) body, wherein the SiC body comprises a drift region of a first conductivity type, a body region of a second conductivity type, and a source region of the first conductivity type; and wherein the SiC body is provided with a gate structure comprising a gate electrode and a gate dielectric that isolates the gate electrode from the SiC body, wherein the gate structure is disposed adjacent to the source region, the body region and the drift region; wherein the gate dielectric is deposited on parts of the SiC body in a multilayer laminate structure comprising a first layer of a first dielectric material and a second layer of a second dielectric material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akram et al (PG Pub 2016/0343823 A1) as applied to claim 1 above, and further in view of Shimizu et al (PG Pub 2017/0077288 A1).
Regarding claim 12, Akram remains as applied in claim 1.
Akram does not teach the first dielectric material and the second dielectric material have a band gap lower than 7.0 eV.
Akram teaches the first and second dielectric materials may be TiO and ZrO (paragraph [0038]); Shimizu teaches TiO and ZrO have a band gap lower than 7.0 eV (fig. 8). Thus, it is inherent in Akram device that the first dielectric material and the second dielectric material have a band gap lower than 7.0 eV.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akram et al (PG Pub 2016/0343823 A1) as applied to claim 1 above, and further in view of Siddiqui, A et al 2021, High-k dielectrics for 4H-silicon carbide: present status and future perspectives', Journal of Materials Chemistry C, 9, pp. 5055-5081, a reference cited by Applicant.
Regarding claim 13, Akram remains as applied in claim 1.
Akram does not teach the first dielectric material has an offset to the conduction band of the SiC body material of at least 1.0 eV; and at least one of: the second dielectric material has an offset to the valence band of the SiC body material of at least 1.0 eV; or the first dielectric material has an offset to the valence band of the SiC body material of at least 1.0 eV and the second dielectric material has an offset to the conduction band of the SiC body material of at least 1.0 eV.
Akram teaches the first and second dielectric materials to be SiO2 and AlO (paragraphs [0037][0038]), respectively.
In the same field of endeavor, Siddiqui teaches SiO2 has an offset to the conduction band of the SiC body material of at least 1.0 eV (fig. 1) and AlO has an offset to the valence band of the SiC body material of at least 1.0 eV (fig. 1).
Thus, it is inherent in Akram device that the first dielectric material has an offset to the conduction band of the SiC body material of at least 1.0 eV; and at least one of: the second dielectric material has an offset to the valence band of the SiC body material of at least 1.0 eV; or the first dielectric material has an offset to the valence band of the SiC body material of at least 1.0 eV and the second dielectric material has an offset to the conduction band of the SiC body material of at least 1.0 eV.
Allowable Subject Matter
Claims 2,3,5-7,14,17,20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach
“the first dielectric material and the second dielectric material have a dielectric constant (k value) of 4 or higher; and at least one of the first dielectric material has an at least 0.3 eV higher conduction band offset and an at least 0.3 eV lower valence band offset than the second dielectric material or the second dielectric material has an at least 0.3 eV higher conduction band offset and an at least 0.3 eV lower valence band offset than the first dielectric material” (claim 2);
“the first dielectric material has a high conduction band offset but low valence band offset and the second dielectric material has a low conduction band offset but high valence band offset; or the second dielectric material has a high conduction band offset but low valence band offset and the first dielectric material has a low conduction band offset but high valence band offset” (claim 3);
“the interlayer dielectric comprises an interlayer multilayer laminate structure comprising a first layer of a first dielectric material and a second layer of a second dielectric material; and the first dielectric material and the second dielectric material of the interlayer dielectric have a dielectric constant (k value) of 4 or higher, wherein at least one of: the first dielectric material has an at least 0.3 eV higher conduction band offset and an at least 0.3 eV lower valence band offset than the second dielectric material; or the first dielectric material has a high conduction band offset but low valence band offset and the second dielectric material has a low conduction band offset but high valence band offset” (claim 5);
“the interlayer dielectric comprises an interlayer multilayer laminate structure comprising a first layer of a first dielectric material and a second layer of a second dielectric material; and the first dielectric material and the second dielectric material of the interlayer dielectric have a dielectric constant (k value) of 4 or higher, wherein at least one of:the first dielectric material has an at least 0.3 eV higher conduction band offset and an at least 0.3 eV lower valence band offset than the second dielectric material; or the first dielectric material has a high conduction band offset but low valence band offset and the second dielectric material has a low conduction band offset but high valence band offset” (claim 6);
“an interlayer dielectric isolates the gate electrode from the source metal; the interlayer dielectric comprises a first layer of a first dielectric material comprising silicon oxide and a second layer of a second dielectric material; at least one of the first dielectric material or the second dielectric material of the interlayer dielectric having a dielectric constant (k value) of 4 or higher;…and the interlayer dielectric comprises layers of the first dielectric material as the first and the last layers of the multilayer laminate structure” (claim 7);
“at least one of an interlayer dielectric or the gate dielectric has an overall k value higher than silicon oxide (SiO2),the semiconductor device further comprising: a multilayer laminate structure comprising a first layer of a first dielectric material having a band gap lower than 7.0 eV and a second layer of a second dielectric material having a band gap lower than 7.0 eV, wherein the first dielectric material has an offset to the conduction band of the SiC body material or source metal of at least 0.8 eV and the second dielectric material has an offset to the valence band of the SiC body material or source metal of at least 0.8 eV” (claim 14);
“the multilayer laminate structure comprises a third dielectric material layer comprising at least one of a Si- based material, an Al-based material, or a high-k dielectric material” (claim 17) and “the gate dielectric comprises a multilayer laminate structure comprising a first layer of a first dielectric material and a second layer of a second dielectric material” (claim 16);
“the first dielectric material and the second dielectric material have a dielectric constant (k value) of 4 or higher; the first dielectric material has an at least 0.3 eV higher conduction band offset and an at least 0.3 eV lower valence band offset than the second dielectric material; the second dielectric material has an at least 0.3 eV higher conduction band offset and an at least 0.3 eV lower valence band offset than the first dielectric material;the first dielectric material comprises silicon oxide and the second dielectric material has a dielectric constant (k value) of 4 or higher; the thickness of the layers of the first dielectric material is at most 5 nm; and the interlayer dielectric comprises layers of the first dielectric material as the first and the last layers of the multilayer laminate structure” (claim 20).
Conclusion
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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