Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 407, 409. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,2,3,4,5,6,7,9,10, 20, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1).
Regarding independent claim 1, Eijiri teaches a photoelectric conversion apparatus ({0110}, “…converts entering light into an electric signal by photoelectric conversion…”) comprising: a semiconductor layer having a first surface and a second surface (Fig. 1, 11, 11S1, 11S2; [0121], “The semiconductor substrate 11 has the first surface 11S1 and the second surface 11S2…”); an avalanche photodiode arranged in the semiconductor layer (Fig. 1, 14, 12X; [0126], “The multiplier 14 avalanche-multiplies the carriers…”); a Schottky barrier diode formed in a contact portion with the semiconductor layer (Fig. 1, 54; [0117], “For example, in addition to the clamping diode, it is possible to use a Schottky barrier diode, or the like, as the first clamping element 54.”); and a wiring structure arranged on a side of the second surface (Fig. 1, 18; [0123], “The semiconductor layer 15 and the multilayer wiring layer 18 are laminated in order on the first surface 11S1…” (The first surface in Eijiri corresponds to the second surface in the application)).
However, Eijiri does not teach an electrode film arranged to contact the first surface.
However, in the same field of endeavor, Cha teaches an electrode film arranged to contact the first surface (Fig. 1A, 16b; [0054], “…the second electrode 16b is provided on an upper surface…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of Eijiri, specifically the Schottky barrier diode, with the electrode film contacting the upper surface of Cha, so as to create a reverse bias in the APD when a voltage is applied.
Regarding dependent claim 2, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 1, and further teaches wherein light from an outside enters the semiconductor layer via the first surface (Fig. 1, 13; [0125], “The light receiving section 13 performs photoelectric conversion that absorbs light entering from side of the second surface 11S2 of the semiconductor substrate 11…”).
Regarding dependent claim 3, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 2. However, as previously combined, they do not teach wherein the avalanche photodiode is arranged between the second surface and the Schottky barrier diode.
However, Cha further teaches wherein the avalanche photodiode is arranged between the second surface and the Schottky barrier diode (Fig. 1A, 20, 10; [0054], “…between the cathode of the avalanche photodiode 10 and the cathode of the quenching diode 20 therethrough.”, [0066], “The quenching diode 20 of FIG. 1 may be implemented as a Schottky diode as illustrated in FIG. 9.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Cha’s diode arrangement with the apparatus as described by the combination of Eijiri and Cha so as to output a voltage between the the APD and the SBD (Cha, [0054]).
Regarding dependent claim 4, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 2. However, as previously combined, they do not teach wherein in an orthogonal projection to the second surface, the avalanche photodiode and the Schottky barrier diode overlap each other.
However, Cha further teaches wherein in an orthogonal projection to the second surface, the avalanche photodiode and the Schottky barrier diode overlap each other ([0055], “The avalanche photodiode 10 has a PIN photodiode structure composed of the first p-type semiconductor layer 11, the first i-type semiconductor layer 12, and the first n-type semiconductor layer 13.”, [0066], “…a plurality of Schottky diodes may be formed on the first n-type semiconductor layer 13…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Cha’s diode arrangement with the apparatus as described by the combination of Eijiri and Cha so as to output a voltage between the the APD and the SBD (Cha, [0054]), and to increase the voltage (Cha, [0066]).
Regarding dependent claim 5, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 2. However, as previously combined, they do not teach wherein the avalanche photodiode and the Schottky barrier diode are series-connected via a depletion region.
However, Cha further teaches wherein the avalanche photodiode and the Schottky barrier diode are series-connected via a depletion region (Fig. 1A, 15,13; [0065], “…the second p-type semiconductor layer 15 is provided only on a portion of the upper surface of the first n-type semiconductor layer 13”, “…a depletion layer is formed at the P-N junction thereof…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Cha’s diode arrangement and depletion region with the apparatus as described by the combination of Eijiri and Cha so as to have a “high response speed” (Cha, [0055]).
Regarding dependent claim 6, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 2, and further teaches wherein the wiring structure includes a first reflection layer configured to reflect light having passed through the semiconductor layer and entering the wiring structure (Fig. 7A, 41; [0156], “As a result, light that passes through the light receiving section 13 without being absorbed is reflected by the reflection layer 41…”).
Regarding dependent claim 7, Eijri, as previously modified by Cha, teaches the apparatus according to claim 6, and further teaches wherein the wiring structure includes an insulating layer arranged between the second surface and the first reflection layer (Fig. 7A, 182; [0133], “The inter-layer insulating layer 182 includes…”).
Regarding dependent claim 9, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 6, and further teaches wherein a dimension of the first reflection layer in a direction along the second surface is larger than a dimension of the electrode film in the direction along the second surface (Fig. 7A, 41, 16).
Regarding dependent claim 10, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 6. Furthermore, Eijiri further teaches the third semiconductor region includes a portion arranged between the second surface and the second semiconductor region to surround a side surface of the first semiconductor region (Fig. 1, 14X, 14Y), and a portion arranged between the first semiconductor region and the second semiconductor region (Fig. 1, 15, 14Y, 14X), and a dimension of the first reflection layer in a direction along the second surface is larger than a dimension of the third semiconductor region in the direction along the second surface (Fig. 7A, 41, 14X). However, as previously combined, they do not teach wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type arranged between the second surface and the second semiconductor region.
However, Cha further teaches wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type (Fig. 1A, 11; [0055], “The avalanche photodiode 10 has a PIN photodiode structure composed of the first p-type semiconductor layer 11…”), a second semiconductor region of a second conductivity type (Fig. 1A, 13; [0055], “…and the first n-type semiconductor layer 13.”), and a third semiconductor region of the first conductivity type arranged between the second surface and the second semiconductor region (Fig. 1A, 15; [0054], “…the second electrode 16b is provided on an upper surface of the second p-type semiconductor layer 15.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Cha’s regions of the APD with the apparatus as described by the combination of Eijiri and Cha so as to have a “high response speed” (Cha, [0055]).
Regarding dependent claim 20, Eijri, as previously modified by Cha, teaches the apparatus according to claim 1, and further teaches the third semiconductor region includes a portion arranged between the second surface and the second semiconductor region to surround a side surface of the first semiconductor region (Fig. 1, 15; [0161], “Next, the semiconductor layer 15 including, for example, silicon (Si), is formed on the first surface…”), and a portion arranged between the first semiconductor region and the second semiconductor region (Fig. 1, 15, 14, 16 (Section 15 surrounds section 14Y and separates section 16 from section 14X)). However, as previously combined, they do not teach wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type arranged between the second surface and the second semiconductor region.
However, Cha further teaches wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type (Fig. 1A, 14; [0054], “…a second i-type semiconductor layer 14…”), a second semiconductor region of a second conductivity type (Fig. 1A, 13; [0054], “…a first n-type semiconductor layer 13…”), and a third semiconductor region of the first conductivity type arranged between the second surface and the second semiconductor region (Fig. 1A, 12; [0054], “…a first i-type semiconductor layer 12…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine Cha’s regions of the APD with the apparatus as described by the combination of Eijiri and Cha so as to have a “high response speed” (Cha, [0055]).
Regarding dependent claim 30, Eijiri, as previously modified by Cha, teaches a photoelectric conversion system, comprising: the photoelectric conversion apparatus defined in claim 1, and further teaches a signal processing unit configured to process a signal output from the photoelectric conversion apparatus ([0146], “…a readout circuit that outputs a pixel signal based on electric charges outputted from…a logic circuit including a vertical driving circuit, a horizontal driving circuit, and an output circuit, or the like. It is to be noted that the logic circuit may include a column signal processing circuit.”).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1) and Ono (US 20230040906 A1).
Regarding dependent claim 8, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 6. However, neither teach wherein in a case where λ represents a wavelength of the light entering from the outside and m1 represents a natural number, an optical path length between the electrode film and the first reflection layer is given by m1 × λ/2 ± λ/8.
However, in the same field of endeavor, Ono teaches wherein in a case where λ represents a wavelength of the light entering from the outside and m1 represents a natural number, an optical path length is given by m1 × λ/2 ± λ/8 ([107], “
0.05
+
m
2
≤
L
λ
λ
≤
0.35
+
m
/
2
”; Rearranging this gives an equation
m
λ
2
+
λ
/
20
≤
L
λ
≤
m
λ
2
+
7
λ
/
20
, in which
λ
8
is between the values
λ
20
and
7
λ
2
).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri and Cha with the equation given by Ono to describe the intensified light through optical interference ([0107], “…and as a result, the light is intensified by the optical interference effect…”).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1) and Nomura (US 20090283758 A1).
Regarding dependent claim 11, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 6. However, as previously combined, they do not teach further comprising a light shielding film, wherein the light shielding film is arranged so that the first surface is located between the second surface and the light shielding film; the light shielding film includes an opening that defines light entering the Schottky barrier diode, and a dimension of the first reflection layer in a direction along the second surface is larger than a dimension of the opening in the direction along the second surface.
However, in the same field of endeavor, Nomura teaches further comprising a light shielding film (Fig. 12, 14; [0233], “…where a light-shielding film 14 having provided therein an opening is formed on the photoelectric conversion part…”), wherein the light shielding film is arranged so that the first surface is located between the second surface and the light shielding film (Fig. 12, 14, 13, 1; (given that the surfaces define a semiconductor region in the application, and in Nomura, the shielding film is disposed above the semiconductor region, this means the first surface is between it and the second surface.)); the light shielding film includes an opening that defines light entering the Schottky barrier diode (Fig. 12, 14, 11; [0233], “…where a light-shielding film 14 having provided therein an opening is formed on the photoelectric conversion part…”), and a dimension of the first reflection layer in a direction along the second surface is larger than a dimension of the opening in the direction along the second surface.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri and Cha with the light shielding film of Nomura so as to limit “the light-receiving region” (Nomura, [0233]).
Claim(s) 12 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1) and Kobayashi (US 20110122500 A1).
Regarding dependent claim 12, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 6. However, as previously combined, they do not teach further comprising a second reflection layer, wherein the second reflection layer is arranged so that the first surface is located between the second surface and the second reflection layer.
However, in the same field of endeavor, Kobayashi teaches further comprising a second reflection layer, wherein the second reflection layer is arranged so that the first surface is located between the second surface and the second reflection layer (Fig. 6, 14; [0061], “…and a second reflection layer 14. The reflection layers are disposed to sandwich the single light emitting function layer 15 and to have areas not overlapping each other in plan view.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri and Cha with the second reflection layer of Kobayashi so as to reflect light back into the system.
Regarding dependent claim 15, Eijiri, as previously modified by Cha and Kobayashi, teaches the apparatus according to claim 12. However, as previously combined, they do not teach wherein the second reflection layer has an antireflection structure on the surface which the light enters from the outside.
However, Kobayashi further teaches wherein the second reflection layer has an antireflection structure on the surface which the light enters from the outside (Fig. 6, 79; [0081], “All the respective layers constituting the above-mentioned sealing layer 79 are made of transparent materials, and thus there is no obstacle to transmission of the light emitted from the side of the upper surface 3.” (The structure is not explicitly named, but since the sealing layer lets the light go through, it acts as an antireflection structure.)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the antireflection structure of Kobayashi with the apparatus as described by the combination of Eijiri, Cha, and Kobaysahi so that “there is no obstacle to transmission of the light emitted from the side of the upper surface.” (Kobayashi, [0081]).
Regarding dependent claim 16, Eijiri, as previously modified by Cha and Kobayashi, teaches the apparatus according to claim 12. However, as previously combined, they do not teach further comprising a sealing layer arranged between the semiconductor layer and the second reflection layer.
However, Kobayashi further teaches further comprising a sealing layer arranged between the semiconductor layer and the second reflection layer (Fig. 6, 79, 14; [0081], “A sealing layer 79 is formed as an upper layer of the cathode 19, that is, between the cathode 19 and the counter substrate 11, with the later-described second reflection layer 14 interposed…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the sealing layer of Kobayashi with the apparatus as described by the combination of Eijiri, Cha, and Kobaysahi to fill the space containing the second reflection layer (Kobayashi, [0081]).
Regarding dependent claim 17, Eijiri, as previously modified by Cha and Kobayashi, teaches the apparatus according to claim 16 and further teaches further comprising a microlens arranged to cover the second reflection layer (Fig. 1, P; [0152], “On the second surface 11S2 that is the light entering surface of the semiconductor substrate 11 is provided a microlens…”).
Regarding dependent claim 18, Eijiri, as previously modified by Cha and Kobayashi, teaches the apparatus according to claim 12. However, as previously combined, they do not teach further comprising a sealing layer, wherein the sealing layer is arranged so that the first surface is located between the second surface and the sealing layer, and the sealing layer has a third surface on an opposite side of the first surface, and the second reflection layer is arranged in the sealing layer.
However, Kobayashi further teaches further comprising a sealing layer, wherein the sealing layer is arranged so that the first surface is located between the second surface and the sealing layer, and the sealing layer has a third surface on an opposite side of the first surface, and the second reflection layer is arranged in the sealing layer (Fig. 6, 79, 14, [0081], “ A sealing layer 79 is formed as an upper layer of the cathode 19, that is, between the cathode 19 and the counter substrate 11, with the later-described second reflection layer 14 interposed…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the sealing layer of Kobayashi with the apparatus as described by the combination of Eijiri, Cha, and Kobaysahi to fill the space containing the second reflection layer (Kobayashi, [0081]).
Regarding dependent claim 19, Eijiri, as previously modified by Cha and Kobayashi, teaches the apparatus according to claim 18 and further teaches further comprising a microlens arranged to cover the second reflection layer (Fig. 1, P; [0152], “On the second surface 11S2 that is the light entering surface of the semiconductor substrate 11 is provided a microlens…”).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1), Kobayashi (US 20110122500 A1), and Ono (US 20230040906 A1).
Regarding dependent claim 13, Eijiri, as previously modified by Cha and Kobayashi, teaches the apparatus according to claim 12. However, as previously combined, they do not teach wherein in a case where λ represents a wavelength of the light entering from the outside and m2 represents a natural number, an optical path length between the electrode film and the second reflection layer is given by m2 × λ/2 ± λ/8.
However, in the same field of endeavor, Ono teaches wherein in a case where λ represents a wavelength of the light entering from the outside and m2 represents a natural number, an optical path length between the electrode film and the second reflection layer is given by m2 × λ/2 ± λ/8 ([107], “
0.05
+
m
2
≤
L
λ
λ
≤
0.35
+
m
/
2
”; Rearranging this gives an equation
m
λ
2
+
λ
/
20
≤
L
λ
≤
m
λ
2
+
7
λ
/
20
, in which
λ
8
is between the values
λ
20
and
7
λ
2
).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri, Cha, and Kobayashi with the equation given by Ono to describe the optical path length within the device.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1), Kobayashi (US 20110122500 A1), and Kimura (US 20240172521 A1).
Regarding dependent claim 14, Eijri, as previously modified by Cha and Kobayashi, teaqches the apparatus according to claim 12. However, as previously combined, they do not teach wherein in a case where λ represents a wavelength of the light entering from the outside and m1 and m2 represent natural numbers, an optical path length between the electrode film and the first reflection layer is given by m1 × λ/4, and an optical path length between the electrode film and the second reflection layer is given by m2 × λ/4.
However, in the same field of endeavor, Kimura teaches wherein in a case where λ represents a wavelength of the light entering from the outside and m1 and m2 represent natural numbers, an optical path length between the electrode film and the first reflection layer is given by m1 × λ/4, and an optical path length between the electrode film and the second reflection layer is given by m2 × λ/4 ([0233], “…the optical path length from the conductive layer 171 functioning as a reflective electrode to the light-emitting layer is preferably set to an odd multiple of λ/4.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri, Cha, and Kobayashi with the equation given by Kimura to describe the optical path length within the device.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1) and Suzuki (US 20120182540 A1).
Regarding dependent claim 21, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 20. However, as previously combined, they do not teach wherein in a planar view, an area of the first semiconductor region is smaller than an area of the electrode film.
However, in the same field of endeavor, Suzuki teaches wherein in a planar view, an area of the first semiconductor region is smaller than an area of the electrode film (Fig. 17, 9a, 9b, PG; [0102], “…the area of the third semiconductor regions 9a, 9b is also set smaller than the area of the photogate electrode PG.”).
Therefore, it would have been obvious to one of ordinary skill in the art to combine the photoelectric conversion device as described by the combination of Eijiri and Cha with the disclosure of Suzuki of a semiconductor region smaller than the electrode so as to reduce the area of the semiconductor region.
Claim(s) 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1), and Toyoda (US 20220190171 A1).
Regarding dependent claim 22, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 20. However, as previously combined they do not teach wherein a first potential is supplied to the second semiconductor region, a second potential is supplied to the first semiconductor region, a third potential is supplied to the electrode film, and a potential becomes higher in an order of the third potential, the first potential, and the second potential.
However, in the same field of invention, Toyoda teaches wherein a first potential is supplied to the second semiconductor region (Fig. 8, 72, 11; [0051], “The second potential terminal 72 is connected to the semiconductor region 11.”), a second potential is supplied to the first semiconductor region (Fig. 3, 4; [0043], “The second semiconductor region 4, which is in contact with the high specific resistance layer 2, is led to have a high potential…”), a third potential is supplied to the electrode film (Fig. 1, 73, 10a; [0077], “A third potential terminal 73 is connected to the electrode 10a.”), and a potential becomes higher in an order of the third potential, the first potential, and the second potential ([0043], ““The second semiconductor region 4, which is in contact with the high specific resistance layer 2, is led to have a high potential…”, [0077], “The third potential applied may be the same VCC potential as the first potential…”, [0038], “is applied to the second potential terminal 72 as a second potential lower than the first potential”, (two potentials are the same, while one delivers a high potential to a semiconductor region, therefore they are in increasing order.)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri and Cha with the potential supply of Toyoda to set the semiconductor regions at different potentials.
Regarding dependent claim 23, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 20. Eijiri further teaches further comprising a fourth semiconductor region of the second conductivity type electrically connected to the second semiconductor region and extending between the first surface and the second surface in a direction orthogonal to the first surface (Fig. 1, 111; [0123], “The semiconductor substrate 11 has a p-well (p) 111 common to the plurality of unit pixels P.”). However, as previously combined, they do not teach wherein a potential is applied to the second semiconductor region via the fourth semiconductor region.
However, in the same field of endeavor, Toyoda teaches wherein a potential is applied to the second semiconductor region (Fig. 8, 72, 11; [0051], “The second potential terminal 72 is connected to the semiconductor region 11.”).
Therefore, it would have been obvious to one of prior skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of the combination of Eijiri and Cha, especially the fourth semiconductor region on the sides, with the potential applied to a second semiconductor region of Toyoda so as to supply a potential through Eijiri’s fourth semiconductor region.
Regarding dependent claim 24, Eijiri, as previously modified by Cha and Toyoda, teaches the apparatus according to claim 23 and further teaches wherein the fourth semiconductor region is arranged to surround the first semiconductor region, the second semiconductor region, and the third semiconductor region (Fig. 1, 111).
Regarding dependent claim 25, Eijiri, as previously modified by Cha and Toyoda, teaches the apparatus according to claim 24, and further teaches further comprising a fifth semiconductor region of the second conductivity type arranged between the second surface and the fourth semiconductor region (Fig. 1, 113; [0131], “The p-type semiconductor region (p+) 113 further extends along the second surface 11S2 of the semiconductor substrate 11.”).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1), Toyoda (US 20220190171 A1), and Kubota (US 20220163410 A1).
Regarding dependent claim 26, Eijiri, as previously modified by Cha and Toyoda, teaches the apparatus according to claim 25. However, as previously combined, they do not teach further comprising a pinning film configured to cover the first surface to surround the electrode film.
However, in the same field of endeavor, Kubota teaches further comprising a pinning film configured to cover the first surface to surround the electrode film (Fig. 3, 41, 40; [0189], “For example, CoFe/IrMn is film-formed as the pinned film/pinning film (ferromagnetic film/antiferromagnetic film) above the lower electrode film 63.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus of Eijiri, as combined with Cha and Toyoda, with the pinning film of Kubota so as to make an antiferromagnetic surface (Kubota, [0135]).
Claim(s) 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1) and Takatsuka (US 20220120868 A1).
Regarding dependent claim 27, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 1, and further teaches further comprising a plurality of pixels (Fig. 2, 100A; [0108], The photodetection device 1 includes, for example, a pixel array section 100A in which a plurality of unit pixels P is disposed in an array in a row direction and in a column direction.”), wherein the plurality of pixels includes at least one first pixel and at least one second pixel ([0108], “…each of the unit pixels P…”), and wherein the plurality of pixels includes at least one first pixel and at least one second pixel, the at least one first pixel includes the avalanche photodiode and the Schottky barrier diode (Fig.1, P, 14, Fig. 3A, 54; [0107], “unit pixel P of the photodetection device 1 illustrated in FIG. 1.”, [0109], “As illustrated in FIG. 3A, the unit pixel P includes… a clamping circuit 50…”, [0115], “…the clamping circuit 50 includes…a first clamping element 54…”, [0117], “…it is possible to use a Schottky barrier diode, or the like, as the first clamping element 54.”, [0126], “The multiplier 14 avalanche-multiplies the carriers…”). However, as previously combined, they do not teach and the at least one second pixel includes a second avalanche photodiode arranged in the semiconductor layer, and includes no Schottky barrier diode.
However, in the same field of endeavor, Takatsuka teaches the at least one second pixel includes a second avalanche photodiode arranged in the semiconductor layer, and includes no Schottky barrier diode (Fig. 2, 31; [0049], “Each of the pixels 21 includes, for example, an APD 31…” (There is no mention of a Schottky barrier diode in Takatsuka)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion apparatus as described by the combination of Eijiri and Cha with the second pixel with an avalanche photodiode and no Schottky barrier diode of Takatsuka, so as to have color-sensing pixels.
Regarding dependent claim 28, Eijiri, as previously modified by Cha and Takatsuka, teaches the apparatus according to claim 27. However, as previously combined, they do not teach wherein the at least one second pixel includes a pixel having sensitivity to light in a red wavelength range, a pixel having sensitivity to light in a green wavelength range, and a pixel having sensitivity to light in a blue wavelength range.
However, Takatsuka further teaches wherein the at least one second pixel includes a pixel having sensitivity to light in a red wavelength range, a pixel having sensitivity to light in a green wavelength range, and a pixel having sensitivity to light in a blue wavelength range (Fig. 14, 21V; [0105], “The Pixel 21V is a pixel that receives light beams in a red wavelength region, a green wavelength region, and a blue wavelength region to generate a light-receiving signal…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the colored pixels of Takatsuka with the apparatus as described by the combination of Eijiri, Cha, and Takatsuka so as to receive light of a wavelength in the visible spectrum (Takatsuka, [0105]).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eijiri (US 20250120213 A1) in further view of Cha (US 20180277689 A1) and Sekiguchi (US 20060007092 A1).
Regarding dependent claim 29, Eijiri, as previously modified by Cha, teaches the apparatus according to claim 1. However, as previously combined, they do not teach further comprising a potential supply circuit configured to supply a potential to the electrode film of the Schottky barrier diode, wherein the potential supply circuit supplies, to the electrode film, a potential corresponding to a mode selected from a plurality of modes.
However, in the same field of endeavor, Sekiguchi teaches further comprising a potential supply circuit configured to supply a potential to the electrode film (Fig. 7, 9; [0113], “Both the common electrode potential outputted from the common electrode potential generating circuit 10 and a standby potential are inputted to the selecting circuit 11, and then, the selecting circuit 11 selects any one of these two input potentials to output the selected potential to the common electrode.”), wherein the potential supply circuit supplies, to the electrode film, a potential corresponding to a mode selected from a plurality of modes ([0113], “The common electrode potential generating circuit 10 generates common electrode potentials in the partially scanning periods when the normal display mode is selected and the partial display mode is selected.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the photoelectric conversion device described by the combination of Eijiri and Cha with the potential supply circuit of Sekiguchi, so as to “output the selected potential to the…electrode” (Sekiguchi, [0113]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20230069887 A1, which describes a photoelectric conversion apparatus.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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