DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fail to show in individual or in combination of the limitations “a LO signal distribution component, wherein the LO signal distribution component is configured to distribute the LO signal to the additional BF chip and the third BF chip in the first beamforming configuration and distribute the additional LO signal to the BF chip and the third BF chip in the second beamforming configuration” as disclosed in independent claim 13.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fail to show in individual or in combination of the limitations “the LO signal and the fourth LO signal have a first common frequency; and the additional LO signal and the fifth LO signal have a second common frequency” as disclosed in independent claim 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-12, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Buliga (US 20190319631 A1) in view of Kahrizi et al. (US 20200388916 A1).
Regarding claim 1, Buliga teaches a phased array antenna system comprising: a plurality of antenna elements (Fig. 3); a reference clock (Fig. 3); and a beamformer (BF) chip (Figs. 3-4, each PLL module 350) comprising: a phase-locked loop (PLL) configured to output a local oscillator (LO) signal by a LO signal output based on the reference clock (Figs. 3-4, and Par. 50, reference clock signal is received by each of a plurality of PLL modules 350a to 350n (generally referred to as PLL module 350) and each PLL module 350a to 350n outputs a respective output LO signal); and a LO signal input/output (IO) port configured to output the LO signal from the BF chip in a first beamforming configuration and to receive an additional LO signal in a second beamforming configuration (Figs. 3-4 and Par. 51, each PLL module 350 provides a signal to (i.e. output LO signal) and receives a signal (i.e. receive an additional LO signal) from immediately adjacent PLL modules 350 in the loop, e.g. PLL module 350a provides a local LO signal to adjacent downstream PLL module 350b (i.e. first beamforming configuration) and receives an adjacent LO signal from adjacent upstream PLL module 350n (i.e. second beamforming configuration).
Buliga fails to teach each PLL module 350 as taught above is a chip/DBF chip. However, it cannot be considered new or novel in the presence Kahrizi. Kahrizi teaches each PLL is included in each DBF chip (Par. 21).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Kahrizi into the modified Buliga to reduce weight and size.
Regarding claims 9-10, the modified Buliga fails to teach claims 9-10.
However, the claim 9 cannot be considered new or novel in the presence Kahrizi. Kahrizi teaches the phased array antenna system of claim 1, wherein the BF chip further comprises a frequency multiplier (Fig. 2, frequency multiplier 203) electrically coupled to generate an upscaled LO signal (Par. 32), wherein: a frequency of the upscaled LO signal is a first multiple of a frequency of the LO signal in the first beamforming configuration (Fig. 2, output of frequency multiplier 203 comprises an input to mixer 242 to up convert signal (frequency of the upscaled LO signal) in first DBF chip (first beamforming configuration) and Pars. 29, 32, 62); the frequency of the upscaled LO signal is a second multiple of a frequency of the additional LO signal in the second beamforming configuration (Fig. 2, output of frequency multiplier 203 comprises an input to mixer 242 to up convert signal (frequency of the upscaled LO signal) in second DBF chip (second beamforming configuration) and Pars. 29, 32, 62); and wherein the first multiple of the frequency of the LO signal and the second multiple of the frequency of the additional LO signal are equal (Par. 22, a respective DBF chip of the plurality of DBF chips 106 is equal to each other).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Kahrizi into the modified Buliga for carrying signals to a frequency suitable for transmission.
Regarding claim 11, the modified Buliga further teaches the phased array antenna system of claim 1, further comprising: an additional BF chip (Figs. 3-4, each PLL module 350) comprising: an additional PLL configured to output the additional LO signal, by an additional LO signal output based on the reference clock (Figs. 3-4, and Par. 50, reference clock signal is received by each of a plurality of PLL modules 350a to 350n (generally referred to as PLL module 350) and each PLL module 350a to 350n outputs a respective output LO signal); and an additional LO signal IO port configured to output the additional LO signal from the additional BF chip in the first beamforming configuration and to receive the LO signal from the BF chip in the second beamforming configuration (Figs. 3-4 and Par. 51, each PLL module 350 provides a signal to (i.e. output LO signal) and receives a signal (i.e. receive an additional LO signal) from immediately adjacent PLL modules 350 in the loop, e.g. PLL module 350a provides a local LO signal to adjacent downstream PLL module 350b (i.e. first beamforming configuration) and receives an adjacent LO signal from adjacent upstream PLL module 350n (i.e. second beamforming configuration).
Regarding claim 12, the modified Buliga further teaches the phased array antenna system of claim 11, further comprising: a third BF chip (Figs. 3-4, each PLL module 350) comprising a third LO signal IO port configured to receive the LO signal from the BF chip in the first beamforming configuration and to receive the additional LO signal from the additional BF chip in the second beamforming configuration (Figs. 3-4 and Par. 51, each PLL module 350 provides a signal to (i.e. output LO signal) and receives a signal (i.e. receive an additional LO signal) from immediately adjacent PLL modules 350 in the loop, e.g. PLL module 350a provides a local LO signal to adjacent downstream PLL module 350b (i.e. first beamforming configuration) and receives an adjacent LO signal from adjacent upstream PLL module 350n (i.e. second beamforming configuration).
Regarding claim 14, the modified Buliga further teaches the phased array antenna system of claim 12, wherein the third BF chip comprises a third PLL coupled to the reference clock, wherein a third LO signal output of the third PLL is coupled to a third LO signal IO port (Figs. 3-4, and Par. 50, reference clock signal is received by each of a plurality of PLL modules 350a to 350n (generally referred to as PLL module 350) and each PLL module 350a to 350n outputs a respective output LO signal).
Regarding claim 16, the modified Buliga further teaches the phased array antenna system of claim 12, further comprising: a fourth BF chip (Figs. 3-4, each PLL module 350) comprising: a fourth LO signal IO port (Figs. 3-4); a fourth PLL (Figs. 3-4, each PLL module 350) configured to generate a fourth LO signal based on the reference clock (Figs. 3-4, and Par. 50, reference clock signal is received by each of a plurality of PLL modules 350a to 350n (generally referred to as PLL module 350) and each PLL module 350a to 350n outputs a respective output LO signal); and a fourth LO signal IO port configured to output the fourth LO signal in the first beamforming configuration and receive a fifth LO signal in the second beamforming configuration (Figs. 3-4 and Par. 51, each PLL module 350 provides a signal to (i.e. output LO signal) and receives a signal (i.e. receive an additional LO signal) from immediately adjacent PLL modules 350 in the loop, e.g. PLL module 350a provides a local LO signal to adjacent downstream PLL module 350b (i.e. first beamforming configuration) and receives an adjacent LO signal from adjacent upstream PLL module 350n (i.e. second beamforming configuration); and a fifth BF chip (Figs. 3-4, each PLL module 350) comprising: a fifth LO signal IO port (Figs. 3-4, each PLL module 350); a fifth PLL (Figs. 3-4, each PLL module 350) configured to generate a fifth LO signal based on the reference clock (Figs. 3-4, and Par. 50, reference clock signal is received by each of a plurality of PLL modules 350a to 350n (generally referred to as PLL module 350) and each PLL module 350a to 350n outputs a respective output LO signal); and a fifth LO signal IO port configured to output the fifth LO signal in the first beamforming configuration and receive the fourth LO signal in the second beamforming configuration (Figs. 3-4 and Par. 51, each PLL module 350 provides a signal to (i.e. output LO signal) and receives a signal (i.e. receive an additional LO signal) from immediately adjacent PLL modules 350 in the loop, e.g. PLL module 350a provides a local LO signal to adjacent downstream PLL module 350b (i.e. first beamforming configuration) and receives an adjacent LO signal from adjacent upstream PLL module 350n (i.e. second beamforming configuration).
Claims 2-6, 8, 15, 26 and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Buliga (US 20190319631 A1) in view of Kahrizi et al. (US 20200388916 A1) and in further view of Zanuso et al. (US 20170338940 A1).
Regarding claim 2, the modified Buliga fails to teach claim 2.
However, the feature of claim 2 cannot be considered new or novel in the presence Zanuso. Zanuso teaches the phased array antenna system of claim 1, further comprising: one or more LO signal selection components (Fig. 4A, PLL controller or PLL selector 440 or Fig. 14, selector 1440), wherein the one or more LO signal selection components are configured to couple the LO signal IO port to the LO signal output of the PLL in the first beamforming configuration and to disconnect the LO signal IO port from the LO signal output of the PLL in the second beamforming configuration (Figs. 4A, 14 and Pars. 84, 132-133, enable receive path (first beamforming configuration) and disable the transmit path (second beamforming configuration) “or” disable receive path (second beamforming configuration) and enable the transmit path (first beamforming configuration)).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Zanuso into the modified Buliga for maximizing the throughput in the communication.
Regarding claims 3-4, the modified Buliga fails to teach claims 3-4.
However, the feature of claims 3-4 cannot be considered new or novel in the presence Zanuso. Zanuso teaches the phased array antenna system of claim 1, wherein the PLL is configured to select an output frequency of the LO signal based on a mode signal (PLL controller/selector 440 controls/selects a frequency of a transmitter local oscillator signal LO.sub.Tx or a frequency of a receiver local oscillator signal LO.sub.Rx by frequency control words (FCW) (Figs. 4A, 14 and Pars. 84, 132-133), wherein the transmission frequency is different from the reception frequency (Par. 130); wherein: the mode signal comprises an enable signal (Pars. 84, 132-133); and the PLL is configured to selectively enable outputting the LO signal based on the enable signal (Pars. 84, 132-133).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Zanuso into the modified Buliga for maximizing the throughput in the communication.
Regarding claim 5, the modified Buliga fails to teach the phased array antenna system of claim 1, wherein, in the second beamforming configuration, the PLL is configured to continue generating the LO signal.
However, this feature cannot be considered new or novel in the presence Zanuso. Zanuso teaches enable receive path (continue generating the LO signal in second beamforming configuration) and disable the transmit path (first beamforming configuration) (Figs. 4A, 14 and Pars. 84, 132-133).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Zanuso into the modified Buliga for maximizing the throughput in the communication.
Regarding claim 6, the modified Buliga fails to teach the phased array antenna system of claim 1, wherein the first beamforming configuration comprises a transmitting (Tx) configuration and the second beamforming configuration comprises a receiving (Rx) configuration.
However, this feature cannot be considered new or novel in the presence Zanuso. Zanuso teaches enable receive path (first beamforming configuration) and disable the transmit path (second beamforming configuration) “or” disable receive path (second beamforming configuration) and enable the transmit path (first beamforming configuration) (Figs. 4A, 14 and Pars. 84, 132-133).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Zanuso into the modified Buliga for maximizing the throughput in the communication.
Regarding claim 8, the modified Buliga fails to teach the phased array antenna system of claim 1, wherein the first beamforming configuration comprises a receiving (Rx) configuration and the second beamforming configuration comprises a transmitting (Tx) configuration.
However, this feature cannot be considered new or novel in the presence Zanuso. Zanuso teaches enable receive path (first beamforming configuration) and disable the transmit path (second beamforming configuration) “or” disable receive path (second beamforming configuration) and enable the transmit path (first beamforming configuration) (Figs. 4A, 14 and Pars. 84, 132-133.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Zanuso into the modified Buliga for maximizing the throughput in the communication.
Regarding claim 15, the modified Buliga fails to teach the phased array antenna system of claim 14, wherein the third PLL is disabled based on a mode signal.
However, this feature cannot be considered new or novel in the presence Zanuso. Zanuso teaches enable receive path (first beamforming configuration) and disable the transmit path (second beamforming configuration) “or” disable receive path (second beamforming configuration) and enable the transmit path (first beamforming configuration) (Figs. 4A, 14 and Pars. 84, 132-133.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Zanuso into the modified Buliga for maximizing the throughput in the communication.
Regarding claim 26, method of claim 26 is performed by the apparatus of claims 1, 2 and 11. They recite similar limitations. Applicant is kindly advised to refer to rejection of claims 1, 2 and 11.
Regarding claims 28-29, method of claims 28-29 are performed by the apparatus of claims 3-4. They recite similar limitations. Applicant is kindly advised to refer to rejection of claims 3-4.
Regarding claims 30, method of claim 30 is performed by the apparatus of claims 12. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 12.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Buliga (US 20190319631 A1) in view of Kahrizi et al. (US 20200388916 A1), in further view of Zanuso et al. (US 20170338940 A1), and further in further view of Gonikberg (US 20130028246 A1).
Regarding claim 7, the modified Buliga fails to teach the phased array antenna system of claim 6, wherein a transmit beamformer section of the BF chip is configured to up-convert signals based on the LO signal in the transmitting (Tx) configuration and a receive beamformer section of the BF chip is configured to down-convert signals based on the additional LO signal in the receiving (Rx) configuration.
However, this feature is very well-known and cannot be considered new or novel in the presence Gonikberg. Gonikberg teaches the LO 207 provides local oscillation signals for use by transmitter 201 for up-conversion and by receiver 202 for down-conversion (Fig. 4 and Par. 33).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Gonikberg into the modified Buliga to shift signals between different range so they can be transmitted efficiently and processed easily.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Buliga (US 20190319631 A1) in view of Kahrizi et al. (US 20200388916 A1) and in further view of Hung et al. (US 20130202002 A1).
Regarding claim 18, the modified Buliga fails to teaches the phased array antenna system of claim 1, wherein the BF chip receives the reference clock from a reference clock signal distribution network.
However, this feature cannot be considered new or novel in the presence Hung. Hung teaches the PLL 222 is configured to receive a clock signal from a network reference clock 210 (Fig. 2, Pars. 25-27, and claim 4).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Hung into the modified Buliga for aligning or synchronizing system clock.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Buliga (US 20190319631 A1) in view of Kahrizi et al. (US 20200388916 A1) and in further view of Clarke et al. (US 20020129661 A1).
Regarding claim 27, the modified Buliga fails to teaches the method of claim 26, wherein the first PLL and the second PLL remain active during the first BF configuration and the second BF configuration.
However, this feature cannot be considered new or novel in the presence Clarke. Clark teaches enable the first PLL and enable the second PLL (Pars. 17-19).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Clark into the modified Buliga to assist lock-in the signal.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Buliga (US 20190319631 A1) in view of Kahrizi et al. (US 20200388916 A1) and in further view of Amel et al. (US 20200366457 A1).
Regarding claim 31, the modified Buliga fails to teaches the method of claim 30, wherein a third PLL of the third BF chip is disabled based on a third mode signal of the third PLL.
However, this feature cannot be considered new or novel in the presence Amel. Amel teaches disable command to the selection circuit 126 to disable the HP-PLL 124 (Par. 20).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching by Amel into the modified Buliga for selecting different operating modes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Cao et al. US 20120007640 A1
Nilsson US 20190131979 A1
Gao (US 20220116193 A1)
Mehrnia et al. (US 10938465 B1)
Mehrnia et al. US 10944442 B1
Harel et al. (US 20150124634 A1)
Tertinek (US 10511311 B1)
Jakobsson US 20190089448 A1)
Sandner et al. US 20080290953 A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CINDY HUYEN TRANDAI whose telephone number is (571)270-1914. The examiner can normally be reached 8am -4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley L. Kim can be reached at 571-272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Cindy Trandai/ Primary Examiner, Art Unit 2648
6/9/2026
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