Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 05/15/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 3, 4, 13, 14, 15, and 16 are objected to because of the following informalities: Regarding claim 3, in line 6, “the resonant tank” appears that it should read as “a resonant tank”. Regarding claim 4, in line 3, “in half cycle” appears that it should read as “during a half cycle”;in line 5-6, “in half cycle” appears that it should read as “during a half cycle”. Regarding claim 13, in line 2, “a control signal” appears that it should read as “the control signal”;in line 3-4, “an output current change rate” appears that it should read as “the output current change rate”. Regarding claim 14, in line 2, “an analog reference voltage” appears that it should read as “the analog reference voltage”;in line 8, “the current output current signal” appears that it should read as “a current output current signal”;in line 9, “the historical output current signal” appears that it should read as “a historical output current signal”. Regarding claim 15, in line 2, “a second comparison reference value” appears that it should read as “the second comparison reference value”;in line 3, “an output current feedforward coefficient” appears that it should read as “the output current feedforward coefficient”;in line 4-5, “the input voltage sampling signal” appears that it should read as “an input voltage sampling signal”. Regarding claim 16, in line 2, “a second comparison reference value” appears that it should read as “the second comparison reference value”;in line 3, “an output current feedforward coefficient” appears that it should read as “the output current feedforward coefficient”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Regarding claim 17, “steps of the resonant converter dynamic control method described above” renders the claims to be indefinite as it is unclear what “described above” is being referring to. Furthermore, “the resonant converter dynamic control method” lacks antecedent basis. For examining purposes, the term "implements steps of the resonant converter dynamic control method described above" is interpreted to read as “implements steps of a resonant converter dynamic control method comprising: …”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 17 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the claim claims “a memory” which includes “volatile memory”, as disclosed in [0099] of the Specification, which could reasonably comprise a transitory propagating signal per se. The United States Patent and Trademark Office (USPTO) is obliged to give claims their broadest reasonable interpretation consistent with the specification during proceedings before the USPTO. See In re Zietz, 893 F.2d 319 (Fed. Cir. 1989).The broadest reasonable interpretation of a claim drawn to a computer readable medium typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, i.e. “memory”, particularly when the specification is silent. See MPEP 2111.01. Here, Applicant has claimed a “memory”, i.e. a computer readable medium, and the specification is silent on whether this medium is explicitly non-transitory medium. Therefore, given the broadest reasonable interpretation of the claim, the recited computer readable medium could be interpreted as a transitory propagating signal per se. As such, the claim must be rejected under 35 US.C. § 101 as covering non-statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007). In order to overcome this rejection under 35 U.S.C. 101, a claim drawn to such a computer readable medium that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments by adding the limitation "non-transitory" to the claim. Cf Animals - Patentability, 1077 Off. Gaz. Pat. Office 24 (April 21, 1987) (suggesting that applicants add the limitation "non-human" to a claim covering a multicellular organism to avoid a rejection under 35 US.C. § 101). Such an amendment would typically not raise the issue of new matter, even when the specification is silent because the broadest reasonable interpretation relies on the ordinary and customary meaning that includes signals per se.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hu et al. (Chinese Patent Application Publication CN 114362544 A, hereinafter “Hu”). Regarding claim 1, Hu discloses (see Fig. 1) a resonant converter dynamic control system, wherein comprising a resonant converter (see LLC resonant converter), a sampling circuit connected to the resonant converter (comprising “the output current detecting unit and the input voltage detecting unit “ connected to the ADC module circuit sampling vo, io, vg, CT- and CT+, see [0014] – [0015] “the output end of the output current detecting unit and the input voltage detecting unit is connected to the ADC module input port of the digital controller,”), and a control circuit connecting the sampling circuit and the resonant converter (controller comprising DSP and CPLD); the sampling circuit is used for acquiring and transmitting an output voltage signal (vo), an output current signal (io) and a charge integration signal of the resonant converter (vsum) to the control circuit; the control circuit is used for generating a control signal (comprising vgs1, 4 and vgs2, 3, and res) to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate (delta io) and the charge integration signal (DSP and CPLD use vo, io, delta io, and vsum to generate vgs1, 4 and vgs2, 3, and res), wherein the output current change rate is calculated by the output current signal (delta io is calculated by io).
Regarding claim 2, Hu discloses (see Fig. 1) wherein, the control circuit is specifically used for generating an analog reference voltage (Vcomp) according to the output voltage signal, the output current signal and the output current change rate (Vcomp is generated according to vo, io, and delta io); and for transmitting the control signal to the resonant converter to control power transmission of the resonant converter according to a comparison result of the charge integration signal and the analog reference voltage (vgs1, 4 and vgs2, 3, and res is generated according to CMP_OUT, which is the comparison result of vsum and Vcomp).
Regarding claim 3, Hu discloses (see Fig. 1) wherein, the sampling circuit includes: an output voltage sampling circuit (see [0025] “sampling, output voltage”), an output current sampling circuit (see [0025] “sampling, output voltage and output current) and a resonant tank charge sampling circuit (see [0046] “LLC resonant converter adopts charge control the most important link is also obtaining converter charge information, when the charge information reaches a certain threshold, the switch tube acts to realize the power control, the resonant cavity current is taken out by the current transformer CT connected in series in the resonant cavity, and converted into the voltage signal vs CT secondary side, The voltage signal is transferred into weak integral current through the voltage-controlled current source of the transconductance, and the integral voltage vi is obtained on the integral capacitor Ci, so as to finish the isolation sampling and integration of the resonant cavity charge”); an input end of the output voltage sampling circuit and an input end of the output current sampling circuit are respectively connected to an output end of the resonant converter (io and vo are output to RL, which are respectively connected to each sampling circuit), and the resonant tank charge sampling circuit is connected to the resonant tank of the resonant converter (the charge sampling circuit is connected to LLC tank of the LLC resonant converter via CT- and CT+).
Regarding claim 4, Hu discloses (see Fig. 1) wherein, the resonant tank charge sampling circuit is used for detecting the current integration of the resonant tank in half cycle (see [0046] “LLC resonant converter adopts charge control the most important link is also obtaining converter charge information, when the charge information reaches a certain threshold, the switch tube acts to realize the power control, the resonant cavity current is taken out by the current transformer CT connected in series in the resonant cavity, and converted into the voltage signal vs CT secondary side, The voltage signal is transferred into weak integral current through the voltage-controlled current source of the transconductance, and the integral voltage vi is obtained on the integral capacitor Ci, so as to finish the isolation sampling and integration of the resonant cavity charge. the integral capacitor is provided with a switch tube and a parallel connection for discharging and resetting. In order to improve the control stability, further adding the slope compensation, by Vbias through Ri is the integral capacitor Ci linear charging, Ci on the slope compensation voltage vramp and the integral capacitor voltage vi and vsum input comparator, when the integral voltage reaches the voltage outer ring, the switch tube is closed, The other half periods are symmetrical through the digital controller.”), and the resonant tank charge sampling circuit includes a slope compensation circuit (see [0046] “In order to improve the control stability, further adding the slope compensation, by Vbias through Ri is the integral capacitor Ci linear charging, Ci on the slope compensation voltage vramp and the integral capacitor voltage vi and vsum input comparator, when the integral voltage reaches the voltage outer ring, the switch tube is closed,”), the charge integration signal is obtained by adding the slope compensation and charge obtained by current integration of the resonant tank in half cycle (see [0046] “In order to improve the control stability, further adding the slope compensation, by Vbias through Ri is the integral capacitor Ci linear charging, Ci on the slope compensation voltage vramp and the integral capacitor voltage vi and vsum input comparator, when the integral voltage reaches the voltage outer ring, the switch tube is closed,”).
Regarding claim 5, Hu discloses (see Fig. 1) wherein, the control circuit comprises a calculation unit which includes an output voltage controller (comprising adder connected to vo and vref) that is connected to the output voltage sampling circuit, the output voltage sampling circuit is used for transmitting the output voltage signal to the output voltage controller, and the output voltage controller is used for generating a first comparison reference value (Ve) based on the output voltage signal and an output voltage reference value (Ve is based on vo and vref); the calculation unit further includes an output current feedforward unit (comprising Z^-1) which is connected to the output current sampling circuit that is used for transmitting the output current signal to the output current feedforward unit, and the output current feedforward unit is used for generating a second comparison reference value (output of Z^-1 to adder connected to io) based on the output current signal and an output current feedforward coefficient (comprising io portion of kFF, see [0043]); the calculation unit further includes an output current change rate feedforward unit (comprising adder connected to io) which is connected to the output current sampling circuit that is used for transmitting a current output current signal (io) and a historical output current signal (output signal of Z^-1) to the output current change rate feedforward unit, and the output current change rate feedforward unit is used for generating a third comparison reference value (delta io) based on the current output current signal, the historical output current signal and an output current change rate feedforward coefficient (comprising delta io portion of kFF, see [0043]); the calculation unit is further used for obtaining a target comparison reference value (output of PI to DAC) according to the first comparison reference value, the second comparison reference value and the third comparison reference value.
Regarding claim 6, Hu discloses (see Fig. 1) wherein, the control circuit further includes an analog output unit (DAC) which is connected to the calculation unit that is used for transmitting the target comparison reference value to the analog output unit, and the analog output unit is used for receiving the target comparison reference value and converting the target comparison reference value to the analog reference voltage (DAC converts the output of PI to DAC and outputs the analog value Vcomp).
Regarding claim 7, Hu discloses (see Fig. 1) wherein, the control circuit further includes a comparator (CMP) which is connected to the analog output unit and is used for receiving the analog reference voltage and the charge integration signal and performs comparison operation (see [0019] “the output end of the charge detection unit is connected to the in-phase input port of the analogue comparison module of the digital controller, the inverting input end of the analogue comparison module is connected to the DAC module,”).
Regarding claim 8, Hu discloses (see Fig. 1) wherein, the control circuit further includes a pulse width modulation unit (comprising CPLD) which is connected to the comparator, the comparator transmits a comparison result (CMP_OUT) of the charge integration signal and the analog reference voltage to the pulse width modulation unit, and the pulse width modulation unit is used for generating the control signal based on the comparison result (CPLD uses CMP_OUT to generate vgs1, 2, 3, 4 and res); the pulse width modulation unit is further used for transmitting the control signal to an inverter circuit of the resonant converter (comprising Q1, Q2, Q3, Q4), and the control signal is used for controlling power transmission of the resonant converter (Vgs1, 2, 3, 4 are used to control Q1, Q2, Q3, Q4 to control power transmission of the LLC resonant converter).
Regarding claim 9, Hu discloses (see Fig. 1) wherein, the control circuit further includes an input voltage sampling circuit (see [0015] “the input voltage detecting unit is connected to the ADC module input port of the digital controller,”) which is connected to the calculation unit, the input voltage sampling circuit is used for acquiring an input voltage of the resonant converter (Vg) and transmitting an input voltage sampling signal (vg) to the calculation unit, and the calculation unit is further used for adjusting the output current feedforward coefficient according to the input voltage sampling signal and the output voltage signal (kFF is determined according to vg and vo).
Regarding claim 10, Hu discloses (see Fig. 1) wherein, the control circuit further includes an input voltage sampling circuit (see [0015] “the input voltage detecting unit is connected to the ADC module input port of the digital controller,”) which is connected to the calculation unit, the input voltage sampling circuit is used for acquiring an input voltage of the resonant converter (Vg) and transmitting an input voltage sampling signal (vg) to the calculation unit, and the calculation unit is further used for determining an estimated operating frequency of the resonant converter (fs) according to the input voltage sampling signal, the output voltage signal, the output current signal and a resonant tank parameter of the resonant converter (fs is determined according to vg, vo, io, and Lr and Cr); the calculation unit is further used for adjusting the output current feedforward coefficient based on the estimated operating frequency, the input voltage sampling signal and the output voltage signal (kFF is determined according to fs, vg, and vo).
Regarding claim 11, Hu discloses (see Fig. 1) wherein, the resonant converter comprises an inverter circuit (comprising Q1, Q2, Q3, Q4), a resonant tank (comprising Lr, Lm, Cr) and a rectifier circuit (comprising SR1, SR2), the inverter circuit is a full-bridge circuit or a half-bridge circuit (Q1, Q2, Q3, Q4 is a full-bridge circuit), and the rectifier circuit is a full-bridge circuit or a full-wave circuit (SR1, SR2 is a full-wave circuit), and the rectifier circuit contains a transformer for electrical isolation and/or voltage conversion (n:1:1 transformer).
Regarding claim 12, Hu discloses (see Fig. 1) a resonant converter dynamic control method, wherein comprising: acquiring an output voltage signal (vo), an output current signal (io) and a charge integration signal (vsum) of a resonant converter (LLC resonant converter); generating a control signal (comprising vgs1, 2, 3, 4) to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate (delta io) and the charge integration signal (vgs1, 2, 3, 4 is generated according to vo, io, delta io, and vsum), wherein the output current change rate is calculated by the output current signal (delta io is calculated by io).
Regarding claim 13, Hu discloses (see Fig. 1) wherein, the generating a control signal to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate and the charge integration signal, includes: generating an analog reference voltage (vcomp) according to the output voltage signal, the output current signal and the output current change rate (vcomp is generated according to vo, io, delta io); transmitting the control signal to the resonant converter to control power transmission of the resonant converter according to a comparison result of the charge integration signal and the analog reference voltage (CMP_OUT, LLC resonant converter is controlled according to CMP_OUT).
Regarding claim 14, Hu discloses (see Fig. 1) wherein, the generating an analog reference voltage according to the output voltage signal, the output current signal and the output current change rate, includes: generating a first comparison reference value (Ve) based on the output voltage signal and an output voltage reference value (Ve is based on vo and vref); generating a second comparison reference value (output of Z^-1 to adder connected to io) based on the output current signal and an output current feedforward coefficient (comprising io portion of kFF, see [0043]); generating a third comparison reference value (delta io) based on the current output current signal, the historical output current signal and an output current change rate feedforward coefficient (comprising delta io portion of kFF, see [0043]); obtaining a target comparison reference value (output of PI to DAC) according to the first comparison reference value, the second comparison reference value and the third comparison reference value, and converting the target comparison reference value to the analog reference voltage (converting via DAC).
Regarding claim 15, Hu discloses (see Fig. 1) wherein further comprising, before the generating a second comparison reference value based on the output current signal and an output current feedforward coefficient, adjusting the output current feedforward coefficient according to the input voltage sampling signal (vg) and the output voltage signal of the resonant converter (kFF is determined according to vg and vo).
Regarding claim 16, Hu discloses (see Fig. 1) wherein further comprising, before the generating a second comparison reference value based on the output current signal and an output current feedforward coefficient, determining an estimated operating frequency of the resonant converter (fs) according to the input voltage sampling signal, the output voltage signal, the output current signal of the resonant converter and a resonant tank parameter of the resonant converter (fs is determined based on vg, vo, io, and Cr, Lr, Lm); adjusting the output current feedforward coefficient based on the estimated operating frequency, the input voltage sampling signal and the output voltage signal (kFF is determined according to fs, vg, vo).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Yu et al. (US Patent Application Publication US 2021/0249961 A1, hereinafter “Yu”). Regarding claim 17, as best understood, Hu discloses (see Fig. 1) an electronic device, implementing steps of a resonant converter dynamic control method comprising: acquiring an output voltage signal (vo), an output current signal (io) and a charge integration signal (vsum) of a resonant converter (LLC resonant converter); generating a control signal (comprising vgs1, 2, 3, 4) to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate (delta io) and the charge integration signal (vgs1, 2, 3, 4 is generated according to vo, io, delta io, and vsum), wherein the output current change rate is calculated by the output current signal (delta io is calculated by io). Hu does not disclose comprising a memory, a processor, and a computer program stored on the memory and executable on the processor. However, Yu teaches (see Fig. 4) an electronic device (400) comprising a memory (404), a processor (402), and a computer program (146) stored on the memory and executable on the processor (see [0044] “Both memory 404 and mass storage devices 412 may be collectively referred to as memory or computer storage media herein and may be any type of non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that can be executed by the processors 402 as a particular machine configured for carrying out the operations and functions described in the implementations herein.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Hu to comprise a memory, a processor, and a computer program stored on the memory and executable on the processor, as taught by Yu, because it can help implement the dynamic control system in a programmable compact integrated form factor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication US 2024/0243656 A1 discloses a resonant power converter circuit. US Patent Application Publication US 2023/0088584 A1 discloses a resonant power converter circuit control method with charge control and feedforward control. US Patent Application Publication US 2019/0044430 A1 discloses a power limit protection method for a resonant power converter. US Patent Application Publication US 2024/0388200 A1 discloses a resonant converter dynamic control system. WIPO Patent Application Publication WO 2023/011138 A1 discloses a dynamic control method for a resonant power converter circuit. Chinese Patent CN 105406717 B discloses an LLC resonant power converter circuit control method.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838