Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 06/04/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-9, 11, 12, 14, and 15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hu et al. (Chinese Patent Application Publication CN 114362544 A, hereinafter “Hu”). Regarding claim 1, Hu discloses (see Fig. 1) a resonant converter dynamic control system comprising a resonant converter (LLC resonant converter), a sampling circuit connected to the resonant converter (comprising the output current detecting unit and the input voltage detecting unit connected to the ADC module circuit sampling vo, io, vg, CT- and CT+, see [0014]-[0015] of Hu “the output end of the output current detecting unit and the input voltage detecting unit is connected to the ADC module input port of the digital controller,”), and a control circuit connecting the sampling circuit and the resonant converter (controller comprising DSP and CPLD), wherein: the sampling circuit is used for acquiring and transmitting an output voltage signal (vo), an output current signal (io), and a charge integration signal (vsum) of the resonant converter to the control circuit; and the control circuit is used for: generating a control signal (comprising vgs1, 2, 3, 4, and res) to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate (delta io), and the charge integration signal (DSP and CPLD use vo, io, delta io, and vsum to generate vgs1, 2, 3, 4, and res), wherein the output current change rate is calculated based on the output current signal (delta io is calculated by io); generating an analog reference voltage (Vcomp) according to the output voltage signal, the output current signal, and the output current change rate (Vcomp is generated according to vo, io, and delta io); and transmitting the control signal to the resonant converter to control the power transmission of the resonant converter according to a comparison result of the charge integration signal and the analog reference voltage (vgs1, 2, 3, 4, and res is generated according to CMP_OUT, which is the comparison result of vsum and Vcomp).
Regarding claim 3, Hu discloses (see Fig. 1) wherein: the sampling circuit includes an output voltage sampling circuit (see [0025] of Hu “sampling, output voltage”), an output current sampling circuit (see [0025] of Hu “sampling, output voltage and output current”), and a resonant tank charge sampling circuit (charge detection unit, see [0046] of Hu “the resonant cavity current is taken out by the current transformer CT connected in series in the resonant cavity, and converted into the voltage signal vs CT secondary side”); an input end of the output voltage sampling circuit and an input end of the output current sampling circuit are connected to an output end of the resonant converter (io and vo are output to RL, which are respectively connected to each sampling circuit); and the resonant tank charge sampling circuit is connected to a resonant tank of the resonant converter (the charge sampling circuit is connected to LLC tank of the LLC resonant converter via CT- and CT+).
Regarding claim 4, Hu discloses (see Fig. 1) wherein: the resonant tank charge sampling circuit is used for detecting current integration of the resonant tank during a half cycle (see [0046] of Hu “when the charge information reaches a certain threshold, the switch tube acts to realize the power control” and see [0046] of Hu “The other half periods are symmetrical through the digital controller.”); the resonant tank charge sampling circuit includes a slope compensation circuit (see [0046] of Hu “In order to improve the control stability, further adding the slope compensation, by Vbias through Ri is the integral capacitor Ci linear charging”); and the charge integration signal is obtained by adding slope compensation and charge obtained by the current integration of the resonant tank during the half cycle (see [0046] of Hu “Ci on the slope compensation voltage vramp and the integral capacitor voltage vi and vsum input comparator, when the integral voltage reaches the voltage outer ring, the switch tube is closed,”).
Regarding claim 5, Hu discloses (see Fig. 1) wherein: the control circuit comprises a calculation unit which includes an output voltage controller (comprising adder connected to vo and vref) that is connected to the output voltage sampling circuit, the output voltage sampling circuit is used for transmitting the output voltage signal to the output voltage controller, and the output voltage controller is used for generating a first comparison reference value (Ve) based on the output voltage signal and an output voltage reference value (Ve is based on vo and vref); the calculation unit further includes an output current feedforward unit (comprising Z^-1) which is connected to the output current sampling circuit that is used for transmitting the output current signal to the output current feedforward unit, and the output current feedforward unit is used for generating a second comparison reference value (output of Z^-1 to adder connected to io) based on the output current signal and an output current feedforward coefficient (comprising io portion of kFF, see [0043] of Hu); the calculation unit further includes an output current change rate feedforward unit (comprising adder connected to io) which is connected to the output current sampling circuit that is used for transmitting a current output current signal (io) and a historical output current signal (output signal of Z^-1) to the output current change rate feedforward unit, and the output current change rate feedforward unit is used for generating a third comparison reference value (delta io) based on the current output current signal, the historical output current signal, and an output current change rate feedforward coefficient (comprising delta io portion of kFF, see [0043] of Hu); and the calculation unit is further used for obtaining a target comparison reference value (output of PI to DAC) according to the first comparison reference value, the second comparison reference value, and the third comparison reference value.
Regarding claim 6, Hu discloses (see Fig. 1) wherein: the control circuit further includes an analog output unit (DAC) which is connected to the calculation unit that is used for transmitting the target comparison reference value to the analog output unit; and the analog output unit is used for receiving the target comparison reference value and converting the target comparison reference value to the analog reference voltage (DAC converts the output of PI to DAC and outputs the analog value Vcomp).
Regarding claim 7, Hu discloses (see Fig. 1) wherein the control circuit further includes a comparator (CMP) which is connected to the analog output unit and is used for receiving the analog reference voltage and the charge integration signal and performs comparison operation (see [0019] of Hu “the output end of the charge detection unit is connected to the in-phase input port of the analogue comparison module of the digital controller, the inverting input end of the analogue comparison module is connected to the DAC module,”).
Regarding claim 8, Hu discloses (see Fig. 1) wherein: the control circuit further includes a pulse width modulation unit (comprising CPLD) which is connected to the comparator, the comparator transmits the comparison result (CMP_OUT) of the charge integration signal and the analog reference voltage to the pulse width modulation unit, and the pulse width modulation unit is used for generating the control signal based on the comparison result (CPLD uses CMP_OUT to generate vgs1, 2, 3, 4 and res); the pulse width modulation unit is further used for transmitting the control signal to an inverter circuit of the resonant converter (comprising Q1, Q2, Q3, Q4); and the control signal is used for controlling the power transmission of the resonant converter (Vgs1, 2, 3, 4 are used to control Q1, Q2, Q3, Q4 to control power transmission of the LLC resonant converter).
Regarding claim 9, Hu discloses (see Fig. 1) wherein: the control circuit further includes an input voltage sampling circuit (see [0015] of Hu “the input voltage detecting unit is connected to the ADC module input port of the digital controller,”) which is connected to the calculation unit; the input voltage sampling circuit is used for acquiring an input voltage of the resonant converter (Vg) and transmitting an input voltage sampling signal (vg) to the calculation unit; and the calculation unit is further used for adjusting the output current feedforward coefficient according to the input voltage sampling signal and the output voltage signal (kFF is determined according to vg and vo).
Regarding claim 11, Hu discloses (see Fig. 1) wherein: the resonant converter comprises an inverter circuit (comprising Q1, Q2, Q3, Q4), a resonant tank (comprising Lr, Lm, Cr), and a rectifier circuit (comprising SR1, SR2); the inverter circuit is a full-bridge circuit or a half-bridge circuit (Q1, Q2, Q3, Q4 is a full-bridge circuit); the rectifier circuit is a full-bridge circuit or a full-wave circuit (SR1, SR2 is a full-wave circuit); and the rectifier circuit contains a transformer for electrical isolation and/or voltage conversion (n:1:1 transformer).
Regarding claim 12, Hu discloses (see Fig. 1) a resonant converter dynamic control method comprising: acquiring an output voltage signal (vo), an output current signal (io), and a charge integration signal (vsum) of a resonant converter (LLC resonant converter); and generating a control signal (comprising vgs1, 2, 3, 4, and res) to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate (delta io), and the charge integration signal (vgs1, 2, 3, 4, and res is generated according to vo, io, delta io, and vsum), wherein the output current change rate is calculated based on the output current signal (delta io is calculated by io), and wherein generating the control signal to control the power transmission of the resonant converter according to the output voltage signal, the output current signal, the output current change rate, and the charge integration signal includes: generating an analog reference voltage (vcomp) according to the output voltage signal, the output current signal, and the output current change rate (vcomp is generated according to vo, io, delta io); and transmitting the control signal to the resonant converter to control the power transmission of the resonant converter according to a comparison result of the charge integration signal and the analog reference voltage (CMP_OUT, LLC resonant converter is controlled according to CMP_OUT).
Regarding claim 14, Hu discloses (see Fig. 1) wherein generating the analog reference voltage according to the output voltage signal, the output current signal, and the output current change rate includes: generating a first comparison reference value (Ve) based on the output voltage signal and an output voltage reference value (Ve is based on vo and vref); generating a second comparison reference value (output of Z^-1 to adder connected to io) based on the output current signal and an output current feedforward coefficient (comprising io portion of kFF, see [0043] of Hu); generating a third comparison reference value (delta io) based on a current output current signal, a historical output current signal, and an output current change rate feedforward coefficient (comprising delta io portion of kFF, see [0043] of Hu); obtaining a target comparison reference value (output of PI to DAC) according to the first comparison reference value, the second comparison reference value, and the third comparison reference value; and converting the target comparison reference value to the analog reference voltage (converting via DAC).
Regarding claim 15, Hu discloses (see Fig. 1) further comprising, before generating the second comparison reference value based on the output current signal and the output current feedforward coefficient, adjusting the output current feedforward coefficient according to an input voltage sampling signal (vg) and the output voltage signal of the resonant converter (kFF is determined according to vg and vo).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Yu et al. (US Patent Application Publication US 2021/0249961 A1, hereinafter “Yu”).
Regarding claim 17, Hu discloses (see Fig. 1) implementing a resonant converter dynamic control method comprising: acquiring an output voltage signal (vo), an output current signal (io), and a charge integration signal (vsum) of a resonant converter (LLC resonant converter); and generating a control signal (comprising vgs1, 2, 3, 4, and res) to control power transmission of the resonant converter according to the output voltage signal, the output current signal, an output current change rate (delta io), and the charge integration signal (vgs1, 2, 3, 4, and res is generated according to vo, io, delta io, and vsum), wherein the output current change rate is calculated based on the output current signal (delta io is calculated by io), and wherein generating the control signal to control the power transmission of the resonant converter according to the output voltage signal, the output current signal, the output current change rate, and the charge integration signal, includes: generating an analog reference voltage (vcomp) according to the output voltage signal, the output current signal, and the output current change rate (vcomp is generated according to vo, io, delta io); and transmitting the control signal to the resonant converter to control the power transmission of the resonant converter according to a comparison result of the charge integration signal and the analog reference voltage (CMP_OUT, LLC resonant converter is controlled according to CMP_OUT).
Hu does not disclose an electronic device comprising a non-transitory memory, a processor, and a computer program stored on the non-transitory memory and executable on the processor, wherein the processor, when executing the computer program, implements a method.
However, Yu teaches (see Fig. 4) an electronic device (400) comprising a non-transitory memory (404 and 412), a processor (402), and a computer program (416) stored on the non-transitory memory and executable on the processor, wherein the processor, when executing the computer program, implements a method (see [0044] of Yu “Both memory 404 and mass storage devices 412 may be collectively referred to as memory or computer storage media herein and may be any type of non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that can be executed by the processors 402 as a particular machine configured for carrying out the operations and functions described in the implementations herein.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic device of Hu to comprise a non-transitory memory, a processor, and a computer program stored on the non-transitory memory and executable on the processor, wherein the processor, when executing the computer program, implements the resonant converter dynamic control method, as taught by Yu, because it can help implement the dynamic control method in a programmable compact integrated form factor.
Allowable Subject Matter
Claims 10 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “determining an estimated operating frequency of the resonant converter according to the input voltage sampling signal, the output voltage signal, the output current signal, and a resonant tank parameter of the resonant converter; and adjusting the output current feedforward coefficient based on the estimated operating frequency, the input voltage sampling signal, and the output voltage signal.”. The closest prior art, Hu, obtains the switching frequency of the resonant converter by measurement at the capture module and applies that measured value in computing the output current feedforward coefficient (see [0021] and [0044] of Hu), but Hu does not derive the operating frequency from the input voltage sampling signal, the output voltage signal, the output current signal, and a resonant tank parameter of the resonant converter, and therefore fails to disclose or teach the above limitation. Nishijima (US Patent Application Publication US 2017/0294844 A1) applies a first harmonic approximation analysis that relates the switching frequency of an LLC converter to the input voltage, the output voltage, the load, and the resonant tank parameters, but Nishijima applies that analysis as a design-time confirmation of the operation use region and the operating point of the converter (see [0071] of Nishijima “the operation use region of the LLC converter 100, an operating point (input voltage and a switching frequency, for example) which meets an output voltage, or the like is confirmed”), while the control circuit of Nishijima generates the switching frequency on the basis of a feedback voltage derived from the detected output voltage (see [0046] of Nishijima). Nishijima therefore does not determine an estimated operating frequency within a calculation unit during operation of the converter, and does not adjust an output current feedforward coefficient based on such an estimated operating frequency, and accordingly also fails to disclose or teach the above limitation.
Regarding claim 16, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “determining an estimated operating frequency of the resonant converter according to an input voltage sampling signal, the output voltage signal, the output current signal of the resonant converter, and a resonant tank parameter of the resonant converter; and adjusting the output current feedforward coefficient based on the estimated operating frequency, the input voltage sampling signal, and the output voltage signal.”. The closest prior art, Hu, obtains the switching frequency of the resonant converter by measurement at the capture module and applies that measured value in computing the output current feedforward coefficient (see [0021] and [0044] of Hu), but Hu does not derive the operating frequency from an input voltage sampling signal, the output voltage signal, the output current signal, and a resonant tank parameter of the resonant converter, and therefore fails to disclose or teach the above limitation. Nishijima applies the first harmonic approximation analysis as a design-time confirmation of the operation use region and the operating point of the converter rather than determining an estimated operating frequency during operation of the converter for the purpose of adjusting an output current feedforward coefficient, as set forth above with respect to claim 10, and accordingly also fails to disclose or teach the above limitation.
Response to Arguments
Applicant’s amendments and arguments filed 06/04/2026 have been fully considered. The arguments are persuasive with respect to claims 10 and 16, and are not persuasive with respect to claims 1, 5, and 9, for the reasons set forth below. Regarding claim 1, Applicant argued that Hu does not disclose generating an analog reference voltage according to the output current signal, because the output current io is allegedly used only as an intermediate variable to calculate delta io, such that Vcomp is generated directly only from vo and delta io. This argument is not persuasive for at least the following three reasons. First, Hu uses the sampled output current directly. Hu obtains a predicted load power from the sampled output current together with the input voltage, the output voltage, and the switching frequency (see [0025] of Hu), derives a predicted feedforward control amount therefrom (see [0026] of Hu), and applies that amount in generating the charge upper limit threshold that is supplied to the DAC module and output as the analog reference voltage (see [0027] and [0019] of Hu). The output current signal is therefore a direct input to the generation of the analog reference voltage in Hu, and is not merely an intermediate variable.
Second, the argument is not commensurate with the scope of claim 1. Claim 1 requires only that the analog reference voltage be generated according to the output voltage signal, the output current signal, and the output current change rate. Claim 1 does not require that the output current signal be applied as an input separate from, parallel to, or independent of the path by which the output current change rate is obtained. To the contrary, claim 1 itself recites that the output current change rate is calculated based on the output current signal, so claim 1 expressly contemplates that the output current signal is the quantity from which the output current change rate is derived. Applicant’s argument reads into claim 1 a separate direct input path that claim 1 does not recite. See MPEP 2145.
Third, Applicant’s own remarks confirm the disclosure of Hu. Applicant states that the DSP module of Hu receives vo and io and computes delta io as the difference between the current sample of io and the previous sample of io, and that the output of the PI controller is summed with the feedforward signal based on delta io to generate delta vcomp, which is converted by a DAC to produce Vcomp. Hu therefore generates the analog reference voltage from vo, io, and delta io as set forth in the rejection.
Applicant further argued that Hu teaches away from direct use of io and that the claimed combination provides unexpected technical effects. These arguments are not persuasive. Teaching away and unexpected results are not relevant to a rejection under 35 U.S.C. 102, which requires only that a single reference disclose each and every limitation of the claim as arranged in the claim. Moreover, the asserted improvements in steady-state regulation accuracy and transient response are unsupported by any objective evidence of record, and arguments of counsel cannot take the place of evidence. See MPEP 716.01(c) and MPEP 2145. Regarding claim 5 (Remarks, pp. 11-14), Applicant argued that Hu discloses only a single unified kFF feedforward path and therefore does not disclose (A) two separate feedforward units, (B) two independently configurable feedforward coefficients, or (C) a hierarchical superposition of three comparison reference values. These arguments are not persuasive.
First, with respect to the asserted structural division, the recited output voltage controller, output current feedforward unit, output current change rate feedforward unit, and calculation unit are defined solely by the functions they perform and recite no structure beyond the digital controller of Hu that performs those functions. A single structure that performs each of the recited functions reads on the recited plurality of functional units, and a recitation of the intended use or function of a structure does not distinguish that structure from prior art capable of performing the same function. See MPEP 2114. Hu generates a first comparison reference value from the output voltage signal and a reference value (Ve based on vo and vref), a second comparison reference value from the output current signal and a feedforward coefficient, and a third comparison reference value from the current and historical output current signals and a feedforward coefficient (see [0043] of Hu), as set forth in the rejection.
Second, the two-coefficient argument is not commensurate with the scope of claim 5. Claim 5 recites an output current feedforward coefficient and an output current change rate feedforward coefficient, but does not require the two coefficients to differ in value, to be separately stored, or to be independently configurable or independently adjustable. Under the broadest reasonable interpretation, the coefficient kFF of Hu, as applied to the output current signal in generating the second comparison reference value and as applied to the change in the output current in generating the third comparison reference value, reads on both recited coefficients. Applicant’s assertions regarding independent configuration, modular division, and separate optimization are directed to features that claim 5 does not recite. See MPEP 2145.
Third, with respect to the generation logic of the target comparison reference value, claim 5 requires only obtaining a target comparison reference value according to the first comparison reference value, the second comparison reference value, and the third comparison reference value. Claim 5 recites no hierarchy among the three values, no order of combination, and no requirement that the three values be maintained as physically separate signals. Hu obtains the target comparison reference value supplied to the DAC from the output voltage loop value and the feedforward values as set forth in the rejection, which satisfies claim 5 as written.
Applicant’s assertions of technical contribution and substantial technical effects are not persuasive for the reasons set forth above with respect to claim 1.
Regarding claim 9, Applicant argued that Hu describes only input voltage sampling and a globally determined, unified coefficient kFF, and does not describe adjusting the output current feedforward coefficient according to the input voltage sampling signal and the output voltage signal as a distinct, dedicated, and independently adjustable coefficient. This argument is not persuasive. Applicant’s own remarks establish that the coefficient of Hu is a function of both the input voltage signal and the output voltage signal. Applicant states that “kFF is derived from a combined formula: kFF=vo/2 (Ci * fs * Ks *vg)”. The coefficient of Hu therefore varies with vo, the output voltage signal, and with vg, the input voltage sampling signal, which is precisely the adjustment recited in claim 9.
Furthermore, claim 9 does not require the output current feedforward coefficient to be dedicated solely to the output current path, to be independent of any other coefficient, or to be adjusted while any other coefficient is held unchanged. The characterizations of the coefficient of Hu as global, unified, and non-modular are therefore not commensurate with the scope of claim 9, and do not distinguish the claim from Hu. See MPEP 2145. Regarding claim 10, Applicant argued that Hu describes measuring an actual switching frequency fs for use in the feedforward calculation, and does not describe determining an estimated operating frequency of the resonant converter according to the input voltage sampling signal, the output voltage signal, the output current signal, and a resonant tank parameter of the resonant converter. This argument is persuasive. Hu obtains the switching frequency by measurement at the capture module (see [0021] of Hu), rather than by estimation from the input voltage, the output voltage, the output current, and a resonant tank parameter. Accordingly, the rejection of claim 10 under 35 U.S.C. 102(a)(1) is withdrawn, and claim 10 is objected to as containing allowable subject matter as set forth above. Regarding claim 16, Applicant relies upon the same reasons set forth for claim 10. Those arguments are persuasive for the reasons set forth above. Accordingly, the rejection of claim 16 under 35 U.S.C. 102(a)(1) is withdrawn, and claim 16 is objected to as containing allowable subject matter as set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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