DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/13/2026 has been entered.
Other Refs: Wicki (US 9135175) Distributed Cache Coherency; Ro (US 20240241828)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 7-12, 14, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250053336) and in view of Kalamatianos (US 20220188233 A1) and further in view of Aga (US 20230004491)
Claim 1. Lee discloses A system (eg., [0044] Referring to FIG. 2, a computing system 100 ) comprising:
a memory (eg., 0041, 0045 Fig. 2 - CXL devices 140, 180 and 185 may correspond to the plurality of memory devices 15, 16 and 17 in FIG. 1.);
a processing-in-memory processor associated with the memory (eg., 0041 - memory device having a processing-in-memory (PIM) feature);
a memory controller, the memory controller configured to: (eg., Fig. 3 0053-0054 - controller 145)
receive a memory request for the processing-in-memory processor, wherein the memory request is associated with a region of the memory (eg., 0041 - memory operations may include one or more computations performed in a memory device having a processing-in-memory (PIM) feature.);
schedule writing, into the memory, cached data associated with the region of the memory (eg., 0039 - The request generator RQG may generate requests for requesting a memory access such as a write operation and a read operation based on an address corresponding to the memory region; [0059] The command scheduler 165 may provide scheduled commands CMD_S to the memory 170 by scheduling commands ; [0063] The second buffer 163 may receive the rearranged data RDTA and may provide the all or some of the plurality of hosts 101, 102 and 103 with the rearranged data RDTA by a receiving order as an output data ODTA.); and
Lee does not disclose, but Kalamatianos discloses
a plurality of memory requests, the plurality of memory requests including a memory request for the processing-in-memory processor, the memory request associated with a region of the memory (eg. 0011 - PIM instructions are placed in a PIM queue and are eventually dispatched to the PIM device for execution … data is present in a cache)…; ., [0012] If the data to be used by a PIM read instruction is in a cache and the data is marked dirty, a PIM read request will wait to be dispatched until the data is flushed from the cache to memory; [0038] In some examples, after a PIM request is issued by a processor core 106, 108, 110, 112, the PIM request is received by the coherency synchronizer 134. The coherency synchronizer 134 performs cache operation on the various caches of the core complexes 102, 104 to ensure that any cache entries for virtual and/or physical addresses identified in the PIM request remain coherent. For example, when a PIM request includes as an operand a virtual and/or physical address,)
delaying scheduling the memory request of the processing-in-memory processor until the cached data is transmitted from the memory controller to the memory (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory.; 0038 - After the appropriate cache operations have completed, the PIM request is transmitted to the memory controller 136 for offloading to the PIM device; 0014 - issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos does not disclose, but Aga discloses
buffer, in the command queue, (eg. 0053 - instructions stored in the cache controller queues )
adjust an order of the buffered memory requests in the command queue (eg., 0055 - priority, memory-side processing commands, for which preloading of the corresponding memory-side processing results is to be used, specify a priority via, for example, one or more newly added or previously unused bit values or bits. The cache controller uses the priority specified in the memory-side processing command to decide when to issue the corresponding prefetch commands relative to other commands, i.e., in which order to issue commands. For example, prefetch commands are issued after all commands having a higher priority have been processed.; 0034 - performed by memory-side processing elements, such as PIM. )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, with Aga, providing the benefit of cache controllers store commands to perform preloading, such as prefetch commands, in queues to allow the cache controllers to manage issuance of the commands in a manner that reduces interference with other memory-side processing instructions or memory load/store operations (see Aga, 0044).
Claim 2. Lee discloses wherein the cached data corresponds to memory write requests from a host configured to access the memory via the memory controller (eg., 0039 - a write operation and a read operation based on an address corresponding to the memory region exclusively allocated to each host.).
Claim 3. Lee discloses wherein the memory controller is further configured to identify the region of the memory based on one or more memory requests including the memory request of the processing-in-memory processor (eg., 0039 - requesting a memory access such as a write operation and a read operation based on an address corresponding to the memory region exclusively allocated to each host.; 0041 - the memory operations may include one or more computations performed in a memory device having a processing-in-memory (PIM) ).
Claim 4. Lee discloses a host (eg., 0036 Fig. 1 - host 11); and
a command queue configured to buffer memory requests from the host (eg., [0077] Referring to FIGS. 3 and 6, the CXL device 140 may provide the internal data IDTA11, IDTA2, IDTA12 and IDTA3 to the first buffer 157 according to an order requested by the plurality of hosts),
wherein the memory controller is configured to adjust an order of the memory requests (eg., 0007 - generates output data by rearranging the internal data)
Lee does not disclose, but Kalamatianos discloses
such that one or more memory requests associated with the region of the memory are scheduled prior to the memory request of the processing-in-memory processor (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos does not disclose, but Aga discloses
Command queue … plurality of memory requests (eg. 0053 - instructions stored in the cache controller queues )
adjust an order of the buffered memory requests in the command queue (eg., 0055 - priority, memory-side processing commands, for which preloading of the corresponding memory-side processing results is to be used, specify a priority via, for example, one or more newly added or previously unused bit values or bits. The cache controller uses the priority specified in the memory-side processing command to decide when to issue the corresponding prefetch commands relative to other commands, i.e., in which order to issue commands. For example, prefetch commands are issued after all commands having a higher priority have been processed.; 0034 - performed by memory-side processing elements, such as PIM. )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, with Aga, providing the benefit of cache controllers store commands to perform preloading, such as prefetch commands, in queues to allow the cache controllers to manage issuance of the commands in a manner that reduces interference with other memory-side processing instructions or memory load/store operations (see Aga, 0044).
Claim 6. Lee does not disclose, but Kalamatianos discloses
a coherence directory configured to buffer the cached data, wherein the memory controller is further configured to obtain the cached data from the coherence directory in response to receiving the memory request for the processing-in-memory processor (eg., 0038 - coherency synchronizer 134 performs cache operation on the various caches of the core complexes 102, 104 to ensure that any cache entries for virtual and/or physical addresses identified in the PIM request remain coherent. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Claim 7. Lee discloses A method (eg., [0044] Referring to FIG. 2, a computing system 100 ) comprising:
receiving a memory request, wherein the memory request is associated with a region of a memory (eg., 0041 - memory operations may include one or more computations performed in a memory device having a processing-in-memory (PIM) feature.);
writing, to the memory, cached data associated with the region of the memory (eg., 0039 - The request generator RQG may generate requests for requesting a memory access such as a write operation and a read operation based on an address corresponding to the memory region; [0059] The command scheduler 165 may provide scheduled commands CMD_S to the memory 170 by scheduling commands ; [0063] The second buffer 163 may receive the rearranged data RDTA and may provide the all or some of the plurality of hosts 101, 102 and 103 with the rearranged data RDTA by a receiving order as an output data ODTA.); and
Lee does not disclose, but Kalamatianos discloses
a plurality of memory requests, the plurality of memory requests including a memory request for a processing-in-memory processor, wherein the memory request associated with a region of the memory (eg. 0011 - PIM instructions are placed in a PIM queue and are eventually dispatched to the PIM device for execution … data is present in a cache)…; ., [0012] If the data to be used by a PIM read instruction is in a cache and the data is marked dirty, a PIM read request will wait to be dispatched until the data is flushed from the cache to memory; [0038] In some examples, after a PIM request is issued by a processor core 106, 108, 110, 112, the PIM request is received by the coherency synchronizer 134. The coherency synchronizer 134 performs cache operation on the various caches of the core complexes 102, 104 to ensure that any cache entries for virtual and/or physical addresses identified in the PIM request remain coherent. For example, when a PIM request includes as an operand a virtual and/or physical address,)
the memory request of the processing-in-memory processor until the cached data is transmitted from the memory controller to the memory (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory.; 0038 - After the appropriate cache operations have completed, the PIM request is transmitted to the memory controller 136 for offloading to the PIM device).
adjusting an order of the buffered memory requests in the command queue by delaying scheduling the memory request of the processing-in-memory processor until the cached data is written to the memory (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory.; 0038 - After the appropriate cache operations have completed, the PIM request is transmitted to the memory controller 136 for offloading to the PIM device; 0014 - issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos does not disclose, but Aga discloses
buffering, in a command queue of a memory controller, the plurality of memory requests (eg. 0053 - instructions stored in the cache controller queues )
adjust an order of the buffered memory requests in the command queue (eg., 0055 - priority, memory-side processing commands, for which preloading of the corresponding memory-side processing results is to be used, specify a priority via, for example, one or more newly added or previously unused bit values or bits. The cache controller uses the priority specified in the memory-side processing command to decide when to issue the corresponding prefetch commands relative to other commands, i.e., in which order to issue commands. For example, prefetch commands are issued after all commands having a higher priority have been processed.; 0034 - performed by memory-side processing elements, such as PIM. )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, with Aga, providing the benefit of cache controllers store commands to perform preloading, such as prefetch commands, in queues to allow the cache controllers to manage issuance of the commands in a manner that reduces interference with other memory-side processing instructions or memory load/store operations (see Aga, 0044).
Claim 8 is rejected for reasons similar to Claim 2 above.
Claim 9. Lee does not disclose, but Kalamatianos discloses
flushing the cached data from one or more caches in response to receiving the memory request for the processing-in-memory processor (eg., 0013 0059 - to flush out PIM data from the caches, all younger PIM requests from the same thread need to wait as well.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Claim 10 is rejected for reasons similar to Claim 3 above.
Claim 11. Lee discloses buffering, in a command queue of a memory controller, memory requests from one or more processors (eg., 0059] The command scheduler 165 may provide scheduled commands CMD_S to the memory 170 by scheduling commands CMDs included in the packets PKTa, PKTb and PKTc, and the memory 170 may generate internal data IDTAs by performing memory operations corresponding to the scheduled commands CMD_S and may provide the internal data IDTAs to the first buffer 157.)
Claim 12 is rejected for reasons similar to Claim 4 above.
Claim 14 is rejected for reasons similar to Claim 6 above.
Claim 17. Lee discloses
using hardware comparator logic of a memory controller (eg., 0077 - arbiter 161 )
Lee does not disclose, but Kalamatianos discloses
wherein the write requests dependent on the memory request are identified … configured to perform a processing-in-memory address comparison with addresses of the write requests. (eg., 0014 - I/O die logic is also configured to issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device. In some implementations, the cache probe is issued to one or more caches to invalidate or flush data associated with the physical memory address..).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos does not disclose, but Kim247 discloses
buffering the memory request for the processing-in-memory processor in a separate queue from a processing-in-memory command queue until any write requests dependent on the memory request for the processing-in-memory processor are processed, (eg.,. [0052] Fig. 2 - The PIM request queue 223 may store identified PIM commands. ; [0058] The command queue 227 may store commands generated by or transmitted from the command generator 226.; ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, with Kim247, providing the benefit of a research on processing in memory (PIM) is being conducted for a semiconductor memory device that combines, with a memory function, a function of a processor configured to perform an operation (see Kim247, 0003).
Claim 18. Lee discloses A device (eg., [0044] FIG. 3, device 140 ) comprising:
a processing-in-memory processor associated with the memory (eg., 0041 - memory device having a processing-in-memory (PIM) feature);
a memory controller, the memory controller configured to: (eg., Fig. 3 0053-0054 - controller 145)
receive a memory request for the processing-in-memory processor, wherein the memory request is associated with a region of the memory (eg., 0041 - memory operations may include one or more computations performed in a memory device having a processing-in-memory (PIM) feature.);
writing, into the memory, the region of the memory (eg., 0039 - The request generator RQG may generate requests for requesting a memory access such as a write operation and a read operation based on an address corresponding to the memory region; [0059] The command scheduler 165 may provide scheduled commands CMD_S to the memory 170 by scheduling commands ; [0063] The second buffer 163 may receive the rearranged data RDTA and may provide the all or some of the plurality of hosts 101, 102 and 103 with the rearranged data RDTA by a receiving order as an output data ODTA.); and
Lee does not disclose, but Kalamatianos discloses
a plurality of memory requests, the plurality of memory requests including a memory request for a processing-in-memory processor, wherein the memory request associated with a region of the memory (eg. 0011 - PIM instructions are placed in a PIM queue and are eventually dispatched to the PIM device for execution … data is present in a cache)…; ., [0012] If the data to be used by a PIM read instruction is in a cache and the data is marked dirty, a PIM read request will wait to be dispatched until the data is flushed from the cache to memory; [0038] In some examples, after a PIM request is issued by a processor core 106, 108, 110, 112, the PIM request is received by the coherency synchronizer 134. The coherency synchronizer 134 performs cache operation on the various caches of the core complexes 102, 104 to ensure that any cache entries for virtual and/or physical addresses identified in the PIM request remain coherent. For example, when a PIM request includes as an operand a virtual and/or physical address,)
the memory request of the processing-in-memory processor until the is transmitted from the memory controller to the memory (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory.; 0038 - After the appropriate cache operations have completed, the PIM request is transmitted to the memory controller 136 for offloading to the PIM device).
delaying scheduling the memory request of the processing-in-memory processor until the cached data is transmitted from the memory controller to the memory (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory.; 0038 - After the appropriate cache operations have completed, the PIM request is transmitted to the memory controller 136 for offloading to the PIM device; 0014 - issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos does not disclose, but Aga discloses
buffer, in the command queue, (eg. 0053 - instructions stored in the cache controller queues )
adjust an order of the buffered memory requests in the command queue (eg., 0055 - priority, memory-side processing commands, for which preloading of the corresponding memory-side processing results is to be used, specify a priority via, for example, one or more newly added or previously unused bit values or bits. The cache controller uses the priority specified in the memory-side processing command to decide when to issue the corresponding prefetch commands relative to other commands, i.e., in which order to issue commands. For example, prefetch commands are issued after all commands having a higher priority have been processed.; 0034 - performed by memory-side processing elements, such as PIM. )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, with Aga, providing the benefit of cache controllers store commands to perform preloading, such as prefetch commands, in queues to allow the cache controllers to manage issuance of the commands in a manner that reduces interference with other memory-side processing instructions or memory load/store operations (see Aga, 0044).
Claim 19 is rejected for reasons similar to Claim 4 above.
Claims 5, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250053336) and in view of Kalamatianos (US US 20220188233 A1) and Aga (cited above) and further in view of Kim (US 20200356305 A1)(hereinafter “Kim305”)
Claim 5. Lee does not disclose, but Kalamatianos discloses
wherein the memory controller is further configured to … after the one or more memory requests associated with the region of the memory are transmitted from the memory controller to the memory, wherein updating the ready bit enables scheduling the memory request of the processing-in-memory processor. (eg., 0066 - the PIM instruction waits at the coherency synchronizer 134 until the responses have been received, at which time the PIM instruction can be dispatched to the memory controller.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos and Aga does not disclose, but Kim305 discloses
update a ready bit of the memory request of the processing-in-memory processor in the command queue (eg. [0043] The memory controller 100 may also insert a PIM bit in a corresponding command generated from a memory request or a PIM request and provide the corresponding command to the memory device 200. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, and Aga with Kim305, providing the benefit of a to generate a PIM command from a PIM request requiring a processing operation in the memory device, and to schedule the PIM command together with the memory command (see Kim305, 0008).
Claim 13 is rejected for reasons similar to Claim 5 above.
Claim 20. Lee discloses
wherein the memory controller is configured to: adjust an order of the memory requests (eg., 0007 - generates output data by rearranging the internal data)
Lee does not disclose, but Kalamatianos discloses
such that one or more memory of the plurality of memory requests associated with the region of the memory are scheduled prior to the memory request of the processing-in-memory processor (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos and Aga does not disclose, but Kim305 discloses
update a ready bit of the memory request of the processing-in-memory processor in the command queue after the one or more memory requests associated with the region of the memory are transmitted from the memory controller to the memory, wherein updating the ready bit enables scheduling the memory request of the processing-in-memory processor (eg. [0043] The memory controller 100 may also insert a PIM bit in a corresponding command generated from a memory request or a PIM request and provide the corresponding command to the memory device 200. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, and Aga with Kim305, providing the benefit of a to generate a PIM command from a PIM request requiring a processing operation in the memory device, and to schedule the PIM command together with the memory command (see Kim305, 0008).
Claims 15, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250053336) and in view of Kalamatianos (US 20220188233 A1) and Aga (cited above) and further in view of Agarwal (US US 11625251 B1)
Claim 15. Lee in view of Kalamatianos and Aga does not disclose, but Agrawal discloses
receiving one or more markers to release write requests to the memory; and responsive to processing the one or more markers, writing, to the memory, the cached data associated with the region of the memory (eg., col 6:4-13 - PP level coherence directory 160 flushes first dirty data from at least one of cache 130A and 130B into the plurality of memory addresses based on a result of the second query. for each memory address marked as dirty in step 318, PP level coherence directory 160 may instruct host 115 to flush the corresponding dirty cache lines in cache 130A and/or cache 130B. The flush may result in memory write commands to update memory banks 185A and/or 185B with the latest data from cache 130A and 130B.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, and Aga with Agrawal, providing the benefit of a need for a solution to the technical problem of how to reduce coherence directory controller overhead when processing broadcast PIM or PNM commands (see Agrawal, col 2:9-12).
Claim 16. Lee in view of Kalamatianos and Aga does not disclose, but Agrawal discloses
wherein the one or more markers to release write requests to the memory are processed to release the write requests from at least one of a coherence directory configured to buffer the cached data or an interface between the coherence directory and a memory controller (eg., col 6:4-13 - PP level coherence directory 160 flushes first dirty data from at least one of cache 130A and 130B into the plurality of memory addresses based on a result of the second query. for each memory address marked as dirty in step 318, PP level coherence directory 160 may instruct host 115 to flush the corresponding dirty cache lines in cache 130A and/or cache 130B. The flush may result in memory write commands to update memory banks 185A and/or 185B with the latest data from cache 130A and 130B.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, and Kim247 with Agrawal, providing the benefit of a need for a solution to the technical problem of how to reduce coherence directory controller overhead when processing broadcast PIM or PNM commands (see Agrawal, col 2:9-12).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250053336) and in view of Kalamatianos (US 20220188233 A1) and Aga (cited above) and further in view of Seo (US 20220253246)
Claim 21. Lee in view of Kalamatianos and Aga does not disclose, but Seo discloses
wherein the memory controller is configured to identify, based on memory addresses in the memory request for the processing-in-memory processor, one or more pending write requests in the buffered memory requests that are associated with the region of the memory (eg., 0067 In operation 205, when the first memory request is the memory request for the PIM memory area, the memory controller 120 may generate a second memory request based on a generation parameter. For example, when an address of the first memory request corresponds to a PIM memory, the memory controller 120 may generate one or more second memory requests based on the generation parameter of the first memory request.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, and Kim247 with Aga, with Seo providing the benefit of request scheduler may be configured to transfer the one or more memory requests to a second buffer, in response to the one or more memory requests being a memory request for the general memory area (see Seo, 0020) provided a memory controller include a request generator configured to generate one or more memory requests based on a preset generation parameter (0017).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250053336) and in view of Kalamatianos (US 20220188233 A1) and Aga (cited above) and further in view of Seo (US 20220253246) and Alsop (US 20210373805)
Claim 21. Lee in view of Kalamatianos and Aga and Seo does not disclose, but Alsop discloses
wherein the command queue implements a comparator configured to compare memory addresses in the memory request for the processing-in-memory processor with addresses of the one or more pending write requests in the buffered memory requests (eg., 0018, 0021 - a special PIM command that is executed by multiple PIM-enabled memory modules and providing information specific to each individual command (e.g., address information, command index bits for a single command code sent to multiple memory modules, etc.) to the corresponding PIM-enabled memory modules via a data bus in an exemple embodiment. Furthermore, the solution allows different command or address information, e.g., different bank row and column values, to be provided to each PIM-enabled memory module. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, and Kim247 with Aga, with Seo with Alsop providing the benefit of better utilization of both the command bus and the data bus. Also, the approach, in an example embodiment, may be implemented with only minor changes to existing memory interfaces by repurposing existing unused command bits to identify special PIM commands and to specify PIM-enabled memory modules to process the special PIM commands. Further, changes to existing memory interfaces is reduced by utilizing the existing data bus, when it is underutilized, to communicate information specific to each individual command to the corresponding PIM-enabled memory modules (0018).
Response to Arguments
Applicant's arguments filed 7/13/2026 have been fully considered but they are not persuasive.
For claims 1, 7 and 18, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Lee does not disclose, but Kalamatianos discloses
a plurality of memory requests, the plurality of memory requests including a memory request for the processing-in-memory processor, the memory request associated with a region of the memory (eg. 0011 - PIM instructions are placed in a PIM queue and are eventually dispatched to the PIM device for execution … data is present in a cache)…; ., [0012] If the data to be used by a PIM read instruction is in a cache and the data is marked dirty, a PIM read request will wait to be dispatched until the data is flushed from the cache to memory; [0038] In some examples, after a PIM request is issued by a processor core 106, 108, 110, 112, the PIM request is received by the coherency synchronizer 134. The coherency synchronizer 134 performs cache operation on the various caches of the core complexes 102, 104 to ensure that any cache entries for virtual and/or physical addresses identified in the PIM request remain coherent. For example, when a PIM request includes as an operand a virtual and/or physical address,)
delaying scheduling the memory request of the processing-in-memory processor until the cached data is transmitted from the memory controller to the memory (eg., 0012 - a PIM read request will wait to be dispatched until the data is flushed from the cache to memory.; 0038 - After the appropriate cache operations have completed, the PIM request is transmitted to the memory controller 136 for offloading to the PIM device; 0014 - issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, providing the benefit of a coherency synchronizer that synchronizes cache states for a plurality of processor cores (see Kalamatianos, 0015) to ensure that data that is resident in a cache and is to be used in execution of a PIM instruction is flushed from the cache to memory (0010).
Lee in view of Kalamatianos does not disclose, but Aga discloses
buffer, in the command queue, (eg. 0053 - instructions stored in the cache controller queues )
adjust an order of the buffered memory requests in the command queue (eg., 0055 - priority, memory-side processing commands, for which preloading of the corresponding memory-side processing results is to be used, specify a priority via, for example, one or more newly added or previously unused bit values or bits. The cache controller uses the priority specified in the memory-side processing command to decide when to issue the corresponding prefetch commands relative to other commands, i.e., in which order to issue commands. For example, prefetch commands are issued after all commands having a higher priority have been processed.; 0034 - performed by memory-side processing elements, such as PIM. )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with PIM processing as disclosed by Lee with Kalamatianos, with Aga, providing the benefit of cache controllers store commands to perform preloading, such as prefetch commands, in queues to allow the cache controllers to manage issuance of the commands in a manner that reduces interference with other memory-side processing instructions or memory load/store operations (see Aga, 0044).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1, 7, 18, which are addressed above.
New Claims 21 and 22 are rejected above.
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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