Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Applicant is advised that should claim 3 be found allowable, claim 18 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-13, 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub. 2018/0189105 to Sanghvi et al. (hereafter Sanghvi).
As to claim 1, Sanghvi teaches the invention substantially as claimed including a method for a hardware thread allocation controller of a computing device, the method comprising [paragraph [0005], a method for executing concurrent threads on a hardware thread scheduler included in a data processing device; Fig. 2 and paragraph [0036], MMR 224 is configured to store various control and configuration parameters for the hardware thread scheduler 200. The parameters include parameters for configuring and controlling threads and parameters for configuring and controlling the task schedulers 210-221, 226-232]:
receiving, at the hardware thread allocation controller, a processor thread including one or more processing commands to be executed, and one or more preconditions for execution of the processor thread [paragraph [0024], hardware thread scheduler 200 is configurable to schedule the execution of a single thread of tasks or multiple concurrent threads of tasks by nodes of the VPAC 112; thread being a pipeline of one or more tasks; paragraph [0043], task scheduler is in an idle state 100 until enabled by the activation of a thread in which the task scheduler is included; Fig. 3 and paragraph [0044], Once the init_done signal is received, the task scheduler enters another wait state 308 waiting for certain conditions to be met to start execution of the task…The task scheduler may know that sufficient buffer space is available if the counter for the producer socket is less than the specified buffer depth for the producer socket. Once these conditions are met, the task scheduler enters the task start state 310...];
storing the processor thread in a shared memory of the hardware thread allocation controller [paragraph [0022], Blocks of storage area in the shared memory 238 may be designated as buffers for blocks of data being processed by the hardware accelerators 202-208];
based at least in part on detecting that the one or more preconditions for execution are met, assigning the processor thread to a hardware accelerator of the computing device for execution [paragraph [0043], task scheduler is in an idle state 100 until enabled by the activation of a thread in which the task scheduler is included; Fig. 3 and paragraph [0044], Once the init_done signal is received, the task scheduler enters another wait state 308 waiting for certain conditions to be met to start execution of the task…The task scheduler may know that sufficient buffer space is available if the counter for the producer socket is less than the specified buffer depth for the producer socket. Once these conditions are met, the task scheduler enters the task start state 310...; paragraph [0066], task scheduler 704 starts execution of the hardware accelerator 706 which consumes the block of data in the shared memory 708]; and
wherein the hardware thread allocation controller is configured to receive the processor thread, store the processor thread in the shared memory, and assign the processor thread to the hardware accelerator through hardware programming of the hardware thread allocation controller [hardware programming and/or implementation, Figs. 2 and 4-5; paragraphs [0023], [0032], the logic of the hardware thread scheduler is managed by means of DMA channels together with the scheduler crossbar (222) and the Memory Mapped Registers (224) that includes a control register, a count register, a consumer control register, a producer control register, etc.; paragraph [0036], MMR of hardware thread scheduler being programmed].
Sanghvi does not specifically teach storing the processor thread in a thread queue. However, Sanghvi disclosed the use of shared memory in facilitating the execution of tasks of the thread, and the task scheduler entering a wait state (i.e. tasks not process by a task scheduler is inherently in a wait state and temporarily held/stored awaiting processing) [paragraph 44]. Furthermore, a queue is a well-known data structure. It would have been obvious before the effective filing date of the claimed invention to have implemented a well-known data structure in storing the thread to achieve the predictable result of storing tasks of a thread awaiting execution as being considered by Sanghvi.
As to claim 2, Sanghvi teaches the invention substantially as claimed including wherein the processor thread is associated with a header entry of the hardware thread allocation controller, the header entry specifying a first processing command of the one or more processing commands to be executed [indication or entry of initial/producer task, paragraph 77]. Sanghvi does not specifically teach in a header queue. However, Sanghvi disclosed the use of shared memory and/or buffer space in facilitating the execution of tasks of the thread, and the task scheduler entering a wait state (i.e. tasks not process by a task scheduler is inherently in a wait state and temporarily held/stored awaiting processing) [paragraphs 40,44 and 77]. Furthermore, a queue is a well-known data structure. It would have been obvious before the effective filing date of the claimed invention to have implemented a well-known data structure in storing the thread to achieve the predictable result of storing tasks of a thread awaiting execution as being considered by Sanghvi.
As to claim 3, Sanghvi teaches the invention substantially as claimed including an association between the one or more preconditions for the processor thread and the header entry [initialization/indication/entry of initial/producer task and conditions met before starting execution of the task in the thread, paragraphs 73 and 77]. Sanghvi does not specifically teach in a precondition table. However, Sanghvi disclosed the use of shared memory and/or buffer space in facilitating the execution of tasks of the thread, and the task scheduler entering a wait state (i.e. tasks not process by a task scheduler is inherently in a wait state and temporarily held/stored awaiting processing) until certain conditions are met [paragraphs 40,44 and 77]. Furthermore, a table is a well-known data structure. It would have been obvious before the effective filing date of the claimed invention to have implemented a well-known data structure in storing the preconditions to achieve the predictable result of associating stored precondition with thread/task execution as being considered by Sanghvi.
As to claim 7, Sanghvi teaches the invention substantially as claimed including wherein the hardware accelerator is one of two or more hardware accelerators of the computing device, and wherein the hardware thread allocation controller further comprises a work distribution unit configured to assign processor threads to the two or more hardware accelerators [scheduling thread(s) and/or tasks among hardware accelerators, Figs. 2 and 6-8 and corresponding text]. Sanghvi does not specifically teach the assignment of processor threads to accelerators based on an accelerator allocation history of each hardware accelerator. However, processor/CPU affinity is well known in the art. It would have been obvious before the effective filing date of the claimed invention to have implemented a well-known to achieve the predictable result of cache efficiency.
As to claim 8, Sanghvi teaches the invention substantially as claimed including wherein processing commands of the processor thread are allocated between at least two of the two or more hardware accelerators [scheduling thread(s) and/or tasks among hardware accelerators, Figs. 2 and 6-8 and corresponding text].
As to claim 9, Sanghvi teaches the invention substantially as claimed including wherein the one or more preconditions for execution of the processor thread include detecting that prerequisite data associated with the processor thread has been generated [paragraphs [0044] and [0046], signal or data indicating conditions are met].
As to claim 10, Sanghvi teaches the invention substantially as claimed including wherein the one or more preconditions for execution of the processor thread include detecting that there is sufficient space in memory of the computing device to store data to be generated through execution of the processor thread [paragraphs [0044] and [0046], condition being sufficient buffer space available are met].
As to claims 11-13 and 15-17, Sanghvi teaches for a hardware thread allocation controller of a computing device substantially as claimed in claims 1-3, 7 and 9-10, therefore Sanghvi teaches the computing device for implementing the method.
As to claims 18 and 20, these claims are rejected for the same reason as claims 1-3 and 7 above.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PG Pub. 2018/0189102 and 2024/0345870 disclosed a hardware thread schedulers with hardware task schedulers.
Allowable Subject Matter
Claims 4-6, 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Sanghvi disclosed in paragraph [0005], a method for executing concurrent threads on a hardware thread scheduler included in a data processing device; Fig. 2 and paragraph [0036], MMR 224 is configured to store various control and configuration parameters for the hardware thread scheduler 200. The parameters include parameters for configuring and controlling threads and parameters for configuring and controlling the task schedulers 210-221, 226-232]: paragraph [0024], hardware thread scheduler 200 is configurable to schedule, hence received, the execution of a single thread of tasks or multiple concurrent threads of tasks by nodes of the VPAC 112; thread being a pipeline of one or more tasks; paragraph [0043], task scheduler is in an idle state 100 until enabled by the activation of a thread in which the task scheduler is included; Fig. 3 and paragraph [0044], Once the init_done signal is received, the task scheduler enters another wait state 308 waiting for certain conditions to be met to start execution of the task…The task scheduler may know that sufficient buffer space is available if the counter for the producer socket is less than the specified buffer depth for the producer socket. Once these conditions are met, the task scheduler enters the task start state 310...]; paragraph [0022], Blocks of storage area in the shared memory 238 may be designated as buffers for blocks of data being processed by the hardware accelerators 202-208; paragraph [0043], task scheduler is in an idle state 100 until enabled by the activation of a thread in which the task scheduler is included; Fig. 3 and paragraph [0044], Once the init_done signal is received, the task scheduler enters another wait state 308 waiting for certain conditions to be met to start execution of the task…The task scheduler may know that sufficient buffer space is available if the counter for the producer socket is less than the specified buffer depth for the producer socket. Once these conditions are met, the task scheduler enters the task start state 310...; paragraph [0066], task scheduler 704 starts execution of the hardware accelerator 706 which consumes the block of data in the shared memory 708]; and hardware programming and/or implementation of the thread scheduler, Figs. 2 and 4-5; paragraphs [0023], [0032], the logic of the hardware thread scheduler is managed by means of DMA channels together with the scheduler crossbar (222) and the Memory Mapped Registers (224) that includes a control register, a count register, a consumer control register, a producer control register, etc.; paragraph [0036], MMR of hardware thread scheduler being programmed. The prior art(s) of record when taken individually or in combination do not expressly teach or render obvious the limitations “receiving a subsequent processing command, determining that the subsequent processing command corresponds to an existing processor thread stored in the thread queue, and appending the subsequent processing command to the existing processor thread” and/or “a thread queue management block configured to dynamically assign a subset of address space within the thread queue to the processor thread based on a quantity of the one or more processing commands of the processor thread” as a whole as recited in claims 4-6, 14 and 19.
Neither a reference uncovered that would have provided a basis of evidence for asserting a motivation, nor one of ordinary skill in the art before the effective filing date of the claimed invention, knowing the teaching of the prior arts of record would have combined them to arrive at the present invention as recited in the context of claims 4-6, 14 and 19 as a whole.
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/QING YUAN WU/Primary Examiner, Art Unit 2199
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