DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-26 have been examined and are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/02/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 11 and 26 are objected to because of the following informalities:
Claim 11, line 5: intentional use term: but. Recommend that claim limitation should positively recite.
Claim 26, line 5: intentional use term: but. Recommend that claim limitation should positively recite. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: claim 17 is an independent hardware claim describing a cloaking circuit yet is missing a transitional phrase such as “comprising”, “consisting of”, or “consisting essentially of”; so it unclear what is the preamble or body. Therefore, the scope is not well defined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 10-22 and 24-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gross et al, hereinafter (“Gross”) US PG Publication 20200245140 A1 was submitted in 09/02/2025 IDS.
Regarding claims 1 and 17-18, Gross teaches a circuit comprising; a cloaking circuit configured to; and method of a cloaking circuit coupled to an electrical terminal coupled to a processing circuit on an integrated circuit (IC), wherein a first signal on the electrical terminal indicates circuit activity of the processing circuit, the method comprising:
an electrical terminal; [Gross et al 20200245140A1 ¶0009 electrical lead OR ¶0035 an antenna 106 ]
a processing circuit disposed on an integrated circuit (IC) chip and coupled to the electrical terminal, wherein a first signal on the electrical terminal indicates circuit activity of the processing circuit; [Gross et al 20200245140A1 ¶¶0009 0028 0031 the electrical lead, which is coupled to a ground line in the computer system; hardware modules can include, but are not limited to, application-specific integrated circuit (ASIC) chips. FIG. 1, a server 102 generates EMI emissions 104 during normal operation. These EMI emissions 104/corresponding analog signals can be monitored using an antenna 106. Antenna 106 converts the EMI emissions 104 into corresponding analog signals, which feed through a receiver 108. ] and
a cloaking circuit coupled to the electrical terminal and configured to modify the first signal on the electrical terminal to obfuscate the indications of the circuit activity. [Gross et al 20200245140A1 ¶0035 Fig. 3 shows the EMI emissions 104 can be monitored using an antenna 106 that converts the EMI emissions 104 into corresponding analog signals, which feed through a receiver 108 that converts the analog electrical into corresponding digital signals that feed into frequency-domain converter 110. Frequency-domain converter 110 performs an FFT operation on the digital signals that produces a set of time-series frequency signals 112. Next, time-series frequency signals 112 feed into a camouflaging-signal generator 314, which generates a corresponding camouflaging signal 316]
Regarding claim 2, Gross teaches claim 1 as described above.
the cloaking circuit further configured to generate a cloaking signal on the electrical terminal to modify the first signal. [Gross et al 20200245140A1 ¶0035 Frequency-domain converter 110 performs an FFT operation on the digital signals that produces a set of time-series frequency signals 112. Next, time-series frequency signals 112 feed into a camouflaging-signal generator 314, which generates a corresponding camouflaging signal 316.]
Regarding claims 3 and 20, Gross teaches claim 2 as described above.
Gross teaches the cloaking circuit configured to: analyze the first signal to detect the indications of the circuit activity; [Gross ¶0038 analyzable information content from the EMI emissions from the server] and generate the cloaking signal based on the circuit activity. [See ¶0035 cloaking signal generated from the EMI emissions 104 into corresponding analog signals]
Regarding claim 4, Gross teaches claim 3 as described above.
Gross teaches the cloaking circuit comprising: a signal analysis circuit configured to analyze the first signal; [Gross ¶0031 Frequency-domain converter 110 then performs an FFT operation on the digital signals] and a signal generation circuit configured to generate the cloaking signal. [Gross ¶0035 Next, time-series frequency signals 112 feed into a camouflaging-signal generator 314, which generates a corresponding camouflaging signal 316. ]
Regarding claims 5, Gross teaches claim 3 as described above.
Gross teaches the cloaking circuit further configured to: convert the first signal to first digital information; [Gross ¶0035 Frequency-domain converter 110 performs an FFT operation on the digital signals] generate second digital information based on the first digital information; [Gross ¶0031 recognizes packet-content information 116 and transactional activity 118 in the time-series frequency signals 112 based on the received EMI emissions] and generate the cloaking signal based on the second digital information. [Gross ¶0035 time-series frequency signals 112 feed into a camouflaging-signal generator 314, which generates a corresponding camouflaging signal 316.]
Regarding claims 6 and 22, Gross teaches claim 4 as described above.
Gross teaches the cloaking circuit further configured to: measure a power spectral density (PSD) of the first signal; [Gross ¶0041 output of the FFT, the system produces a power spectral density (PSD] compare the PSD to a target PSD; [Gross ¶0041 which represents a spectral energy distribution of the EMI signals (step 412). ] and generate the cloaking signal based on a difference between the PSD and the target PSD. [Gross ¶0041 Next, the system produces an antiphase signal to camouflage the EMI signals by lagging a phase angle of the PSD by 180° (step 414).]
Regarding claim 10, Gross teaches claim 3 as described above.
Gross teaches wherein: the electrical terminal comprises a first bit of a bus; [Gross ¶0031 read EMI patterns connected to a ground wire in server 102] and the cloaking circuit is further configured to generate a second cloaking signal on a second electrical terminal comprising a second bit of the bus.[Gross ¶0035 which generates a corresponding camouflaging signal 316; Examiner interprets a corresponding signal to another different server 102 EMI emission; hence analogous to a second electrical terminal monitored by the antenna 106]
Regarding claim 11, Gross teaches claim 2 as described above.
Gross teaches further configured to: detect first signal activity in the first signal indicating a first type of transaction corresponding to the circuit activity of the processing circuit; [Gross ¶0037 idle between workload transactions, the time-domain camouflaging technique causes the cores to execute random transactions. Examiner interprets the activity and/or inactivity is analogous the circuit activity of the first signal] and generate, in the cloaking signal, second signal activity resembling the first type of transaction but not corresponding to the circuit activity of the processing circuit. [Gross ¶0036 developed three techniques to camouflage EMI fingerprints, namely: (1) time-domain camouflaging; (2) antiphase camouflaging; and (3) frequency-domain camouflaging. ¶0037 For time-domain camouflaging, a software-defined radio (SDR) associated with each server monitors the dynamic amplitude of the EMI emissions in real time.]
Regarding claim 12, Gross teaches claim 1 as described above.
Gross teaches wherein the cloaking signal does not correspond to circuit activity in the processing circuit. [See Gross ¶0037. Examiner interprets the converse must be true]
Regarding claim 13, Gross teaches claim 1 as described above.
Gross teaches wherein the electrical terminal and the processing circuit are disposed on the IC chip. [Gross ¶0038 special purpose chip]
Regarding claim 14, Gross teaches claim 1 as described above.
Gross teaches wherein: the IC chip is disposed on a substrate; [Gross ¶0028 application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs)] the cloaking circuit is disposed on a second IC chip further disposed on the substrate; [Gross ¶0028 application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs)] and the electrical terminal is disposed on the substrate. [Gross ¶0028 application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs)]
Regarding claim 15, Gross teaches claim 8 as described above.
Gross teaches the cloaking circuit configured to: generate the cloaking signal comprising pseudo-random noise on the electrical terminal based on a pseudo-random number generator. [Gross ¶0008 random noise]
Regarding claim 24, Gross teaches claim 19 as described above.
Gross teaches wherein: generating a pseudo-random number; [Gross ¶0008] and generating the cloaking signal comprising pseudo-random noise based on the pseudo-random number. [See Gross ¶0008]
Regarding claim 26, Gross teaches claim 19 as described above.
Gross teaches wherein: detecting first signal activity in the first signal indicating a first type of transaction comprising a transfer of data of the processing circuit on the electrical terminal; [Gross ¶0031 EMI fingerprint technology; Electromagnetic-Interference Detectors] and generating, in the cloaking signal, second signal activity resembling the first type of transaction but not corresponding to a transfer of data of the processing circuit. [Gross ¶0033 a standard datacenter rack of servers to eavesdrop on transactional activity in slot N+1 or N−1 in the same rack. It is also possible for a malicious actor to use a hand-held wand or other external antenna to monitor transactional activity inside a server. ]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Gross et al, hereinafter (“Gross”) US PG Publication 20200245140 A1 was submitted in 09/02/2025 IDS, in view of US PG Publication Sanchez 20160173067 A1.
Regarding claim 7, Gross teaches claim 5 as described above.
However, Gross fails to explicitly teach but Sanchez teaches wherein: the first signal comprises voltage oscillations at a first frequency and harmonic frequencies of the first frequency; [Sanchez ¶¶0008 multiple signals for reference PLL circuit allows for lowering of the voltage controlled oscillator (VCO) Fmax that is required (maximum frequency required). ¶0019 modified cloak signals 138] and the cloaking circuit is further configured to: detect the first frequency and the harmonic frequencies in the first digital information; [Sanchez ¶0019 the CGC circuits 144 can have an effective set up time suitable for use with the 1 GHz frequency of the additional clock signal 118 rather than the 2 GHz frequency a the modified cloak signals 138.] and generate the cloaking signal comprising the voltage oscillations at least a third frequency different than the first frequency and the harmonic frequencies. [Sanchez ¶0046 a second input terminal undo second output terminal, where the multiplication circuit portion includes a third input terminal and a third output terminal]
Gross teaches all the features of claims 1 and 17-18 not wherein: the first signal comprises voltage oscillations at a first frequency and harmonic frequencies of the first frequency; and the cloaking circuit is further configured to: detect the first frequency and the harmonic frequencies in the first digital information; and generate the cloaking signal comprising the voltage oscillations at least a third frequency different than the first frequency and the harmonic frequencies. Gross teaches camouflaging EMI fingerprints in enterprise computer systems to enhance system security. Sanchez teaches a system and method for enhanced clocking operation. Because both Gross and Sanchez teach distribution of electrical signals via wires, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention was made to try use of the duty cycle correction (DCC), clock gating cell (CGC), circuit blocks, multiple phase-locked loop (PLL) circuits, and/or clock gating cells as taught by Sanchez [Sanchez ¶0008].
Regarding claim 8, Gross teaches claim 1 as described above.
However, Gross fails to explicitly teach but Sanchez teaches wherein the electrical terminal provides a supply voltage to power the processing circuit. [Sanchez ¶0036]
Gross teaches all the features of claims 1 and 17-18 not wherein: the first signal comprises voltage oscillations at a first frequency and harmonic frequencies of the first frequency; and the cloaking circuit is further configured to: detect the first frequency and the harmonic frequencies in the first digital information; and generate the cloaking signal comprising the voltage oscillations at least a third frequency different than the first frequency and the harmonic frequencies. Gross teaches camouflaging EMI fingerprints in enterprise computer systems to enhance system security. Sanchez teaches a system and method for enhanced clocking operation. Because both Gross and Sanchez teach distribution of electrical signals via wires, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention was made to try use of the duty cycle correction (DCC), clock gating cell (CGC), circuit blocks, multiple phase-locked loop (PLL) circuits, and/or clock gating cells as taught by Sanchez [Sanchez ¶0008].
Regarding claim 9, Gross teaches claim 3 as described above.
However, Gross fails to explicitly teach but Sanchez teaches wherein: the first signal includes first voltage oscillations having a first phase and a first magnitude; [Sanchez ¶¶0008 0036 0040 lower VCO gain; first clock signal] and the cloaking circuit is further configured to generate the cloaking signal including the first voltage oscillations having the first magnitude and a second phase opposite to the first phase. [Sanchez ¶0009 second input signal]
Gross teaches all the features of claims 1 and 17-18 not wherein: the first signal includes first voltage oscillations having a first phase and a first magnitude; and the cloaking circuit is further configured to generate the cloaking signal including the first voltage oscillations having the first magnitude and a second phase opposite to the first phase. Gross teaches camouflaging EMI fingerprints in enterprise computer systems to enhance system security. Sanchez teaches a system and method for enhanced clocking operation. Because both Gross and Sanchez teach distribution of electrical signals via wires, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention was made to try use of the duty cycle correction (DCC), clock gating cell (CGC), circuit blocks, multiple phase-locked loop (PLL) circuits, and/or clock gating cells as taught by Sanchez [Sanchez ¶0008].
Regarding claim 23, Gross teaches claim 21 as described above.
However, Gross fails to explicitly teach but Sanchez teaches wherein: detecting a first frequency and harmonic frequencies of the first signal in the first digital information; [See Sanchez ¶¶0008 0036 0040] and generating the cloaking signal comprising at least a third frequency different than the first frequency and the harmonic frequencies. [See ¶¶0008 0036 0040]
Gross teaches all the features of claims 1 and 17-18 not wherein: the first signal includes first voltage oscillations having a first phase and a first magnitude; and the cloaking circuit is further configured to generate the cloaking signal including the first voltage oscillations having the first magnitude and a second phase opposite to the first phase. Gross teaches camouflaging EMI fingerprints in enterprise computer systems to enhance system security. Sanchez teaches a system and method for enhanced clocking operation. Because both Gross and Sanchez teach distribution of electrical signals via wires, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention was made to try use of the duty cycle correction (DCC), clock gating cell (CGC), circuit blocks, multiple phase-locked loop (PLL) circuits, and/or clock gating cells as taught by Sanchez [Sanchez ¶0008].
Claim(s) 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gross et al, hereinafter (“Gross”) US PG Publication 20200245140 A1 was submitted in 09/02/2025 IDS, in view of Govindaraj et al, hereinafter (“Govindaraj”) US PG Publication 20170033591 A1.
Regarding claim 16, Gross teaches claim 1 as described above.
However, Gross fails to explicitly teach but Govindaraj teaches the cloaking circuit further comprising a tunable filter, wherein the cloaking circuit is further configured to: analyze the first signal to detect the indications of the circuit activity; [Govindaraj ¶0137 The method described above may measure the power at any single frequency if a tunable filter is used.] and tune the tunable filter to modify the first signal to reduce the indications of the circuit activity on the electrical terminal. [Govindaraj ¶0178 The matching network can be configured to alter the switching components in the RX matching and switching circuitry 512 to modify the harmonics of the receive circuitry 510.]
Gross teaches all the features of claims 1 and 17-18 not the cloaking circuit further comprising a tunable filter, wherein the cloaking circuit is further configured to: analyze the first signal to detect the indications of the circuit activity; and tune the tunable filter to modify the first signal to reduce the indications of the circuit activity on the electrical terminal. Gross teaches camouflaging EMI fingerprints in enterprise computer systems to enhance system security. Govindaraj teaches detecting and characterizing an object for wireless charging. Because both Gross and Govindaraj teach distribution of electrical signals via wires, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention was made to try filter and matching circuit as taught by Govindaraj [Sanchez ¶0045].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gomez-Diaz teaches 11616299 B2 teaches Nonreciprocal reflectarrary antennas based on time-modulated unit-cells
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SAKINAH WHITE-TAYLOR
Primary Examiner
Art Unit 2407
/Sakinah White-Taylor/Primary Examiner, Art Unit 2407