DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities: Claim 10, line 10 recites “CCM”, which should be -- a continuous conduction mode (CCM) – in order to provides clear explanation of the definition of the term; Claim 10, line 12 recites “DCM”, which should be -- a discontinuous conduction mode (DCM) – in order to provides clear explanation of the definition of the term.
Appropriate correction is required.
Claim 15 is objected to because of the following informalities: Claim 15, line 11 recites “CCM”, which should be -- a continuous conduction mode (CCM) – in order to provides clear explanation of the definition of the term; Claim 15, line 13 recites “DCM”, which should be -- a discontinuous conduction mode (DCM) – in order to provides clear explanation of the definition of the term.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 10-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al. (US 2022/0294355), hereinafter Lin.
Regarding claim 1, Lin discloses (see figures 1-9) a controller (figure 5, part 510) used in an isolated switching converter (figure 5, part 500) having a transformer (figure 5, part 560) and a primary switch (figure 5, part 570) (paragraph [0045]; As shown in FIG. 5, the switching power supply 500 is a flyback switching power supply), the controller (figures 5 and 8, part 510) comprising: a gate driver (figure 8, part gate driver generated by 816, 810, Vcc, 824, 830, 832, 842, 844 and 820/822) configured to provide a driving control signal (figure 8, part 548) for driving the primary switch (figures 5 and 8, part 570) and to receive information indicating a mode (figure 8, part through 877; discontinuous conduction mode [DCM] or the continuous conduction mode [CCM]) of operation of the isolated switching converter (figure 5, part 500) (paragraphs [0062]-[0069]; if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude, and if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude… if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases), the driving control signal (figure 8, part 548) is controlled to being switchable (figure 8, part through 877 at 816) between a first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1) and a second driving strength (figures 6 and 8, part second driving strength in 548 at DCM; before t1) based on the information (figure 8, part through 877), and wherein when the isolated switching converter (figure 5, part 500) operates in a continuous conduction mode (CCM) (figure 6, part CCM after t1), the driving control signal (figure 8, part 548) is controlled to have the first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1), and when the isolated switching converter (figure 5, part 500) operates in a discontinuous conduction mode (DCM) (figure 6, part DCM before t1), the driving control signal (figure 8, part 548) is controlled to have the second driving strength (figures 6 and 8, part second driving strength in 548 at DCM; before t1) stronger than the first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1) (paragraphs [0053]-[0056]; FIG. 6 shows a simplified timing diagram for the switching power supply 500 as shown in FIG. 5 that changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode… the feedback signal 542 becomes larger than a predetermined feedback threshold 640 (e.g., Vfb_th) at time t1 according to certain embodiments. For example, at time t1, the output voltage 552 (e.g., Vout) decreases with time as shown by the waveform 652. As an example, if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode… the drive signal 548 increases more slowly in the continuous conduction mode than in the discontinuous conduction mode as shown by the waveform 648. For example, the drive signal 548 includes rising edges 660 and 662 in the discontinuous conduction mode and also includes rising edges 664 and 666 in the continuous conduction mode. As an example, the drive signal 548 increases faster at the rising edges 660 and 662 in the discontinuous conduction mode than at the rising edges 664 and 666 in the continuous conduction mode… the drive signal 548 increases more slowly at rising edges in the continuous conduction mode than at rising edges in the discontinuous conduction mode. For example, making the drive signal 548 increase more slowly in the continuous conduction mode than in the discontinuous conduction mode reduces a current that flows through the switch 570 (e.g., a transistor) and a current that flows through the switch 572 (e.g., a transistor) when both the switch 570 (e.g., a transistor) and the switch 572 (e.g., a transistor) are closed (e.g., turned on), significantly reducing (e.g., lowering) a spike in magnitude).
Regarding claim 2, Lin discloses everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) the driving control signal (figures 5 and 8, part 548) is configured to have driving parameters (figures 5 and 8, part 548) (figure 6, part S1 Vg), the driving parameters (figures 5 and 8, part 548) (figure 6, part S1 Vg) comprise at least one of a driving current, a driving voltage, a rising slope, a rising time and a gate driver impedance (figures 5 and 8, part 548) (figure 6, part S1 Vg).
Regarding claim 3, Lin discloses everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) the driving control signal (figures 5 and 8, part 548) is controlled to have the first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1) by adjusting one driving parameter (figure 8, part through 816) to be a first value (figure 8, part first value of 825 at CCM); and the driving control signal (figures 5 and 8, part 548) is controlled to have the second driving strength (figures 6 and 8, part second driving strength in 548 at DCM; before t1) by adjusting the one driving parameter (figure 8, part through 816) to be a second value (figure 8, part second value of 825 at DCM) higher than the first value (figure 8, part first value of 825 at CCM) (paragraphs [0062]-[0069]; if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude, and if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude… if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases).
Regarding claim 4, Lin discloses everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) the isolated switching converter (figure 5, part 500) operates in DCM during normal operation (figure 6, part DCM before t1), and switches (figure 6, part at t1) to operate in CCM (figure 6, part CCM after t1) from DCM (figure 6, part DCM before t1) when a peak power mode is enabled (figures 6 and 8, part peak power mode enabled at t1; when the feedback signal 542 becomes larger than the predetermined feedback threshold 855 (e.g., Vfb_th) and the detected pulse width of the drive signal 548 becomes smaller than the predetermined time threshold (e.g., Ton_th)) (paragraphs [0053]-[0056]; the feedback signal 542 becomes larger than a predetermined feedback threshold 640 (e.g., Vfb_th) at time t1 according to certain embodiments. For example, at time t1, the output voltage 552 (e.g., Vout) decreases with time as shown by the waveform 652. As an example, if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode).
Regarding claim 5, Lin discloses everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) a peak power detection circuit (figure 5, part peak power detection circuit generated by 530) configured to receive information indicating if a peak power mode is enabled (figures 5 and 6, part information 532 indicating if a peak power mode is enabled), to generate an indication signal (figure 5, part indication signal from 530) based on the information (figures 5 and 6, part information 532), and to transmit the information (figures 5 and 6, part through 536) from a secondary side (figures 5 and 6, part secondary side of 500) to a primary side (figures 5 and 6, part primary side of 500) through an isolation circuit (figure 5, part 540); and a decode circuit (figure 8, part decode circuit generated by 850 and 870) configured to receive the information (figures 5, 6 and 8, part through 516) indicating if the peak power mode is enabled (figures 5 and 6, part a peak power mode is enabled at t1) through the isolation circuit (figure 5, part 540), and to determine if the isolated switching converter (figure 5, part 500) to enter CCM (figure 6, part CCM after t1) (paragraphs [0053]-[0056]; the feedback signal 542 becomes larger than a predetermined feedback threshold 640 (e.g., Vfb_th) at time t1 according to certain embodiments. For example, at time t1, the output voltage 552 (e.g., Vout) decreases with time as shown by the waveform 652. As an example, if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode).
Regarding claim 10, Lin discloses (see figures 1-9) an isolated switching converter (figure 5, part 500), comprising: a transformer (figure 5, part 560), having a primary winding (figure 5, part 562) and a secondary winding (figure 5, part 564); a primary switch (figure 5, part 570) coupled to the primary winding (figure 5, part 562) (paragraph [0045]; As shown in FIG. 5, the switching power supply 500 is a flyback switching power supply); and a controller (figures 5 and 8, part 510) comprising a gate driver (figure 8, part gate driver generated by 816, 810, Vcc, 824, 830, 832, 842, 844 and 820/822) configured to provide a driving control signal (figure 8, part 548) for driving the primary switch (figures 5 and 8, part 570), the gate driver (figure 8, part gate driver generated by 816, 810, Vcc, 824, 830, 832, 842, 844 and 820/822) is configured to receive information indicating a mode (figure 8, part through 877; discontinuous conduction mode [DCM] or the continuous conduction mode [CCM]) of operation of the isolated switching converter (figure 5, part 500) (paragraphs [0062]-[0067]; if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude, and if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude… if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases), the driving control signal (figure 8, part 548) is controlled to being switchable (figure 8, part through 877 at 816) between a first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1) and a second driving strength (figures 6 and 8, part second driving strength in 548 at DCM; before t1) based on the information (figure 8, part through 877), and wherein when the isolated switching converter (figure 5, part 500) operates in CCM (figure 6, part CCM after t1), the driving control signal (figure 8, part 548) is controlled to have the first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1), and when the isolated switching converter (figure 5, part 500) operates in DCM (figure 6, part DCM before t1), the driving control signal (figure 8, part 548) is controlled to have the second driving strength (figures 6 and 8, part second driving strength in 548 at DCM; before t1) stronger than the first driving strength (figures 6 and 8, part first driving strength in 548 at CCM; after t1) (paragraphs [0053]-[0056]; FIG. 6 shows a simplified timing diagram for the switching power supply 500 as shown in FIG. 5 that changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode… the feedback signal 542 becomes larger than a predetermined feedback threshold 640 (e.g., Vfb_th) at time t1 according to certain embodiments. For example, at time t1, the output voltage 552 (e.g., Vout) decreases with time as shown by the waveform 652. As an example, if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode… the drive signal 548 increases more slowly in the continuous conduction mode than in the discontinuous conduction mode as shown by the waveform 648. For example, the drive signal 548 includes rising edges 660 and 662 in the discontinuous conduction mode and also includes rising edges 664 and 666 in the continuous conduction mode. As an example, the drive signal 548 increases faster at the rising edges 660 and 662 in the discontinuous conduction mode than at the rising edges 664 and 666 in the continuous conduction mode… the drive signal 548 increases more slowly at rising edges in the continuous conduction mode than at rising edges in the discontinuous conduction mode. For example, making the drive signal 548 increase more slowly in the continuous conduction mode than in the discontinuous conduction mode reduces a current that flows through the switch 570 (e.g., a transistor) and a current that flows through the switch 572 (e.g., a transistor) when both the switch 570 (e.g., a transistor) and the switch 572 (e.g., a transistor) are closed (e.g., turned on), significantly reducing (e.g., lowering) a spike in magnitude).
Regarding claim 11, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 12, claim 3 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 13, claim 4 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 14, claim 5 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 16, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 17, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 18, Lin discloses everything claimed as applied above (see claim 17). Further, Lin discloses (see figures 1-9) providing information (figure 5, part information from 530) indicating if a peak power mode is enabled (figures 5 and 6, part peak power mode is enabled at t1) and sending the information (figure 5, part information from 530) to an isolation circuit (figure 5, part 540); and receiving the information (figure 5, part information from 530) indicating if the peak power mode is enabled (figures 5 and 6, part peak power mode is enabled at t1) through the isolation circuit (figure 5, part 540) at a primary side (figure 5, part primary side of 500).
Regarding claim 19, claim 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0294355), hereinafter Lin, in view of Chang et al. (US 2017/0155335), hereinafter Chang.
Regarding claim 8, Lin discloses everything claimed as applied above (see claim 5). Further, Lin discloses (see figures 1-9) the peak power detection circuit (figure 5, part peak power detection circuit generated by 530) comprises: a first comparison circuit (figure 5, part 530) configured to compare (figure 5, part 530) the output voltage (figure 5, part Vout) of the isolated switching converter (figure 5, part 500) with a first threshold voltage (figure 5, part inverting input threshold voltage) and to provide a first comparison signal (figure 5, part output of 530) based on the comparison (figure 5, part 530); and to provide the indication signal (figure 5, part indication signal from 530). However, Lin does not expressly disclose a second comparison circuit configured to compare the compensation signal with a second threshold voltage and to provide a second comparison signal based on the comparison; and a AND gate circuit configured receive the first comparison signal and the second comparison signal.
Chang teaches (see figures 1-9) a second comparison circuit (figure 4, part 737) configured to compare the compensation signal (figure 4, part COMP) with a second threshold voltage (figure 4, part second threshold voltage input to inverting input) and to provide a second comparison signal (figure 4, part VCV) based on the comparison (figure 4, part 737); and a AND gate circuit (figure 4, part 739) configured receive the first comparison signal (figures 4 and 9, part ZC) and the second comparison signal (figure 4, part VCV), and to provide the indication signal (figure 4, part indication signal output from 739).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Lin with the controller features as taught by Chang and obtain the peak power detection circuit comprises: a first comparison circuit configured to compare the output voltage of the isolated switching converter with a first threshold voltage and to provide a first comparison signal based on the comparison; a second comparison circuit configured to compare the compensation signal with a second threshold voltage and to provide a second comparison signal based on the comparison; and a AND gate circuit configured receive the first comparison signal and the second comparison signal, and to provide the indication signal, because it provides more efficient and robust controller in order to obtain more accurate control operation.
Regarding claim 20, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0294355), hereinafter Lin, in view of Chang (US 2016/0352232), hereinafter Chang2.
Regarding claim 9, Lin discloses everything claimed as applied above (see claim 5). Further, Lin discloses (see figures 1-9) the peak power detection circuit (figure 5, part peak power detection circuit generated by 530) provides the indication signal (figure 5, part indication signal from 530). However, Lin does not expressly disclose a peak power enable pin, the peak power detection circuit provides the indication signal based on a status at the peak power enable pin.
Chang2 teaches (see figures 1-9) a peak power enable pin (figure 1B, part peak power enable pin generated by CC1/CC2), the peak power detection circuit (figure 1B and 5, part peak power detection circuit generated by 120 and 150) provides the indication signal (figure 1B and 5, part indication signal at OPTO) based on a status at the peak power enable pin (figure 1B, part peak power enable pin generated by CC1/CC2) (figure 6) (paragraphs [0044]-[0051]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Lin with the controller features as taught by Chang2 and obtain a peak power enable pin, the peak power detection circuit provides the indication signal based on a status at the peak power enable pin, because it provides more efficient controller with power saving (paragraph [0007]).
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 6, an error amplifying circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive a feedback signal representative of an output voltage of the isolated switching converter, the second input terminal is configured to receive a reference voltage, based on the difference between the feedback signal and the reference voltage, the error amplifying circuit provides a compensation signal at the output terminal; a primary ON enable circuit coupled to the peak power detection circuit to receive the indication signal, and further configured to receive the compensation signal, based on the compensation signal and the indication signal, the primary ON enable circuit provides a primary ON enable signal to an input terminal of the isolation circuit, and the primary ON enable signal contains the information indicating if the peak power mode is enabled; and a primary control circuit coupled to an output terminal of the isolation circuit to receive a synchronous signal electrically isolated from the primary ON enable signal, based on the synchronous signal, the primary control circuit provides a primary control signal to control the primary switch through the gate driver; and wherein the decode circuit is coupled to the output terminal of the isolation circuit to receive the synchronous signal and is configured to decode the synchronous signal to obtain the information indicating if the peak power mode is enabled;
Regarding claim 7, this claim 7 is dependent claim of claim 6, therefore, is objected for the same reason presented above;
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838