Prosecution Insights
Last updated: October 02, 2026
Application No. 18/665,523

SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE MATRIX TILE

Non-Final OA §102§112
Filed
May 15, 2024
Examiner
SHOOK, DANIEL P
Art Unit
Tech Center
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
569 granted / 653 resolved
+27.1% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
13 currently pending
Career history
659
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
47.3%
+7.3% vs TC avg
§102
30.3%
-9.7% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 653 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In the semiconductor art many thousands of discrete devices are formed on a wafer that is diced afterwords into a plurality of dies. Each of these dies in turns may contain hundreds to thousands of components. If a wafer that could be subdivided into some number of dies was instead divided into half or less of the dies, those larger dies are, by definition, still dies as they are formed by dicing the wafer. Therefore, it is unclear what could be meant by a semiconductor die matrix comprising a second semiconductor die unsingulated from the first semiconductor die as the semiconductor die matrix is simply a die and it is nonsensical to discuss a first and second die within a single die. For examining purposes, the limitation of a die matrix shall be read as a die and the limitations with regards to the first, second, third and fourth semiconductor dies shall be ignored. Regarding claim 8 it is unclear what is being claimed as a die separation line that is not separated could be any arbitrary line running through the die and does not require a specific structure. The same logic applies to the conjoined semiconductor dies of claim 9. Furthermore, specifically in regards to claim 20, it is unclear what is being claimed by a delineation means as any structure can be taken as a point to delineate one section of the die from another such that there would appear to an arbitrary number of delineation means in any given die. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leslie at al. (US 2021/0280557 A1). Regarding claim 1, Leslie discloses a semiconductor package comprising (Fig 2): a substrate (230); and a stack of semiconductor dies (220) electrically coupled to the substrate; and a redistribution layer (Fig 6, ¶40). PNG media_image1.png 380 576 media_image1.png Greyscale PNG media_image2.png 464 802 media_image2.png Greyscale Regarding claim 2, Leslie discloses bond pads on the semiconductor die (620). Regarding claim 3, Leslie discloses redistribution layer bond pads (610) electrically coupled to one or more bond pads on the semiconductor die Regarding claim 4, Leslie discloses a plurality of solder balls (240) provided on a bottom surface of the substrate. Regarding claim 5, Leslie discloses that the redistribution layer bond pad is electrically coupled to at least one solder ball of the plurality of solder balls as the solder balls illustrated in Fig 2 are the means in which the device sends and receives signals from where it is further integrated which requires the connection of the redistribution layer bond pads to those solder balls in order for the dies to be addressable and thus function as intended. Regarding claims 6 and 7, Leslie discloses semiconductor dies (620). Regarding claim 8, one can envisage a line to further subdivide a die. Regarding claim 9,Leslie discloses a semiconductor package (Fig 2 & 6), comprising; a substrate (230); a first semiconductor die (220) and a second semiconductor die (220) stacked on top of the first semiconductor die and being a memory die (¶24 & ¶25); a first plurality of redistribution layer bond pads (620-1) provided on the first semiconductor die; a second plurality of redistribution layer bond pads (620-2) provided on the second semiconductor die and at least a first redistribution layer bond pad of the second plurality of redistribution layer bond pads on the second semiconductor die. Regarding claim 10, Leslie discloses a redistribution layer provided on a surface of the first semiconductor die matrix tile as the redistribution layer is in substrate 230 and the lowermost semiconductor die 220 is also on substrate 230 with bond pad 620(1) contacting the redistribution layer. Regarding claim 11, Leslie discloses a plurality of traces (632) provided within the redistribution layer and electrically connected to the die. Regarding claim 12, Leslie discloses that the redistribution layer bond pad is electrically coupled to one or more interconnects associated with the semiconductor package (Fig 6, any of the illustrated conductive members are interconnects associated with the semiconductor package). Regarding claim 13, one can envisage a line to further subdivide a die. Regarding claim 14, as no structure is required by the claim it does not patentably distinguish over claim 13, claim 14 essentially claiming the lack of a process step within the context of a device claim. Regarding claim 15, Leslie discloses a semiconductor package (Fig 2 & 6), comprising a substrate (230); a stack of semiconductor dies (220) a trace distribution means (Fig 6) provided on the semiconductor die (as the redistribution layer is in substrate 230 and the lowermost semiconductor die 220 is also on substrate 230, where the elements may be considered reversed, i.e. the substrate is on the die stack); a trace means (632); and a connection means (240). Regarding claim 16, Leslie discloses that the connection means are bond pads associated with the trace distribution means (Fig 6, elements 610 & 620 are bond pads). Regarding claim 17, Leslie discloses interconnection means associated with the connection means (any of traces 632 or any other element of the redistribution layer). Regarding claim 18, Leslie discloses that the interconnection means are solder balls (per Fig 2, said elements being associated with the connection means as they are all part of the same device. Regarding claim 19, Leslie discloses circuitry means (the redistribution layer of Fig 6) for electrically coupling each semiconductor die in the stack of semiconductor dies on the substrate. Regarding claim 20, one could delineate the dies into first and second areas. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL P SHOOK/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Sep 11, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+8.4%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 653 resolved cases by this examiner. Grant probability derived from career allowance rate.

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