DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to preliminary amendment filed 5/16/2024.
Claims 1-20 are presented for examination.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) or (f).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/22/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
“the processing task” at line 6 of claim 1 should be: one processing task from the set of processing tasks.
“the processing tasks of the set of processing tasks” at line 7 of claim 1 should be: one or more processing tasks of the set of processing tasks.
Claims 2-15 and 18-20 are objected for failing to cure the deficiency from their respective parent claim by dependency.
Each of Claims 16-17 is objected under the same reason set forth in the (I) and (II) above.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding to Claim 10, claim 10 recites the limitation “the computer code” at line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, examiner interprets “the computer code” as “a computer code”.
In addition, meaning of limitation “the analyses” at line 7 is not clear. There are three different “analysing” at claim 10. It is not clear that “the analyses” at line 7 is referred to which analysing (any one of the three, any two of the three OR all of the three). For the purpose of examination, examiner interprets “the analyses” as: at least one of the three analyses above.
Claims 11-14 are rejected for failing to cure the deficiency from their respective parent claim by dependency.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Regarding to Claim 16, Claim 16 recites “A computer readable storage media” “storing thereon an application program” “having instructions”. However, Applicant’s specification (particularly [0111]) only provides certain descriptions to provide certain examples of such claimed computer readable storage media. According to the descriptions, BRI of such claimed “computer readable storage media” does not exclude signals. Signals are directed to a non-statutory subject matter. Thus, Claim 16 is rejected under 35 U.S.C. 101 for directing to a non-statutory subject matter. Examiner suggests amend the claim element as “non-transitory computer readable storage media” in order to draw the claim to non-transitory subject matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-9, 15-16 and 18-20 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Nakashima (US 20080250232 A1).
Regarding to claim 1, Nakashima discloses: A computer-implemented method for performing a set of processing tasks, the set of processing tasks involving transforming a set of discrete inputs to a set of discrete outputs (see [0007], [0030] and [0098]-[0099]; “This value reuse is arranged such that, an input value and an output value regarding a part of a program are registered in a reuse table, and when the same part is executed again, the registered output value is output if the input value is identical with the input value registered in the reuse table” and “The data processing device of the present invention … a reuse process is performed so that an output pattern, which is stored in the input/output storage means in association with the input pattern, is outputted to the register and/or the main memory means”. Also see [0034]-[0035]; “data (00110000) are registered, as inputs, in the first column on the Input-side of the RB … data (00000002) are registered, as outputs, in the Output-side first column of the RB”, “data (02) are, as inputs, registered in the Input-side second column of the RB … data (00000002) are, as outputs, registered in the Output-side second column of the RB”), the method comprising:
identifying a unique input value from the set of discrete inputs among the set of processing tasks; performing the processing task with the unique input value to generate a discrete output; and (see [0007], [0043], [0103], [0213]; “This value reuse is arranged such that, an input value and an output value regarding a part of a program are registered in a reuse table” and “If the registered address/register number thus registered is not found in the Input side of the RB, a new entry is added to the RB, and the address/register number and the value of the entry are registered”, “in a case where an input element is newly stored in the input/output storage means”, “Each entry must be registered as a new entry, if at least one of the items of the entry does not match”. A new unique input value is found at [0043] or [0103] or [0213] to register such new unique input value);
assigning the discrete output to the processing tasks of the set of processing tasks having the same discrete input as the unique input value (see [0007], [0075] and [0574]; “when the same part is executed again, the registered output value is output if the input value is identical with the input value registered in the reuse table” and “The aforesaid data processing device of the present invention may be arranged such that … if the same instruction region appears and an input identical with the predicted input value is done, it is possible to reuse a value stored in the instruction region storage means” and “in a case where the MSP 1A executes the instruction region and an input value identical with a predicted input element stored in the RB as a predicted entry is inputted, a corresponding predicted output element is outputted. In this manner, reuse is realized”).
Regarding to Claim 2, the rejection of Claim 1 is incorporated and further Nakashima discloses: wherein each discrete input comprises a plurality of input attributes, wherein the unique input value is a particular group of input attribute values across the plurality of input attributes (see [0060]-[0061], [0303]-[0304]; “generating an input/output group which is made up of an input pattern and an output pattern at the time of execution of the instruction region by the first computing means; and instruction region storage means for storing the input/output group generated by the input/output generating means, at the time of execution of the instruction region, if the input pattern of the instruction region is matched with an input pattern stored in the instruction region storage means, the first computing means performing reuse so that the output pattern”, “input patterns belonging to different groups can be individually registered”).
Regarding to Claim 4, the rejection of Claim 2 is incorporated and further Nakashima discloses: prior to identifying the unique input value from the set of discrete inputs: generating at least one of the plurality of input attributes (see [0060]-[0061], [0303]-[0304]; “generating an input/output group which is made up of an input pattern and an output pattern at the time of execution of the instruction region by the first computing means; and instruction region storage means for storing the input/output group generated by the input/output generating means, at the time of execution of the instruction region”, “input patterns belonging to different groups can be individually registered”).
Regarding to Claim 6, the rejection of Claim 1 is incorporated and further Nakashima discloses: wherein identifying a unique input value from the set of discrete inputs among the set of processing tasks comprises: identifying a plurality of unique input values from the set of discrete inputs among the set of processing tasks (see [0034]-[0035]; “data (00110000) are registered, as inputs, in the first column on the Input-side of the RB”, “data (02) are, as inputs, registered in the Input-side second column of the RB”. Also see [0007], [0043], [0103], [0213]; “If the registered address/register number thus registered is not found in the Input side of the RB, a new entry is added to the RB, and the address/register number and the value of the entry are registered”, “in a case where an input element is newly stored in the input/output storage means”, “Each entry must be registered as a new entry, if at least one of the items of the entry does not match”. At least two different unique input values are identified).
Regarding to Claim 7, the rejection of Claim 6 is incorporated and further Nakashima discloses: wherein performing the processing task with the unique input value to generate a discrete output is performed for each of the plurality of unique input values (see [0034]-[0035]; “data (00110000) are registered, as inputs, in the first column on the Input-side of the RB … data (00000002) are registered, as outputs, in the Output-side first column of the RB”, “data (02) are, as inputs, registered in the Input-side second column of the RB … data (00000002) are, as outputs, registered in the Output-side second column of the RB”).
Regarding to Claim 8, the rejection of Claim 1 is incorporated and further Nakashima discloses: wherein the set of discrete inputs is stored in an input dataset, each discrete input value of the set of discrete inputs forming a different row or column of the input dataset, and wherein the set of discrete outputs is stored in an output dataset, each discrete output of the set of discrete outputs forming a different row or column of the output dataset (see [0034]-[0035]; “data (00110000) are registered, as inputs, in the first column on the Input-side of the RB … data (00000002) are registered, as outputs, in the Output-side first column of the RB”, “data (02) are, as inputs, registered in the Input-side second column of the RB … data (00000002) are, as outputs, registered in the Output-side second column of the RB”).
Regarding to Claim 9, the rejection of Claim 8 is incorporated and further Nakashima discloses: wherein assigning the discrete output to the processing tasks of the set of processing tasks having the same discrete input as the unique input value comprises: selecting any rows or columns of the input dataset having the same discrete input as the unique input value, and setting the corresponding rows or columns in the output dataset to the discrete output (see [0007]; “This value reuse is arranged such that, an input value and an output value regarding a part of a program are registered in a reuse table, and when the same part is executed again, the registered output value is output if the input value is identical with the input value registered in the reuse table”).
Regarding to Claim 15, the rejection of Claim 1 is incorporated and further Nakashima discloses: wherein the method is for reducing processor cycles (see [0007]; “The value reuse is advantageous in the following points: (1) if the input value is identical with the input value registered in the reuse table, it is unnecessary to verify the execution result; (2) since hardware costs are determined only in accordance with the total number of input and output values, the lengths of omissible sequences of instructions are not limited; (3) the number of dependency relations among instructions is unrelated to the complexity of the reuse mechanism; and (4) redundant load/store instructions are eliminated, and power consumption is reduced accordingly”).
Regarding to Claim 16, Claim 16 is a product claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: Also see claim 31 from reference Nakashima; “A computer-readable storage medium, storing the data processing program defined in claim 30”).
Regarding to Claim 18, the rejection of Claim 1 is incorporated and further Nakashima discloses: wherein the set of processing tasks are performed as a batch (see [0007], [0075] and [0574]; “when the same part is executed again, the registered output value is output if the input value is identical with the input value registered in the reuse table” and “The aforesaid data processing device of the present invention may be arranged such that … if the same instruction region appears and an input identical with the predicted input value is done, it is possible to reuse a value stored in the instruction region storage means”. The tasks related to same input values are performed as a batch).
Regarding to Claim 19, the rejection of Claim 8 is incorporated and further Nakashima discloses: wherein the input dataset and/or the output dataset is embodied in a relational database (see [0034]-[0035]; “data (00110000) are registered, as inputs, in the first column on the Input-side of the RB … data (00000002) are registered, as outputs, in the Output-side first column of the RB”, “data (02) are, as inputs, registered in the Input-side second column of the RB … data (00000002) are, as outputs, registered in the Output-side second column of the RB”).
Regarding to Claim 20, the rejection of Claim 19 is incorporated and further Nakashima discloses: wherein the relational database uses composite indexes (See [0380]; “the column locations of the input side number storage section rgpid and the output side number storage section wgpid”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakashima (US 20080250232 A1) in view of de Zambotti et al. (US 20240016456 A1, hereafter Zambotti).
Regarding to Claim 3, the rejection of Claim 2 is incorporated and further Nakashima discloses: wherein the particular group of input attribute values comprises an input attribute value for a reduced group of input attributes of the plurality of input attributes (see [0060]-[0061], [0303]-[0304]; “generating an input/output group which is made up of an input pattern and an output pattern at the time of execution of the instruction region by the first computing means; and instruction region storage means for storing the input/output group generated by the input/output generating means, at the time of execution of the instruction region, if the input pattern of the instruction region is matched with an input pattern stored in the instruction region storage means, the first computing means performing reuse so that the output pattern”, “input patterns belonging to different groups can be individually registered”. Note: identifying input patterns/attributes is used to reduce groups of different unique input values, and thus the input patterns or attributes for a particular unique input value can be an input attribute value for a reduced group of input attributes).
Nakashima does not disclose: wherein the reduced group of input attributes is identified using principal component analysis.
However, Zambotti discloses: wherein the reduced group of input attributes is identified using principal component analysis (see [0120]; “facilitates the understanding of the input pattern … Since the dimension of the input patterns can be very high, statistical methods such as principal component analysis or linear component analysis can be used to transform the features into a lower dimension subspace where a more precise and efficient representation of the input patterns is achieved”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the process of identifying input patterns from Nakashima by including the process of identifying input patterns via principal components analysis from Zambotti, and thus the combination of Nakashima and Zambotti would disclose the missing limitations from Nakashima, since it would provide a mechanism to identifying more precise and efficient representation of input patterns (see [0120] from Zambotti; “Since the dimension of the input patterns can be very high, statistical methods such as principal component analysis or linear component analysis can be used to transform the features into a lower dimension subspace where a more precise and efficient representation of the input patterns is achieved”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakashima (US 20080250232 A1) in view of Miyata et al. (JP2020190875A-English translation provided by Google Patents, publication date: 11/26/2020, hereafter Miyata).
Regarding to Claim 5, the rejection of Claim 4 is incorporated, Nakashima does not disclose: wherein generating at least one of the plurality of input attributes comprises transforming a continuous input attribute to a discrete input attribute.
However, Miyata discloses: wherein generating at least one of the plurality of input attributes comprises transforming a continuous input attribute to a discrete input attribute (see [0006]; “the present invention is a device that … An uncontrollable condition value indicating the time-series data of the system is input and discreteized, and the discrete uncontrollable condition value is divided into a plurality of groups according to the value and managed, and each of the plurality of groups” and “In this embodiment, the time-varying business index approximate values of the first business and the second business are input by inputting the approximate values that are discretized by the rounding rule of the uncontrollable condition values that change with time in each of the first business and the second business”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the process of identifying input patterns/attributes of discrete data/values from Nakashima by including converting continuous input values to discreate input values from Miyata, and thus the combination of Nakashima and Miyata would disclose the missing limitations from Nakashima, since it would provide it would reduce workload or calculation time via discreate input values after converting continuous input values to the discreate input values (see [0004]-[0006] from Miyata; “since each of the plurality of different demand forecast curves changes with time as a continuous value, the calculation time increases as the number of combinations increases when the combination with a plurality of power generation plans is evaluated for each time. Therefore, there is a problem that cannot be applied to the work in which the calculation time is limited … In order to solve the above problems, the present invention … An uncontrollable condition value indicating the time-series data of the system is input and discreteized”).
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nakashima (US 20080250232 A1) in view of Husbands (US 20110314459 A1) and Chang (US 5768592 A).
Regarding to Claim 10, the rejection of Claim 1 is incorporated and further Nakashima discloses: prior to identifying a unique input value: outputting restructured computer code based on the analyses (see [0007]; “This value reuse is arranged such that, an input value and an output value regarding a part of a program are registered in a reuse table”. Before registering the input value and output value regarding a part of a program in the reuse table, i.e., claimed prior to identifying a unique input value, it is understood that a compiled version of program code, i.e., claimed restructured computer code is required to be outputted by performance of compiler).
Nakashima does not disclose: the analyses comprise:
analysing the set of discrete inputs and the set of discrete outputs of the set of processing tasks;
analysing the computer code that is configured to execute the set of processing tasks;
executing the computer code to perform the set of processing tasks and analysing the execution of the computer code.
However, Husbands discloses: analysing the set of [discrete] inputs and the set of [discrete] outputs of the set of processing tasks; analysing the computer code that is configured to execute the set of processing tasks; and outputting restructured computer code based on the analyses (see [0007]-[0010], [0021]-[0022] and [0024]; “a compiler that accepts assertions in the form of a user-defined mapping between one or more input types and one or more output types associated with an operation involving one or more user-defined elements”, “the compiler or other program that analyzes source code to identify type relationships” and “compiler 10 may access a source program 20, process source program 20 and generate code for execution 40”. Also see [0040]; “in addition to the information shown in instruction 24, information about the defined method, such as the number of input parameters, the number of output parameters and other characteristics. This information may be stored by compiler 10 and then used in processing portions of source program 20 using methods of the defined type”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the generation of compiled program to be executed from Nakashima by including a compiler accesses and processes a source program and then generates code for execution from Husbands, since it is well-known and understood to utilize a compiler “convert a program in source code form into a form in which it can be executed by a computer” (see [0001] from Husbands).
In addition, Chang discloses: executing the computer code to perform the set of processing tasks and analysing the execution of the computer code and outputting restructured computer code based on the analyses (see lines 49-16 of cols. 4-5; “to collect profile data of the code being compiled. The object code is then executed in box 240 by the processor 102 with representative input data supplied from box 220 …. the profile data gathered from execution of the instrumented object code is fed back to the compiler at box 210 and the source code is recompiled in a second pass with the profile information to generate an optimized object code”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the compilation of a source computer program code configured to perform tasks from the combination of Nakashima and Husbands by including compiling a source computer program code based on execution of the source computer program code to generate optimized object code from Chang, and thus the combination of Nakashima, Husbands and Chang would disclose the missing limitations from Nakashima, since it would provide a mechanism of generating optimized computer code which “runs faster and occupies less space” (see lines 6-16 of col. 5 from Chang).
Regarding to Claim 11, the rejection of Claim 10 is incorporated and further the combination of Nakashima, Husbands and Chang discloses: wherein the restructured computer code comprises: a synthetic groups creation layer determined by analysing the set of discrete inputs and the set of discrete outputs of the set of processing tasks, analysing the computer code that is configured to execute the set of processing tasks, and executing the computer code to perform the set of processing tasks and analysing the execution of the computer code; a core functionality layer determined by analysing the computer code that is configured to execute the set of processing tasks; and a post-processing layer determined by analysing the set of discrete inputs and the set of discrete outputs of the set of processing tasks, analysing the computer code that is configured to execute the set of processing tasks, and executing the computer code to perform the set of processing tasks and analysing the execution of the computer code (see Fig. 36(a), [0007], [0625]-[0631] from Kakashima, [0024] from Husbands and lines 58-5 of cols. 4-5 from Chang; “an input value and an output value regarding a part of a program”, “generate code for execution 40 … the sections of the program that are to be executed are identified based on runtime conditions”. Fig. 36(a) from Kakashima represents a particular example to show the compiled program code, i.e., claimed restructured computer code, at least comprises: 1. a synthetic groups creation layer like “ld (A1=R1) -> Rx” at line 2 and “ld (A2=R2) -> Ry” at line 4 to form basic input group, 2. Core functionality layer like “ld (A3=Rx-4) -> Rz add Rx+4 -> Rx” at lines 5-6 and “add Ry+Rz -> Rz” at line 10 to perform the main/core operations, 3. post-processing layer like “st Rz -> (A4=Rx) br loop” to perform the output loading/storing and return to beginning of execution. And these layers are determined by the compilation processes, i.e., claimed “analysing the set of discrete inputs and the set of discrete outputs of the set of processing tasks, analysing the computer code that is configured to execute the set of processing tasks, and executing the computer code to perform the set of processing tasks and analysing the execution of the computer code” at the combination system after combing the features from Husbands).
Note1: for claimed “a synthetic groups creation layer”, the current claim 11 only requires such claimed synthetic groups creation layer is determined by certain analysis without further clearly defining or requiring what kind of layer to be considered as such claimed synthetic groups creation, and thus any reasonable section/part/layer of a compiled program can be considered as current claimed “a synthetic groups creation layer” under BRI.
Note2: for claimed “a core functionality layer”, current claim 11 only requires such layer is determined by “analysing the computer code that is configured to execute the set of processing tasks” without excluding such layer can also be determined by “analysing the set of discrete inputs and the set of discrete outputs of the set of processing tasks”.
Regarding to Claim 12, the rejection of Claim 11 is incorporated and further the combination of Nakashima, Husbands and Chang discloses: a pre-processing layer determined by analysing the computer code that is configured to execute the set of processing tasks (see Fig. 36(a), [0007], [0625]-[0631] from Kakashima, [0024] from Husbands and lines 58-5 of cols. 4-5 from Chang; “an input value and an output value regarding a part of a program”, “generate code for execution 40 … the sections of the program that are to be executed are identified based on runtime conditions”. Similar as explained at the rejection of claim 11, Fig. 36(a) from Kakashima represents a particular example to show the compiled program code, i.e., claimed restructured computer code, at least comprises: pre-processing layer like “set A1 ->R1” at line 1 and “set A2 -> R2” at line 3 to declare inputs).
Regarding to Claim 13, the rejection of Claim 11 is incorporated and further the combination of Nakashima, Husbands and Chang discloses: wherein the restructured computer code further comprises: an observability layer determined by executing the computer code to perform the set of processing tasks and analysing the execution of the computer code (see Fig. 36(a), [0007], [0625]-[0631] from Kakashima, [0024] from Husbands and lines 58-5 of cols. 4-5 from Chang; “an input value and an output value regarding a part of a program”, “generate code for execution 40 … the sections of the program that are to be executed are identified based on runtime conditions” and “the source code is recompiled in a second pass with the profile information to generate an optimized object code”. Similar as explained at the rejection of claim 11, Fig. 36(a) from Kakashima represents a particular example to show the compiled program code, i.e., claimed restructured computer code, at least comprises: observability layer like “st Rx -> (A1=R1) shift Ry -> Ry st Ry –>(A2=R2)” at lines 7-9 to observe certain intermediate results/output).
Regarding to Claim 14, the rejection of Claim 10 is incorporated and further the combination of Nakashima, Husbands and Chang discloses: wherein the restructured computer code is used for processing the set of processing tasks (see [0007] from Kakashima, [0024] from Husbands and lines 58-5 of cols. 4-5 from Chang; “an input value and an output value regarding a part of a program”, “generate code for execution 40 … the sections of the program that are to be executed are identified based on runtime conditions” and “the source code is recompiled in a second pass with the profile information to generate an optimized object code”).
Claims 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakashima (US 20080250232 A1) in view of Gershgorn et al. (US 20220342696 A1).
Regarding to Claim 17, Nakashima discloses: A [cloud] computing environment having a processor configured to perform the method of claim 1 (see [0007], [0030] and [0098]-[0099]; “This value reuse is arranged such that, an input value and an output value regarding a part of a program are registered in a reuse table, and when the same part is executed again, the registered output value is output if the input value is identical with the input value registered in the reuse table” and “The data processing device of the present invention … first computing means for performing a computation based on the instruction region read out from the main memory means … a reuse process is performed so that an output pattern, which is stored in the input/output storage means in association with the input pattern, is outputted to the register and/or the main memory means”).
Nakashima does not disclose the computing environment is a cloud computing environment.
However, Gershgorn discloses: A cloud computing environment having a processor configured to perform the method of performing the processing task with the unique input value to generate a output; and assigning the output to the processing tasks of the set of processing tasks having the same input as the unique input value (see Figs. 1, 2, [0015], [0034]-[0036], [0067]; “For deterministic computing tasks (i.e., computing tasks that produce the same outputs given the same inputs) these conditions guarantee that the stored outputs of the previous computing task can be reused safely as outputs of the new computing task” and “the system configuration seen in FIG. 1 is one non-limiting example implementation. In alternative embodiments the disclosed techniques can be used in various other system configurations, e.g. …. cloud-based systems, or any other suitable configuration. The description that follows refers to a centralized, single-processor system, purely for the sake of clarity. In various embodiments, processor 24 may be configured to execute various types of computing tasks (referred to herein simply as “tasks” for brevity)”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the generic computing environment performs reuse value mechanism from Nakashima by including the cloud computing environment performs reuse value mechanism from Gershgorn, and thus the combination of Nakashima and Gershgorn would disclose the missing limitations from Nakashima, since a cloud computing environment is a well-known and understood mechanism to use scalable and elastic pool of shared resources nowadays.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cardoza et al. (US 5630049 A) discloses: a set of processing tasks can be performed as a batch and output of at least one of the set of processing tasks can be reused for another one of the set of processing task having identical input (see lines 51-16 of cols. 27-28; “The network cache may be used to store the results of an RPC call in which, given an input, the RPC always returns the same results. For subsequent calls to the same RPC with identical input, RPC results stored in the network cache may be reused” and “A plurality of write operations requested, respectively, through a plurality of NDP messages, for example, may be batched into a single NDP message”).
Yang (US 10853363 B2) discloses: the relational database uses the one or more rowkey fields, the one or more column family fields, and the one or more time fields as a composite primary index key (see claim 4).
Deng et al. (US 20240362225 A1) discloses: In order to further optimize the performance of a relational database management system (MySQL) executor, a composite index may be created for a data table (see [0003]).
Popa et al. (US 6567802 B1) discloses: using select distinct function to identify unique value from a set of values (see lines 9-15 of col. 9) and common subproblems are solved only once and the results reused (see lines 2-5 of col. 28).
Djordjevic et al. (US 20170206242 A1) discloses: the system identifies queries that are structurally different but semantically the same and re-uses cached results (see [0083]).
Villarroel Humérez (US 20230019006 A1) discloses: executing the computer code and analyszing the execution of the computer code and outputting restructured computer code based on the analyses (see [0011]).
Todirel et al. (US 20240296107 A1) discloses: just-in-time compiler, also refers to just-in-time (JIT) compilation; compilation of part of a program which is performed during program execution after a previously compiled different part of the program has begun executing (see [0302]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR to authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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