Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Objections
Claims 7, 11-17 and 19-20 are objected to because of the following informalities:
As to claim 7, “the system limits” should read --system limits-- (Note: claim 7 depends on claim 5 and not claim 6 where “system limits” was first recited).
As to claims 11-13, “The method of claim 9” should read --The method of claim 10--.
As to claim 14, “The method of claim 12” should read --The method of claim 13-- since claim 14 appears to be further limit the runtime limits of claim 13.
As to claims 15-16, this claim is rejected for the same reason as claims 7 and 14 above.
As to claim 17, “The method of claim 15” should read --The method of claim 16-- since claim 17 appears to be further limit the decreasing of runtime metrics of claim 16.
As to claims 19-20, “The SOC of claim 17” should read --The SOC of claim 18--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9-14 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over translation of CN116931707 to Fan et al. (hereafter Fan) in view of WO2024/145091 to Kao et al. (hereafter Kao). (Note: translation of CN116931707 do not have associated pages or paragraphs explicitly labeled, therefore the examiner will refer to the page(s) and paragraph(s) within the document to assist applicant to best locate the mappings)
Fan was cited in applicant’s IDS filed on 12/15/25.
As to claim 1, Fan teaches the invention substantially as claimed including a system on a chip (SOC) comprising:
a processor [system-on-chip comprising at least one chip, p. 2, paragraph 3]; and
memory comprising computer executable instructions that, when executed, perform operations [computer readable medium having stored thereon a computer program when executed by a processor in performing the various embodiments, p. 7, paragraphs 3-5] comprising:
recording, during a runtime of a workload, runtime metrics for the workload using sensors associated with logical partitions of the SOC, wherein the sensors calculate the usage of each of the logical partitions [collects monitoring data of each partition/sub-areas, p. 2, paragraphs 3-4; detecting working state such as detecting temperature and voltage and use/record/transmit temperature sampling data and voltage sampling data of the partition/sub-area to a dynamic adjusting unit, p. 8, paragraph 8-p. 9, paragraph 1; monitoring data collected by the partition sensors of each partition/sub-area of the chip, p. 11, line 4] (Note: working state reflects the current state of partition(s) of a chip and the data collected with respect to the change in temperature and voltage pertains to the use of the chip);
determining, by a runtime profiler of the SOC, performance characteristics of the logical partitions based on the runtime metrics [taking into consideration the computing performance of each partition, management chip sets the frequency of the partition to the frequency protection value, or adjusts the power supply chip to set the voltage of the partition to the voltage protection value through a preset voltage value, thereby protecting each partition of each single chip of the system-on-chip and ensuring hardware operation. The unit is in a safe working environment, effectively improving the service life of the system- on-chip, p. 5, paragraph 10-p. 6, paragraph 1; computing performance of each partition, p. 11, paragraphs 10-11; p. 12, paragraph 1] ;
determining for at least one partition processor associated with a partition of the logical partitions a respective optimal clock frequency to run the workload based on the performance characteristics [determine the preset clock frequency trend as the to-be- adjusted value of the partition, p. 6, paragraph 9; the configured frequency adjusting strategy can determine the adjusted clock frequency, output the adjusted clock frequency to the partition corresponding to the second instruction, and dynamically adjust the power management unit according to the monitoring data of the partition sensor of each partition, thereby achieving dynamic adjustment of the clock frequency of each partition, p. 10, paragraph 6]; and
adjusting, during the runtime of the workload, the at least one partition processor associated with the partition of the logical partitions to run the partition of the logical partitions at the respective optimal clock frequency for the workload [dynamically adjust the power management unit according to the monitoring data of the partition sensors in each partition, thereby achieving dynamic adjustment of the clock frequency of each partition, p. 2, last paragraph; p. 3, lines 1-4; improving the adjustment accuracy of the voltage frequency of each partition of each single chip of the system-on-chip, p. 6, paragraph 7; The dynamic adjustment unit is also configured to adjust the clock frequency output by the power management unit according to the monitoring data of each partition sensor [p. 9, last paragraph; p. 10, lines 1-2].
Fan does not specifically explicitly teach the use of counters. However, Fan disclosed partition sensor of respective partition of a plurality of partitions [p. 2, paragraph 3] acquiring monitoring data pertaining to temperature and voltage that directly or indirectly correlates to the usage of a partition in determining whether a preset monitoring threshold requirement is met [p. 2, paragraph 7-p. 3, paragraph 4]. Furthermore, Kao teaches the use of sensor as well as performance counters in an SoC in tracking various performance metrics [paragraphs 22-23].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combine Fan with Kao because they are both in the same field of endeavor in adjusting operating clock frequency of an processing unit to accommodate workload changes [determine the preset clock frequency trend as the to-be- adjusted value of the partition, p. 6, paragraph 9; the configured frequency adjusting strategy can determine the adjusted clock frequency, output the adjusted clock frequency to the partition corresponding to the second instruction, and dynamically adjust the power management unit according to the monitoring data of the partition sensor of each partition, thereby achieving dynamic adjustment of the clock frequency of each partition, p. 10, paragraph 6; Kao, paragraphs 24-26].
As to claim 2, Fan and Kao teaches the invention substantially as claimed including wherein counters are used to count usage amount of a partition of the logical partitions [partition sensor of respective partition of a plurality of partitions, p. 2, paragraph 3; acquiring monitoring data pertaining to temperature and voltage that directly or indirectly correlates to the usage of a partition in determining whether a preset monitoring threshold requirement is met, p. 2, paragraph 7-p. 3, paragraph 4; Kao, sensor as well as performance counters in an SoC in tracking various performance metrics, paragraphs 22-23].
As to claim 3, Fan teaches the invention substantially as claimed including wherein each partition processor associated with each of the logical partitions is running at a base clock frequency of the processor [clock frequency of the chip prior to frequency adjustment, p. 2, last paragraph-p. 3, line 1].
As to claims 4-5, Fan teaches the invention substantially as claimed including wherein the runtime metrics are dependent on power requirements of the SOC measured as runtime limits; wherein the runtime metrics are directly proportional to the power requirements [acquiring monitoring data pertaining to temperature and voltage as a result of usage of a partition in determining whether a preset monitoring threshold requirement is met, p. 2, paragraph 5-p. 3, paragraph 4].
As to claim 9, Fan teaches the invention substantially as claimed including wherein the performance characteristics define the usage behavior of the logical partitions executing the workload [real-time load demand reflects usage behavior of a chip and partitions/sub-area as well as monitoring data collected, p. 9, paragraph 3; taking into consideration the computing performance of each partition, management chip sets the frequency of the partition to the frequency protection value, or adjusts the power supply chip to set the voltage of the partition to the voltage protection value through a preset voltage value, thereby protecting each partition of each single chip of the system-on-chip and ensuring hardware operation. The unit is in a safe working environment, effectively improving the service life of the system- on-chip, p. 5, paragraph 10-p. 6, paragraph 1; computing performance of each partition, p. 11, paragraphs 10-11; p. 12, paragraph 1].
As to claims 10-14, these claims are rejected for the same reason as claims 1-5 above.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over to Fan and Kao as applied to claims 1-5 and 10-14 above, further in view of US PG Pub. 2024/0094796 to Narayanaswamy et al. (hereafter Narayanaswamy).
As to claim 18, this claim is rejected for the same reason as claim 1 above. Fan and Kao do not specifically teach the use of a model for determining future usage of a partition and adjustment of clock frequency of an associated partition processor based on the future usage. However, Narayanaswamy teaches the use of a model to correlate clock frequency with power consumption of a processor within a group or cluster of processors and outputting an optimum clock frequency for the processor [paragraph 72]; controller 102 calculates a target clock frequency based, at least in part on a workload factor correlated with an application being performed by processors 104a-n, and as a result, causes a processor with clock frequency 1335 MHz to increase its clock frequency to 1340 MHz, causes a processor with clock frequency 1340 MHZ to remain at 1340 MHz, and causes a processor with clock frequency 1344 MHz to decrease to 1340 MHz. In at least one embodiment, controller 102 uses a table that correlates a clock frequency of 1340 MHz with a power consumption of 200 W and predicts that if a processor runs at a clock frequency of 1340 MHz, that 200 W of power will be consumed. In at least one embodiment, controller 102 sums all predicted power consumptions values for each of processors 104a-n and calculates whether that total power consumption value fits within a power budget. In at least one embodiment, clock speed models 106a-n each set a target clock frequency for processors 104a-n and controller 102 calculates whether those target clock frequencies will allow those processors to run within a power budget and increase execution speed of an application. In at least one embodiment, a controller 102 will set a decreased target frequency for one or more processors 104a-n if, at least in part, those processors are running at a clock frequency that is unnecessarily fast such as when processors are running at a speed in excess of what is necessary to improve application execution and is no longer providing an improvement to application processing speed [paragraph 74].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combine Fan, Kao and Narayanaswamy because they are in the same field of endeavor in adjusting operating clock frequency of an processing unit to accommodate workload changes [determine the preset clock frequency trend as the to-be- adjusted value of the partition, p. 6, paragraph 9; the configured frequency adjusting strategy can determine the adjusted clock frequency, output the adjusted clock frequency to the partition corresponding to the second instruction, and dynamically adjust the power management unit according to the monitoring data of the partition sensor of each partition, thereby achieving dynamic adjustment of the clock frequency of each partition, p. 10, paragraph 6; Kao, paragraphs 24-26; Narayanaswamy, Figs. 4-5 and corresponding text].
As to claims 19-20, these claims are rejected for the same reason as claims 2-3 above.
Allowable Subject Matter
Claims 6-8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
US PG. Pub. 2024/0094796 discloses that one portion of controller 102 increases and/or decreases a clock frequency [paragraph 58], one or more controllers implemented on and/or external to processors 104a-n calculate whether target clock speeds will cause those processors to remain within and/or exceed a power consumption budget for those processors [paragraphs 71-72], a lowest target frequency among target frequencies output by one or more of models 106a-n is set by an application as a maximum clock frequency that one or more processors cannot exceed; a controller sets one or more processors with a maximum clock frequency based, at least in part, on a lowest target clock frequency output by one or more of models 106a- n [paragraph 73]. Fan disclosed adjusting frequency based on monitored data, inclusive of voltage/power usage/requirement being over threshold of each partition sensor and adjusting the voltage/power and frequency upward or downward accordingly [p. 11 last paragraph-p. 13, paragraph 1]. “Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks with Runtime Distribution” disclosed applying power/clock gating when the operating temperature of a chip reaches a thermal threshold including turning off the processor [whole document].
The prior arts of record when taken individually or in combination do not expressly teach or render obvious the invention as a whole as recited in in claims 6-8 and 15-17.
Neither a reference uncovered that would have provided a basis of evidence for asserting a motivation, nor one of ordinary skilled in the art before the effective filing date of the claimed invention, knowing the teaching of the prior arts of record would have combined them to arrive at the present invention as recited in claims 6-8 and 15-17 as a whole.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QING YUAN WU whose telephone number is (571)272-3776. The examiner can normally be reached M-F 9AM-6PM EST.
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/QING YUAN WU/Primary Examiner, Art Unit 2199
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