Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed December 18, 2025 have been fully considered but they are not persuasive.
In pages 2-4, Applicant argues the differences of the claims of the Application and the cited prior art, in particular the reference of Faruque (US 20240338491) using RTL (register-transfer level) or gate-level netlists, which is the highest level abstraction. It is in contrast with the Applicant utilizing a primitive netlist, such as SPICE, which is a low-level abstraction representation. Furthermore, the Applicant states that the Application’s claims state physical connections between primitives, such as physical devices (transistors, capacitors, resistors, etc.), with Faruque’s signals are inputs/outputs of a functional block, and are logical, in contrast to physical connections. In particular, claims 1 and 14 have the limitation of looking at primitive-level netlists with physical properties of primitive devices and nets as “parsing the data file to identify primitives and connections of the primitives”, and Applicant states that the independent claims should be allowed.
Examiner disagrees with the Applicant regarding the rejections of the independent claims 1 and 14 being in an allowable state, as Faruque also allows for gate-level netlist files to be analyzed, to which the gates can have physical connections that corresponds to primitives of a circuit, which can be seen in Fig. 5, which uses HW2VEC to generate a graph generation tool and a graph learning model to analyze the circuit for security threats, and is described in paragraph [0074]. Although the signals are functional in contrast to physical connections, the usage of gate-level netlists or physical layouts (GDSII), both of which contains gates in the circuits, and gates can correspond to a primitive in a circuit, to identify circuits for IP piracy in HW2VEC corresponds to ‘parsing [a] data file to identify primitives and connections to the primitives’ limitation of the independent claims 1 and 14. As a result, Examiner maintains the rejection of the independent claims 1 and 14 under 35 U.S.C. 102. The dependent claims’ rejections are also maintained as a result of independent claims’ rejections being maintained from the previous Office Action.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
The independent claims recite “receiving a data file identifying components and connections for a functional component of an integrated circuit”, “parsing the data file to identify primitives and connections of the primitives”, “generating a first graph in which nodes of the first graph correspond to the primitives and edges of the first graph correspond to the connections of the primitives”, “determining matching portions of the first graph, wherein each matching portion of the determined matching portions matches any of a plurality of subgraphs of a subgraph library of known secure functionality”, “identifying that each of the determined matching portions is secure”, and “based on at least identifying that each of the determined matching portions is secure, generating an alert that the data file is secure”, in which the processes of “generating a first graph […]” and “determining matching portions of the first graph […]” are processes that generates a graph with nodes and edges based on components and connections, and the matching of portions of the graphs based on the connections of the components corresponds to “organizing information and manipulating information through mathematical correlations”, Digitech Image Techs., LLC v. Electronics for Imaging, Inc., 758 F.3d 1344, 1350, 111 USPQ2d 1717, 1721 (Fed. Cir. 2014), as described in MPEP 2106.04(a)(2), subsection I, paragraph (A), “Mathematical Relationships”. This judicial exception is not integrated into a practical application because the recited elements of independent claims 1, and 14 implement the abstract idea on a computer for integrated circuit (“IC”) design and verification, and limiting an abstract idea to a particular technological environment, without more, does not integrate it into a practical application, as stated in Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983; MPEP §2106.05(f), “Mere Instructions To Apply An Exception”, the claims recite no particular machine with meaningful constraints. The claimed limitations do not recite a specific algorithmic improvement, and the invention is results-oriented without technical details on how to implement the invention.
In addition, the limitations of “parsing the data file […]”, “identifying that each of the determined matching portions is secure”, and “[…] generating an alert that the data file is secure” are processes that can be performed in the mind, and therefore, are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, “Mental Processes”. This judicial exception is not integrated into a practical application because the recited elements of independent claims 1, and 14 implement the abstract idea on a computer for IC design and verification, Alice, MPEP §2106.05(f), and the claims do not amount to an improvement to technology/computer functionality, and the limitation of “generating an alert that the data file is secure” is a non-technical, post-solution activity rather than a practical application that improves the IC itself or improving tools for electronic designs. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the addition of “receiving a data file identifying components and connections for a functional component of an integrated circuit” of independent claims 1, and 14 merely amounts to data gathering, as stated in MPEP 2106.05(g), “Insignificant Extra-Solution Activity”.
Dependent claims 2-13, and 15-20 that rely upon independent claims 1, and 14 are rejected for relying upon their respective independent claims. Dependent claims 2-13 depend on independent claim 1, and claims 15-20 depends on claim 14. As independent claims 1, and 14 are rejected under 35 U.S.C. 101, the dependent claims listed are also rejected as well.
Regarding claim 2, the recitation of “based on at least identifying that all portions of the first graph are secure, building the integrated circuit using the data file” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 3, the recitation of “determining whether any portion of the first graph is unmatched, where an unmatched portion comprises a portion of the first graph that does not have a match to any subgraph of the subgraph library”, “and for each unmatched portion: performing a security assessment of the unmatched portion”, “and either: based on at least the security assessment determining that the unmatched portion is secure, identifying the unmatched portion as secure”, and “or based on at least the security assessment not determining that the unmatched portion is secure, generating an alert that the data file is not secure” are mental processes that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 4, the recitation of “based on at least determining that the unmatched portion is secure, adding the unmatched portion to the subgraph library” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 5, the recitation of “wherein performing the security assessment comprises: extracting a schematic of the unmatched portion” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 6, the recitation of “wherein performing the security assessment comprises: performing a Boolean analysis of the unmatched portion” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 7, the recitation of “wherein performing the security assessment comprises: extracting a schematic of the unmatched portion” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 8, the recitation of “based on at least the security assessment not determining that the unmatched portion is secure, persisting an indication of the data file as not secure” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 9, the recitation of “based on at least identifying that all portions of the first graph are secure, persisting an indication of the data file as secure” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Regarding claim 11, the recitation of “wherein the primitives comprise circuit elements selected from the list consisting of: transistors, diodes, resistors, capacitors, and inductors” is a mental process that can be performed in the mind, and therefore, the elements are grouped under mental processes, as described in MPEP 2106.04(a)(2), subsection III, "Mental Processes".
Independent claim 14 recites similar limitations to claim 1 above, and as a result, is rejected for similar issues in claim 1 above.
Claim 15 recites similar limitations to claim 3 above, and as a result, is rejected for similar issues in claim 3 above.
Claim 16 recites similar limitations to claim 4 above, and as a result, is rejected for similar issues in claim 4 above.
Claim 17 recites similar limitations to claims 5 and 7 above, and as a result, is rejected for similar issues in claims 5 and 7 above.
Claim 18 recites similar limitations to claim 8 above, and as a result, is rejected for similar issues in claim 8 above.
Claim 19 recites similar limitations to claim 9 above, and as a result, is rejected for similar issues in claim 9 above.
Claim 20 recites similar limitations to claim 11 above, and as a result, is rejected for similar issues in claim 11 above.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claim 1 recites the limitation of “receiving a data file identifying components and connections for a functional component of an integrated circuit”. While the limitation is cited in paragraph [0036] of the Specification, with operation 502 in Fig. 5 reciting the step of performing “receive data file”, it merely repeats the claim language, without further clarifying how the data file 102 is received in the invention of the Applicant, and simply states that data file 102 comprises “hard [third party IP], a netlist, or an OASIS formatted file”. Paragraphs [0045] and [0046] also repeat the claimed limitation language present in the independent claims, and do not further clarify how receiving a data file is performed in the invention.
Furthermore, the limitation of “parsing the data file to identify primitives and connections of the primitives” contains similar issues, as paragraph [0037] of the Specification merely repeats the claim language without further clarification of how the data file parser 122 parses the data file 102, in particular identifying primitives (stated in paragraph [0012] as being transistors, diodes, resistors, or other electrical components) and connections to the primitives, as whether it converts the primitives based on symbols used to identify components, or what programs are utilized to read data files containing electrical components and connections, despite the step being presented in operation 504 of Fig. 5. Paragraphs [0045] and [0046] also repeat the claimed limitation language present in the independent claims, and do not further clarify how parsing a data file is performed in the invention.
Furthermore, the limitation of “identifying that each of the determined matching portions is secure” contains similar issues, as paragraph [0038] of the Specification merely repeats the claim language without further clarification of how each of the matching portions 201 and 202 (seen in Fig. 2) as secure, with paragraph [0027] stating that the matching portions being deemed as secure have been assessed during “some prior security assessment”, and while security assessment 400 is described in paragraph [0029] that can identify “previously-unmatched portion of graph 200” as secure, it is not clarified as to how unmatched portions not found in the subgraph library 300 are determined as secure, such as checking for malicious code or faulty hardware. Paragraphs [0045] and [0046] also repeat the claimed limitation language present in the independent claims, and do not further clarify how identifying matching portions as secure is performed in the invention.
Furthermore, the limitation of “and based on at least identifying that each of the determined matching portions is secure, generating an alert that the data file is secure” contains similar issues, as paragraph [0040] of the Specification merely repeats the claim language without further clarification of how a data file being alerted as secure is performed, as it merely states that if no unmatched portions are found in comparison to the subgraph library 300, the data file is then flagged as secure in operation 516, with issues for the claimed limitation being similar to “identifying that each of the determined matching portions is secure” above. Paragraphs [0045] and [0046] also repeat the claimed limitation language present in the independent claims, and do not further clarify how generating an alert based on each of the matching portions as secure is performed in the invention.
Dependent claims 2-13 recite claims that depend on the independent claim 1, and as a result of claim 1 being rejected for lack of written description for certain limitations, claims 2-13 inherit the rejections of claim 1 above.
Claim 3 recites “for each unmatched portion [of the graph], performing a security assessment of the unmatched portion” is described in paragraph [0029] that a security assessment 400 identify “previously-unmatched portion of graph 200” as secure, it is not clarified as to how unmatched portions not found in the subgraph library 300 are determined as secure, such as checking for malicious code or faulty hardware. Similar issues are also raised for “based on at least the security assessment determining that the unmatched portion is secure, identifying the unmatched portion as secure” and “or, based on at least the security assessment not determining that the unmatched portion is secure, generating an alert that the data file is not secure” of claim 3. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Claim 4 recites “based on at least determining that the unmatched portion is secure, adding the unmatched portion to the subgraph library” is described in paragraph [0029] that a security assessment 400 identify “previously-unmatched portion of graph 200” as secure, it is not clarified as to how unmatched portions not found in the subgraph library 300 are determined as secure, such as checking for malicious code or faulty hardware. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Claim 5 recites “extracting a schematic of the unmatched portion” is described in paragraph [0021], described as visualization, with an extracted schematic, may enable determination of security, and paragraph [0041] describes it in operation 522 of Fig. 5 as extracting a schematic 410 of unmatched portion 203, without further clarification of how the extraction is performed for the unmatched portions of the graph. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Claim 7 recites “performing a circuit simulation of the unmatched portion” is described in paragraphs [0035] and [0041] as a circuit simulation 414 of unmatched portion 203 in Fig. 4, which includes an analog circuit simulation, such as SPICE simulation. Paragraph [0023] describes analog functional analysis of circuits further, but simply states that an unmatched circuit “[is] benign by ensuring it has no unexpected behavior in the analog domain”, without further clarifying what unexpected behaviors are defined as in an analog domain, with no example provided in the Specification provided. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Claim 8 recites “based on at least the security assessment not determining that the unmatched portion is secure, persisting an indication of the data file as not secure” is described in paragraph [0043] that if operation 524 of Fig. 5 does not determine a current unmatched portion as secure, “operation 530 generates alert 134 that data file 102 is not secure” and “operation 534 persists data file 102 with an indication 149 of data file 102 as not secure”, it is not clarified as to how unmatched portions not found in the subgraph library 300 are determined as not secure, such as checking for malicious code or faulty hardware. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Claim 9 recites “based on at least identifying that all portions of the first graph are secure, persisting an indication of the data file as secure” is described in paragraph [0040] that if operation 514 of Fig. 5 determines all portion of graph 200 as secure, “operation 518 persists data file 102 with an indication 145 of data file 102 as secure” in paragraph [0040], it is not clarified as to how unmatched portions not found in the subgraph library 300 are determined as secure, such as checking for malicious code or faulty hardware. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Claim 10 recites “wherein the data file comprises hard third party intellectual property (3PIP)”, and is described in paragraph [0036] of the Specification, where a data file 102 comprises “hard 3PIP”, and the Applicant does not provide examples or clarify how the invention identifies hard 3PIP in a data file. Paragraph [0047] also repeats the claimed limitation language present in the claims, and do not further clarify how the claimed limitations are performed in the invention.
Independent claim 14 recites similar limitations to claim 1 above, and as a result, is rejected for similar issues in claim 1 above.
Dependent claims 15-20 recite claims that depend on the independent claim 14, and as a result of claim 14 being rejected for lack of written description for certain limitations, claims 15-20 inherit the rejections of claim 14 above.
Claim 15 recites similar limitations to claim 3 above, and as a result, is rejected for similar issues in claim 3 above.
Claim 16 recites similar limitations to claim 4 above, and as a result, is rejected for similar issues in claim 4 above.
Claim 17 recites similar limitations to claims 5 and 7 above, and as a result, is rejected for similar issues in claims 5 and 7 above.
Claim 18 recites similar limitations to claim 8 above, and as a result, is rejected for similar issues in claim 8 above.
Claim 19 recites similar limitations to claim 9 above, and as a result, is rejected for similar issues in claim 9 above.
Claim 20 recites similar limitations to claim 10 above, and as a result, is rejected for similar issues in claim 10 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9-10, 14, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Al Faruque et al. (US 20240338491 A1), hereinafter Faruque).
Regarding claim 1, Faruque discloses ‘a method of establishing security assurance for an integrated circuit, the method comprising: receiving a data file identifying components and connections for a functional component of an integrated circuit’ ([0064] A system for detecting hardware Trojans is stated, and a circuit may comprise a plurality of input and output signals based on a base level file, which is based on a circuit, as stated in [0027] of Faruque. Input signal and output signals correspond to connections for functional components of the circuit of the Applicant.);
‘parsing the data file to identify primitives and connections of the primitives’ ([0064] Combined base-level file is parsed to a graph, which is first parsed as subgraphs that will combine into a larger graph. As stated in paragraph [0027], input and output signals correspond to connections to primitives, as signals must go through components in a circuit first.);
‘generating a first graph in which nodes of the first graph correspond to the primitives and edges of the first graph correspond to the connections of the primitives’ ([0015] Circuit is represented by data flow graph (DFG), which shows nodes and edges, shown in Fig. 6. [0064] Hardware-to-graph module 100 can combine subgraphs to a combined graph.);
‘determining matching portions of the first graph, wherein each matching portion of the determined matching portions matches any of a plurality of subgraphs of a subgraph library of known secure functionality’ ([0064] Combined graph can connect output signals with input signals via a root-to-leaf relationship and identify disconnected subgraphs and redundant nodes in combined graph, trimming disconnect subgraphs and redundant nodes in the combined graph, corresponding to determined matching portions and subgraphs in a subgraph library of the Applicant.);
‘identifying that each of the determined matching portion is secure’ ([0021] Hardware Trojans (HTs) are searched for using subgraph matching, and when no HTs are detected, the subgraph is considered a determined secure portion. [0075] Invention has a defense mechanism to generate a score to determine an HT detection in each of the nodes of the graph.);
‘and based on at least identifying that each of the determined matching portions is secure, generating an alert that the data file is secure’ ([0075] When all subgraphs are considered HT-free, the circuit can also be labeled Trojan-free, corresponding to generating an alert that the data file is secure of the Applicant, as the base-level file which contains the circuit configuration is also secure based on this evaluation.).
Regarding claim 9, Faruque discloses the limitations of claim 1 as described above, and Faruque also discloses ‘further comprising: based on at least identifying that all portions of the first graph are secure, persisting an indication of the data file as secure’ ([0075] When all subgraphs are considered HT-free, the circuit can also be labeled Trojan-free, corresponding to identifying that all portions of the first graph are secure, persisting an indication of the data file as secure of the Applicant, as the base-level file which contains the circuit configuration is also secure based on this evaluation.);
Regarding claim 10, Faruque discloses the limitations of claim 1 as described above and Faruque also discloses ‘wherein the data file comprises hard third party intellectual property (3PIP)’ ([0092] Design of an IP in a netlist can contains a hard IP, and paragraph [0017] states that third-party EDA tools, IP cores, and outsourcing can occur, with a third-party IP core corresponding to a hard 3PIP of the Applicant.).
Regarding claim 14, Faruque discloses all the limitations as described in independent claim 1, as the limitations are identical to claim 1 above. Faruque also teaches, as stated in claim 14, ‘a system for establishing integrity of digital content, the system comprising: a processor’ ([0064] Invention features a system for detecting hardware Trojans and IP piracy, and comprises a processor capable of executing computer-readable instructions.);
‘and a computer-readable medium storing instructions that are operative upon execution by the processor to’ ([0119] Physical storage media can store computer-readable instructions that are executable by a computer, including ROM, RAM, CD-ROM, DVD-ROM, and other forms of disk storage, and any other tangible mediums that can be processed by a computer.);
Regarding claim 19, Faruque discloses all the limitations as described in independent claim 14, as well as the limitations that are identical to dependent claim 9 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Faruque in view of Chen (US 10922462 B2).
Regarding claim 2, Faruque discloses the limitations of claim 1 as described above, and Faruque also discloses ‘further comprising: based on at least identifying that all portions of the first graph are secure […]’ ([0075] When all subgraphs are considered HT-free, the circuit can also be labeled Trojan-free, corresponding to generating an alert that the data file is secure of the Applicant.).
Faruque does not appear to disclose, but Chen teaches ‘[…] building the integrated circuit using the data file’ ([Col. 25, lines 62-67] Fig. 9, in step 930, the process 900 is invoked to manufacture the integrated circuit.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Chen before them, to include Chen’s ‘[…] building the integrated circuit using the data file’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency by tracking progress of the manufacturing of an integrated circuit, including fabrication, testing, shipping and installation of the manufactured chips, as taught by Chen [Col. 3, lines 39-45].
Regarding claim 12, Faruque discloses the limitations of claim 1 as described above. Faruque also discloses ‘wherein: the data file comprises a netlist’ ([0073] Base-level file can be a gate-level netlist file.);
‘the data file comprises a graphic data stream (GDS) formatted file’ ([0073] Physical layout file is also known as a GDSII file, which consists of a stream format for a graphics data system.);
Faruque does not appear to disclose, but Chen teaches ‘or the data file comprises an open artwork system interchange standard (OASIS) formatted file’ ([Col. 20, lines 47-48] OASIS file consists of a physical design data structure of a circuit, corresponding to an open artwork system interchange standard formatted file of the Applicant.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Chen before them, to include Chen’s ‘or the data file comprises an open artwork system interchange standard (OASIS) formatted file’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency by having a process transmit a physical design specification, such as an OASIS file, to a server to invoke manufacturing easily, as taught by Chen [Col. 26, lines 28-30].
Claims 3-8, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Faruque in view of Zavadsky et al. (US 8701058 B2), hereinafter Zavadsky.
Regarding claim 3, Faruque discloses the limitations of claim 1 as described above, and Faruque also discloses ‘further comprising: determining whether any portion of the first graph is unmatched, where an unmatched portion comprises a portion of the first graph that does not have a match to any subgraph of the subgraph library’ ([0064] Hardware-to-graph 100 can identify disconnected subgraphs and redundant nodes are identified, with disconnected subgraphs corresponding to unmatched portions that do not match any subgraphs in a subgraph library of the Applicant.).
Faruque does not appear to disclose, but Zavadsky teaches ‘and for each unmatched portion: performing a security assessment of the unmatched portion’ ([Col. 13, lines 6-7] Fig. 12, process for determining is hash value for subgraph exists in a library of circuits analyzed, wherein the hash value is computed from a subgraph of a subgraph that is currently unmatched with the main circuit.);
‘and either: based on at least the security assessment determining that the unmatched portion is secure, identifying the unmatched portion as secure’ ([Col. 13, lines 7-9] If a hash value is found, then the subgraph is grown by the process, corresponding to a security assessment determining the unmatched portion as secure of the Applicant. Hash values are used to identify functional blocks in the netlist of the target IC, as stated in [Col. 13, lines 26-27].);
‘or based on at least the security assessment not determining that the unmatched portion is secure, generating an alert that the data file is not secure’ ([Col. 13, lines 9-12] If the hash value is not found, then the subgraph is discarded and is not matched with the rest of the circuit, corresponding to the security assessment determining the unmatched portion, and therefore, the data file, as insecure of the Applicant.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Zavadsky before them, to include Zavadsky’s ‘and for each unmatched portion: performing a security assessment of the unmatched portion’, ‘and either: based on at least the security assessment determining that the unmatched portion is secure, identifying the unmatched portion as secure’, and ‘or based on at least the security assessment not determining that the unmatched portion is secure, generating an alert that the data file is not secure’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency by computing hash values of the subgraphs and obtaining relevant information to identify functional blocks in a netlist of an integrated circuit, as taught by Zavadsky [Col. 13, lines 25-27].
Regarding claim 4, Faruque in view of Zavadsky teaches the limitations of claims 1 and 3 as described above. Faruque does not appear to disclose, but Zavadsky teaches ‘further comprising: based on at least determining that the unmatched portion is secure, adding the unmatched portion to the subgraph library’ ([Col. 13, lines 7-9] If a hash value is found, then the subgraph is grown by the process, corresponding to adding the unmatched portion to the subgraph library of the Applicant. Further described in [Col. 13, lines 17-22], when a subgraph is grown, it is added to another subgraph found in a module library 3402, shown in Fig. 13.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Zavadsky before them, to include Zavadsky’s ‘further comprising: based on at least determining that the unmatched portion is secure, adding the unmatched portion to the subgraph library’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency by computing hash values of the subgraphs and obtaining relevant information to identify functional blocks in a netlist of an integrated circuit, as taught by Zavadsky [Col. 13, lines 25-27].
Regarding claim 5, Faruque in view of Zavadsky teaches the limitations of claims 1 and 3 as described above. Faruque does not appear to disclose, but Zavadsky teaches ‘wherein performing the security assessment comprises: extracting a schematic of the unmatched portion’ ([Col. 7, lines 43-46] Structural data mining is used for finding equivalent circuitry for automated schematics generation of library elements, including subgraphs described in [Col. 13, lines 7-22], which include the unmatched portions.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Zavadsky before them, to include Zavadsky’s ‘wherein performing the security assessment comprises: extracting a schematic of the unmatched portion’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency by utilizing data mining algorithms that can be used to handle large digital netlists, as taught by Zavadsky [Col. 8, lines 56-57].
Regarding claim 6, Faruque in view of Zavadsky teaches the limitations of claims 1 and 3 as described above. Faruque does not appear to disclose, but Zavadsky teaches ‘wherein performing the security assessment comprises: performing a Boolean analysis of the unmatched portion’ ([Col. 13, lines 6-7] Process of determining whether hash value exists in a library 3502 corresponds to the Boolean analysis of the Applicant for an unmatched portion.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Zavadsky before them, to include Zavadsky’s ‘wherein performing the security assessment comprises: performing a Boolean analysis of the unmatched portion’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to computing hash values of the subgraphs and obtaining relevant information to identify functional blocks in a netlist of an integrated circuit, as taught by Zavadsky [Col. 13, lines 25-27].
Regarding claim 7, Faruque in view of Zavadsky teaches the limitations of claims 1 and 3 as described above. Faruque does not appear to disclose, but Zavadsky teaches ‘wherein performing the security assessment comprises: performing a circuit simulation of the unmatched portion’ ([Col. 5, lines 46-50] Analyzing of an integrated circuit (IC) is done to extract from a low level netlist, which can include further analysis, along with [Col. 3, lines 12-14], wherein the analysis of a netlist can also involve a portion of at least one IC, which includes an unmatched portion.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Zavadsky before them, to include Zavadsky’s ‘wherein performing the security assessment comprises: performing a circuit simulation of the unmatched portion’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to computing hash values of the subgraphs and obtaining relevant information to identify functional blocks in a netlist of an integrated circuit, as taught by Zavadsky [Col. 13, lines 25-27].
Regarding claim 8, Faruque in view of Zavadsky teaches the limitations of claims 1 and 3 as described above. Faruque does not appear to disclose, but Zavadsky teaches ‘further comprising: based on at least the security assessment not determining that the unmatched portion is secure, persisting an indication of the data file as not secure’ ([Col. 13, lines 9-12] If the hash value is not found, then the subgraph is discarded and is not matched with the rest of the circuit, corresponding to the security assessment determining the unmatched portion, and therefore, the data file, as insecure of the Applicant.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Zavadsky before them, to include Zavadsky’s ‘further comprising: based on at least the security assessment not determining that the unmatched portion is secure, persisting an indication of the data file as not secure’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency by computing hash values of the subgraphs and obtaining relevant information to identify functional blocks in a netlist of an integrated circuit, as taught by Zavadsky [Col. 13, lines 25-27].
Regarding claim 15, Faruque discloses all the limitations as described in independent claim 14, and Faruque in view of Zavadsky teaches the limitations that are identical to dependent claim 3 above.
Regarding claim 16, Faruque discloses all the limitations as described in independent claim 14, and Faruque in view of Zavadsky teaches the limitations that are identical to dependent claim 4 above.
Regarding claim 17, Faruque discloses all the limitations as described in independent claim 14, and Faruque in view of Zavadsky teaches the limitations that are identical to dependent claims 5-7 above.
Regarding claim 18, Faruque discloses all the limitations as described in independent claim 14, and Faruque in view of Zavadsky teaches the limitations that are identical to dependent claim 8 above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Faruque in view of Chamberlain et al. (US 6289116 B1), hereinafter Chamberlain.
Regarding claim 11, Faruque discloses the limitations of claim 1 as described above. Faruque does not appear to disclose, but Chamberlain teaches ‘wherein the primitives comprise circuit elements selected from the list consisting of: transistors, diodes, resistors, capacitors, and inductors’ ([Col. 5, lines 37-39] Building blocks of circuits can include various types of transistors, resistors, capacitors, diodes, and inductors, that can be placed onto IC layout packages. The components listed above correspond to primitives in a circuit of the Applicant.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Chamberlain before them, to include Chamberlain’s ‘wherein the primitives comprise circuit elements selected from the list consisting of: transistors, diodes, resistors, capacitors, and inductors’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency as the building blocks are recognized as primitive functions and are generated as specialized symbols that are also recognized by the netlist using a GDSII layout, as taught by Chamberlain [Col. 4, lines 43-48].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Faruque in view of Hu et al. (US 10719631 B2), hereinafter Hu.
Regarding claim 13, Faruque discloses the limitations of claim 1 as described above. Faruque does not appear to disclose, but Hu teaches ‘wherein: the integrated circuit comprises a field programmable gate array (FPGA)’ ([Col. 19, lines 61-63] Apparatus can be implemented as an FPGA.);
‘or the integrated circuit comprises an application-specific integrated circuit (ASIC)’ ([Col. 19, lines 61-63] Apparatus can be implemented as an ASIC.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Faruque and Hu before them, to include Hu‘s ‘wherein: the integrated circuit comprises a field programmable gate array (FPGA)’ and ‘or the integrated circuit comprises an application-specific integrated circuit (ASIC)’ in Faruque’s method performing ‘establishing security assurance for an integrated circuit’. One would have been motivated to make such a combination to increase efficiency such as having circuit prototypes be built from hardware components such as ‘a number of FPGAs’, as taught by Hu [Col. 7, lines 31-33].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Faruque in view of Chamberlain, and further in view of Chen and Hu.
Regarding claim 20, Faruque discloses all the limitations as described in independent claim 14, with Faruque disclosing the limitations identical to claim 10 above, and Faruque in view of Chamberlain teaches the limitations that are identical to claim 11 above.
While the identical limitations of claim 12 present in claim 20 are not all taught by the combination of Faruque in view of Chamberlain, particularly the limitation of ‘or an open artwork system interchange standard (OASIS) formatted file’, the reference of Chen cures the deficiency for the limitations that are identical to claim 12 above, which the combination of Faruque in view of Chamberlain in further view of Chen teaches the limitation above for the same reasons as in claim 12.
Finally, while the combination of Faruque in view of Chamberlain in further view of Chen do not teach the identical limitations of claim 12 above, and present in claim 20, in particular ‘and the integrated circuit comprises a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)’, the reference of Hu teaches the limitation that is identical to claim 13 above, and present in claim 20 for the same reasons as in claim 13.
Conclusion
.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hu et al. (US 20180032760 A1, “Method And System For Detecting Hardware Trojans And Unintentional Design Flaws”)
Sinanoglu et al. (US 20190129892 A1, “SYSTEM, METHOD AND COMPUTER-ACCESSIBLE MEDIUM FOR STRIPPED-FUNCTIONALITY LOGIC LOCKING”)
Savidis et al. (US 20200342142 A1, “SECURING ANALOG MIXED-SIGNAL INTEGRATED CIRCUITS THROUGH SHARED DEPENDENCIES”)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOMMY MARTINEZ whose telephone number is (703)756-5651. The examiner can normally be reached Monday thru Friday 8AM-4PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jorge L. Ortiz-Criado can be reached at (571) 272-7624 on Monday thru Friday, 7AM-7PM ET. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.M./Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/Supervisory Patent Examiner, Art Unit 2496