DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of foreign priority to Japanese application filed on July 5th, 2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) filed on May 15th, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election without traverse of Species A, shown in FIGS. 1, 13, 20, and 21, a semiconductor device including RESURF layer and source region, with claims 1-16 being readable thereon, in the reply filed on August 4th, 2026, is acknowledged.
The requirement is made FINAL, claims 1-16 are being examined on their merits.
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading:
(a) TITLE OF THE INVENTION.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S).
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet).
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4;
As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008).
Claim 4 can be interpreted to mean that the impurity concentration of the second semiconductor layer is defined by the impurity concentration of the cathode region, the impurity concentration of the first semiconductor region of the anode region of the Zener diode, or the second semiconductor region of the anode region of the Zener diode.
For the purposes of this action, the claim will be interpreted to mean that the impurity concentration of the second semiconductor layer is defined by the impurity concentration of the second semiconductor region of the anode region of the Zener diode.
Regarding claim 12;
Claim 12 inherits the deficiency for the claim limitation “[the] impurity concentration of the second semiconductor layer” of claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13-14, and 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Sudou (JP2013183039A).
Regarding claim 13;
Sudou teaches a method of manufacturing a semiconductor device including a Zener diode,
the method comprising: (a) preparing a semiconductor substrate, the semiconductor substrate comprising: a substrate region of a first conductivity type; a first semiconductor layer of a second conductivity type opposite the first conductivity type formed on the substrate region (e.g. Fig. 4A, Detailed description “an n-type semiconductor layer NSL1 is formed on a semiconductor substrate SB. The n-type semiconductor layer NSL1 is formed by, for example, ion implantation or a combination of ion implantation and thermal diffusion. Further, the n-type semiconductor layer NSL1 may be an epitaxial film formed on the semiconductor substrate SB by an epitaxial growth method.”); and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer (e.g. Fig. 4B, Detailed description “a p-type semiconductor layer PSL1 is formed in the n-type semiconductor layer NSL1. The p-type semiconductor layer PSL1 is formed as follows. First, a resist film RF1 is formed on the semiconductor substrate SB. Next, the resist film RF1 is patterned by exposing and developing. Next, a p-type impurity is introduced into the semiconductor substrate SB using the resist film RF1 as a mask to form a p-type semiconductor layer PSL1. Next, the resist film RF1 is removed.”); (b) forming an anode region of the first conductivity type of the Zener diode in the second semiconductor layer (e.g. Fig. 5A, Detailed description “a p-type semiconductor layer PSL2 is formed in the p-type semiconductor layer PSL1. The p-type semiconductor layer PSL2 is formed as follows, for example. First, a resist film RF2 is formed on the semiconductor substrate SB. Next, the resist film RF2 is patterned by exposing and developing. Next, a p-type impurity is introduced into the semiconductor substrate SB using the resist film RF2 as a mask to form a p-type semiconductor layer PSL2. Next, the resist film RF2 is removed.”); and (c) forming a cathode region of the second conductivity type of the Zener diode in the second semiconductor layer (e.g. Fig. 5B Detailed description “an n-type semiconductor layer NSL2 is formed. The n-type semiconductor layer NSL2 is formed so as to include the p-type semiconductor layer PSL2 on the inner side in plan view and to have the lower surface in contact with the p-type semiconductor layer PSL1 and the p-type semiconductor layer PSL2… The n-type semiconductor layer NSL2 is formed as follows, for example. First, a resist film RF3 is formed on the semiconductor substrate SB. Next, the resist film RF3 is patterned by exposing and developing. Next, an n-type impurity is introduced into the semiconductor substrate SB using the resist film RF3 as a mask to form an n-type semiconductor layer NSL2. Next, the resist film RF3 is removed.”), wherein the (b) comprises: (b1) forming a mask layer on the semiconductor substrate (e.g. Detailed description “a resist film RF1 is formed on the semiconductor substrate SB.”); (b2) after the (b1), forming a first semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by a first ion implantation (e.g. Detailed description “The p-type semiconductor layer PSL1 may be formed by one ion implantation or may be formed by three or more ion implantations.”); (b3) after the (b1), forming a second semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by a second ion implantation (e.g. Detailed description “a p-type impurity is introduced into the semiconductor substrate SB using the resist film RF2 as a mask to form a p-type semiconductor layer PSL2.”); and (b4) after the (b2) and the (b3), removing the mask layer (e.g. Detailed description “Next, the resist film RF2 is removed…”), wherein an implantation energy of the second ion implantation is higher than an ion implantation energy of the first ion implantation (e.g. Detailed description “the p-type semiconductor layer PSL1 is formed by, for example, twice ion implantation. When the ion implantation species is boron, for example, after ion implantation is performed with an implantation energy of 50 Kev or more and 200 Kev or less and an implantation dose of 6e12 cm −2 or more and 1e13 cm −2 or less, the implantation energy is 400 Kev or more and 1000 Kev or less.”), wherein an impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region (e.g. Detailed description “The p-type semiconductor layer PSL2 has a higher impurity concentration than the p-type semiconductor layer PSL1.”), wherein after the (b2) and the (b3), the second semiconductor region is located under the first semiconductor region (e.g. see examiner markup), and wherein after the (b2) and the (c), the first semiconductor region is located under the cathode region (e.g. see examiner markup in claim 1 rejection), and a first PN junction is formed between the first semiconductor region and the cathode region (e.g. see examiner markup in claim 1 rejection).
Regarding claim 14;
Sudou further teaches that a dose amount of the second ion implantation is greater than a dose amount of the first ion implantation (e.g. Detailed description “the p-type semiconductor layer PSL1 is formed by, for example, twice ion implantation. When the ion implantation species is boron, for example, after ion implantation is performed…[with] an implantation dose of 6e12 cm −2 or more and 1e13 cm −2 or less… There ions are implanted under the conditions of 1E13 cm -2 or more 6E13cm -2 or less.”).
Regarding claim 16;
Sudou further teaches that the (b) comprises: (b5) forming a third semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by a third ion implantation (e.g. Detailed description “The p-type semiconductor layer PSL5 is formed by, for example, ion implantation or a combination of ion implantation and thermal diffusion.”), wherein the third semiconductor region covers a side surface of the first semiconductor region, a side surface of the second semiconductor region, and a bottom surface of the second semiconductor region (e.g. Detailed description “The p-type semiconductor layer PSL5 is formed in the n-type semiconductor layer NSL1 so as to include the p-type semiconductor layer PSL1 inside. That is, the p-type semiconductor layer PSL1 is covered with the p-type semiconductor layer PSL5 on the side and bottom surfaces.”), and wherein the impurity concentration of the first semiconductor region is higher than an impurity concentration of the third semiconductor region (e.g. Detailed description “The impurity concentration of the p-type semiconductor layer PSL5 is lower than the impurity concentration of the p-type semiconductor layer PSL1.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sudou (JP2013183039A) in view of Lin et al. (US8946860B2), further in view of Chen et al. (US9099487B2) for the following reasons:
Regarding claim 1;
Sudou teaches a semiconductor device comprising: a semiconductor substrate comprising: a substrate region of a first conductivity type (e.g. Fig. 11 ref SB, Detailed description “The semiconductor device SD1 includes a semiconductor substrate SB. The semiconductor substrate SB has, for example, n-type or p-type conductivity”); a first semiconductor layer of a second conductivity type opposite the first conductivity type formed on the substrate region (e.g. Fig. 11 ref NSL1, Detailed description “the n-type semiconductor layer NSL1 is provided on the semiconductor substrate SB. The n-type semiconductor layer NSL1 has, for example, an n-type conductivity type.”); and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer (e.g. Fig. 11 ref PSL1-3+NSL2); a cathode region of the second conductivity type of a Zener diode, the cathode region being formed in the second semiconductor layer (e.g. Fig. 11 ref NSL2); and an anode region of the first conductivity type of the Zener diode, the anode region being formed in the second semiconductor layer (e.g. Fig. 11 ref PSL1-PSL3), wherein a first PN junction is formed between the anode region and the cathode region (e.g. Fig. 11 ref PNJ2).
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Sudou is silent to an element isolation region penetrating through the second semiconductor layer and the first semiconductor layer and reaching the substrate region as claimed.
However, Lin et al. teaches a semiconductor device with a deep trench isolation structure (e.g. Fig. 10 ref 124, Detailed description [0014] “The deep isolation regions 124 are integral and provide a contiguous or continuous isolation region…”).
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It would have been obvious to someone having ordinary skill in the art to modify the semiconductor device taught in Sudou to include the deep trench isolation (DTI) structure taught in Lin et al. to reduce unintended conductive pathways, leakage current, latch-up susceptibility, and electrical interaction between neighboring/adjacent active elements because the added DTI structure increases electrical separation between conductive or doped regions, improving device isolation while preserving intended device operability (e.g. Detailed description [0014] “The deep isolation regions 124 are integral and provide a contiguous or continuous isolation region…to isolate the bipolar transistor structure from adjacent semiconductor devices fabricated on the same semiconductor substrate.”).
Further, Sudou is also silent to the anode region comprising: a first semiconductor region of the first conductivity type formed under the cathode region; and a second semiconductor region of the first conductivity type formed under the first semiconductor region as claimed.
However, Chen et al. teaches Zener diode including an anode region comprising: a first semiconductor region of the first conductivity type formed under a cathode region (e.g. Fig. 7 ref 702); and a second semiconductor region of the first conductivity type formed under the first semiconductor region (e.g. Fig. 7 ref 704), and wherein an impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region (e.g. Detailed description “FIG. 7 depicts another embodiment of a Zener diode semiconductor device structure 700 that includes a relatively heavily-doped anode contact region 704 that is electrically connected to the anode region 104 via a relatively lightly-doped anode interconnect region 702. In this regard, the anode contact region 704 has a dopant concentration that is greater than that of the anode region 104 to support formation of a lower resistance anode contact 748.”).
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It would have been obvious to someone having ordinary skill in the art to modify the anode region taught in Sudou to be formed with the first and second semiconductor regions taught in Chen et al. to reduce contact/series resistance of the anode contact because the decreased resistance will lead to improved response properties (e.g. current drive, voltage transfer, signal delay, power efficiency, etc.) for the resulting device (e.g. Detailed description [0039] “FIG. 7 depicts another embodiment of a Zener diode semiconductor device structure 700 that includes a relatively heavily-doped anode contact region 704 that is electrically connected to the anode region 104 via a relatively lightly-doped anode interconnect region 702. In this regard, the anode contact region 704 has a dopant concentration that is greater than that of the anode region 104 to support formation of a lower resistance anode contact 748.”).
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to incorporate the DTI structure taught in Lin et al. and the anode region taught in Chen et al. into the Semiconductor device taught in Sudou because each structure would perform its established function in the combined device, leading to a predictable aggregation of design advantages in the combined device.
Regarding claim 2;
Sudou further teaches that the anode region comprises a third semiconductor region of the first conductivity type covering a side surface of the first semiconductor region, a side surface of the second semiconductor region, and a bottom surface of the second semiconductor region (e.g. Fig. 11 ref PSL1), and wherein the impurity concentration of the first semiconductor region is higher than an impurity concentration of the third semiconductor region (e.g. Detailed description “…the concentration of the p-type impurity constituting the p-type semiconductor layer PSL2 is higher than the concentration of the p-type impurity constituting the p-type semiconductor layer PSL1.”).
Regarding claim 3;
Sudou further teaches that the cathode region is disposed adjacent to the first semiconductor region and the third semiconductor region (e.g. see examiner markup), and wherein a second PN junction is formed between the third semiconductor region and the cathode region (e.g. Fig. 11 ref PNJ1).
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Regarding claim 4;
Sudou further teaches that the impurity concentration of the third semiconductor region is higher than an impurity concentration of the second semiconductor layer (e.g. Detailed description “The p-type semiconductor layer PSL2 has a higher impurity concentration than the p-type semiconductor layer PSL1.”).
Regarding claim 5;
Sudou further teaches that the semiconductor device of claim 3 comprises: a first plug disposed on the cathode region and electrically connected to the cathode region (e.g. Fig. 11 ref EL2, Detailed description “The electrode EL2 is connected to the n-type semiconductor layer NSL2.”); and a second plug electrically connected to the anode region (e.g. Fig. 11 ref EL1, Detailed description “The electrode EL1 is connected to the p-type semiconductor layer PSL1.”).
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Regarding claim 6;
Sudou is silent to a first potential being supplied from the first plug to the cathode region, a second potential is supplied from the second plug to the anode region, and the first potential and the second potential are lower than a potential of the substrate region as claimed.
However, language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
In the instant application the following limitations of claim 6 lines 2-7 are understood to be functional: “a first potential is supplied from the first plug… a second potential is supplied from the second plug… wherein the first potential and the second potential are lower than a potential of the substrate region.”
The limitations describe purpose, function, operation, or intent-of-use. However, the claim does not disclose a sufficient structure which supports the function. Since Sudou shows an identical structure as claimed, namely a first plug electrically connected to the cathode region, and a second plug electrically connected to the anode region (e.g. see claim 5 rejection), the Examiner submits that the first and second electrodes are capable of producing the claimed results (i.e. supplying a first potential to the cathode region, a second potential to the anode region with the first and second potential being lower than the potential of the substrate).
Consequently, the teachings of Sudou will be taken to read on the claimed elements of the instant claim.
Regarding claim 7;
Sudou is silent to first and second potential being negative potentials as claimed.
However, language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
In the instant application the following limitations of claim 7 lines 1-2 are understood to be functional: “the first potential and the second potential are negative potentials”.
The limitations describe purpose, function, operation, or intent-of-use. However, the claim does not disclose a sufficient structure which supports the function. Since Sudou shows an identical structure as claimed, namely a first plug electrically connected to the cathode region, and a second plug electrically connected to the anode region (e.g. see claim 5 rejection), the Examiner submits that the first and second electrodes are capable of producing the claimed results (i.e. supplying a first potential and a second potential which are negative potentials).
Consequently, the teachings of Sudou will be taken to read on the claimed elements of the instant claim.
Regarding claim 8;
Sudou is silent to the second potential being higher than the first potential as claimed.
However, language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
In the instant application the following limitations of claim 8 lines 1-2 are understood to be functional: “the second potential is higher than the first potential.”.
The limitations describe purpose, function, operation, or intent-of-use. However, the claim does not disclose a sufficient structure which supports the function. Since Sudou shows an identical structure as claimed, namely a first plug electrically connected to the cathode region, and a second plug electrically connected to the anode region (e.g. see claim 5 rejection), the Examiner submits that the first and second electrodes are capable of producing the claimed results (i.e. having a second potential which is higher than a first potential).
Consequently, the teachings of Sudou will be taken to read on the claimed elements of the instant claim.
Regarding claim 9;
Sudou further teaches that the semiconductor device of claim 5 comprises: a fourth semiconductor region of the first conductivity type formed in the third semiconductor region (e.g. Fig. 11 ref PSL3), wherein the second plug is disposed on the fourth semiconductor region and electrically connected to the third semiconductor region via the fourth semiconductor region (e.g. Detailed description “The p-type semiconductor layer PSL3 is provided in the p-type semiconductor layer PSL2 so as to connect the electrode EL1 and the p-type semiconductor layer PSL2.”).
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Regarding claim 10;
Sudou is silent to an element isolation structure as claimed.
However, Lin et al. teaches a semiconductor device including a DTI structure (e.g. Detailed description [0014] “The deep isolation regions 124 are integral and provide a contiguous or continuous isolation region that circumscribes or otherwise laterally encloses the bipolar transistor structure to isolate the bipolar transistor structure from adjacent semiconductor devices fabricated on the same semiconductor substrate.”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to modify the semiconductor device taught in Sudou to be formed with the DTI structure taught in Lin et al. surrounding the cathode region and the anode region to reduce unintended conductive pathways, leakage current, latch-up susceptibility, and electrical interaction between neighboring/adjacent active elements because the added DTI structure increases electrical separation between conductive or doped regions, improving device isolation while preserving intended device operability.
Regarding claim 11;
Sudou is silent to the potential of the first semiconductor layer being a floating potential as claimed.
However, the first semiconductor layer (e.g. Fig. 11 ref NSL1) is not shown or described to be influenced or biased by any other layers in the semiconductor device taught in Sudou. In the absence of applicant’s specific definition of what is construed to make the first semiconductor layer have a “floating potential”, the teaching of Sudou will be taken to read on the instant claim as it is within the common definition of a “floating potential” (e.g. an element electrically isolated from all external bias which has a potential determined by the potential of other elements in the system).
Regarding claim 12;
Sudou further teaches that the semiconductor device of claim 4 comprises: a fifth semiconductor region of the first conductivity type formed in the second semiconductor layer and located under the third semiconductor region (e.g. Fig. 7 ref PBL, Detailed description “The p-type buried layer PBL is connected to the lower end of the p-type semiconductor layer PSL1. For this reason, the p-type buried layer PBL constitutes a p-type semiconductor layer integrally with the p-type semiconductor layer PSL1…”), wherein an impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the second semiconductor layer (e.g. Detailed description “The p-type buried layer PBL has a higher impurity concentration than the p-type semiconductor layer PSL1”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sudou (JP2013183039A) in view of Lin et al. (US8946860B2) for the following reasons:
Regarding claim 15;
Sudou is silent to a method of manufacturing a semiconductor device including a Zener diode, the method comprising: (d) forming an element isolation region, the element isolation region penetrating through the second semiconductor layer and the first semiconductor layer and reaching the substrate region as claimed.
However, Lin et al. teaches a method of fabricating a semiconductor device including a deep trench isolation (DTI) etch step (e.g. Detailed description [0014] “to form deep isolation regions 124, the interior of the semiconductor device structure 100 is masked with a masking material that is subsequently patterned to expose the peripheral portions of the epitaxial layer 114 and seed layer 106, which are then etched until the insulating layer 104 is etched through, and thereafter, a dielectric material, such as an oxide material, may be deposited in the trenches or grown on exposed surfaces of the trenches to fill the trenches. Although not illustrated in FIG. 5, in some embodiments, an inner conductive material, such as a doped polysilicon material, may be formed in the interior or central portion of the deep isolation regions 124 to facilitate an electrical connection to the support layer 102. The deep isolation regions 124 are integral and provide a contiguous or continuous isolation region that circumscribes or otherwise laterally encloses the bipolar transistor structure to isolate the bipolar transistor structure from adjacent semiconductor devices fabricated on the same semiconductor substrate.”)
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to modify the method of manufacturing a semiconductor device including a Zener diode taught in Sudou to include the DTI etch step taught in Lin et al. to provide a resulting device with reduced unintended conductive pathways, leakage current, latch-up susceptibility, and electrical interaction between neighboring/adjacent active elements because the added DTI structure increases electrical separation between conductive or doped regions, improving device isolation while preserving intended device operability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights