DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-15) in the reply filed on 3/2/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “plurality of insulating layers” as described in claim 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 6-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kikuiri et al. (US PG. Pub. 2003/0066680).
Regarding claim 1 – Kikuiri teaches a circuit board (fig. 14) comprising: an insulating layer (106 [paragraph 0008] Kikuiri states, “an insulating layer 106”) having a first surface (top surface) and a second surface (bottom surface) opposing each other; and a first connection pad (100 [paragraph 0007] Kikuiri states, “the terminal electrode 100”) having a first portion (100B [paragraph 0010] Kikuiri states, “electrode portion 100B”) embedded in the insulating layer (106) and at least partly exposed (see upper surface of 100B) from the insulating layer (106) on the first surface (top surface) and a second portion (100A [paragraph 0012] Kikuiri states, “the electrode portion 100A”) closer to the second surface (bottom surface) than the first portion (100B), wherein, a first width of the first portion (100B) in a direction parallel to the first surface is different from a second width of the second portion (100A) in the direction parallel to the first surface ([paragraph 0009] Kikuiri states, “the lead wire 102 is formed to have a small width, e.g., a few dozen .mu.m, as the size of a thin-film magnetic device or the like is increasingly reduced. This means that the electrode portion 100A has to be formed to have a small sectional width, while the terminal electrode 100 is required to have a joint surface area of a certain size (e.g., 100.times.100 .mu.m)”).
Regarding claim 2 – Kikuiri teaches the circuit board of claim 1, wherein the first width is greater than the second width ([paragraph 0009] Kikuiri states, “the lead wire 102 is formed to have a small width, e.g., a few dozen .mu.m, as the size of a thin-film magnetic device or the like is increasingly reduced. This means that the electrode portion 100A has to be formed to have a small sectional width, while the terminal electrode 100 is required to have a joint surface area of a certain size (e.g., 100.times.100 .mu.m)”; claimed structure shown in figure 14).
Regarding claim 3 – Kikuiri teaches the circuit board of claim 1, wherein the first portion (fig. 14, 100B) and the second portion (100A) are configured to have a step (see “step” structure between 100B and 100A that appears equivalent to that of the instant application).
Regarding claim 6 – Kikuiri teaches the circuit board of claim 1, further comprising a conductive layer (fig. 14, 105 [paragraph 0008] Kikuiri states, “gold electrode layer 105”) disposed on the first connection pad (100).
Regarding claim 7 – Kikuiri teaches the circuit board of claim 6, wherein the conductive layer (fig. 14, 105) is disposed on the exposed portion of the first connection pad (100).
Regarding claim 8 – Kikuiri teaches the circuit board of claim 6, wherein the conductive layer (fig. 14, 105) protrudes on the first surface (top surface) of the insulating layer (106).
Regarding claim 9 – Kikuiri teaches the circuit board of claim 6, wherein a width of the conductive layer (fig. 14, 105) in the direction parallel to the first surface (top surface) is greater than the second width of the second portion (100A) of the first connection pad (100).
Regarding claim 10 – Kikuiri teaches the circuit board of claim 6, wherein a width of the conductive layer (fig. 14, 105) in the direction parallel to the first surface (top surface) is equal to or greater than the first width of the first portion (100B) of the first connection pad (100; figure 14 shows the conductive layer 105 extending beyond the width of the first portion 100B).
Regarding claim 11 – Kikuiri teaches the circuit board of claim 6, wherein the conductive layer (fig. 14, 105) includes a gold (Au) plating layer ([paragraph 0008] Kikuiri states, “gold electrode layer 105”).
Claim(s) 1-10, 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al. (US PG. Pub. 2016/0021744).
Regarding claim 1 – Baek teaches a circuit board (figs. 1, 4 & 5 [title] Baek states, “printed circuit board”) comprising: an insulating layer (200 [paragraph 0019] Baek states, “insulating layer 200”) having a first surface (top surface) and a second surface (bottom surface) opposing each other; and a first connection pad (fig. 4, combination of elements 110 & 80) having a first portion (110 [paragraph 0019] Baek states, “circuit pattern 110”) embedded in the insulating layer (200) and at least partly exposed (exposed top surface) from the insulating layer (200) on the first surface (top surface) and a second portion (80 [paragraph 0019] Baek states, “coupling pad 80”) closer to the second surface (bottom surface) than the first portion (110), wherein, a first width of the first portion (110) in a direction parallel to the first surface is different from a second width of the second portion (80) in the direction parallel to the first surface ([paragraph 0045] Baek states, “A width W.sub.P of the coupling pad 80 formed on the central portion of the first circuit pattern 100 may be narrower than the width W.sub.C of the first circuit pattern 110”).
Regarding claim 2 – Baek teaches the circuit board of claim 1, wherein the first width is greater than the second width (fig. 4 [paragraph 0045] Baek states, “A width W.sub.P of the coupling pad 80 formed on the central portion of the first circuit pattern 100 may be narrower than the width W.sub.C of the first circuit pattern 110”).
Regarding claim 3 – Baek teaches the circuit board of claim 1, wherein the first portion (fig. 4, 110) and the second portion (80) are configured to have a step (see “step” structure between 110 and 80 that appears equivalent to that of the instant application).
Regarding claim 4 – Baek teaches the circuit board of claim 1, further comprising a protection layer (figs. 1 & 4, 300 [paragraph 0101] Baek states, “a solder resist 300”) disposed on the first surface (top surface) of the insulating layer (200) and having an opening (see opening exposing first connection pad 110/80) to expose the first connection pad (combination of elements 110 & 80).
Regarding claim 5 – Baek teaches the circuit board of claim 4, further comprising a first circuit wiring (fig. 1, combination of wirings 110 & 150) embedded in the insulating layer (200) and covered with the protection layer (300), wherein a thickness of the first circuit wiring (110/150) in a direction perpendicular to the first surface (top surface of insulating layer 200) is greater than a thickness of the first portion (110) of the first connection pad (combination of elements 110 & 80) in the direction perpendicular to the first surface (top surface of insulating layer 200).
Regarding claim 6 – Baek teaches the circuit board of claim 1, further comprising a conductive layer (fig. 3, 50 [paragraph 0019] Baek states, “bump pad 50”) disposed on the first connection pad (110/80).
Regarding claim 7 – Baek teaches the circuit board of claim 6, wherein the conductive layer (fig. 4, 50) is disposed on the exposed portion of the first connection pad (110/80).
Regarding claim 8 – Baek teaches the circuit board of claim 6, wherein the conductive layer (fig. 4, 50) protrudes on the first surface (top surface) of the insulating layer (200).
Regarding claim 9 – Baek teaches the circuit board of claim 6, wherein a width of the conductive layer (fig. 4, 50) in the direction parallel to the first surface (top surface) is greater than the second width of the second portion (80) of the first connection pad (110/80).
Regarding claim 10 – Baek teaches the circuit board of claim 6, wherein a width of the conductive layer (fig. 4, 50) in the direction parallel to the first surface (top surface) is equal to or greater than the first width of the first portion (110) of the first connection pad (110/80; figure 4 shows the conductive layer 50 extending beyond the width of the first portion 110).
Regarding claim 12 – Baek teaches the circuit board of claim 1, wherein the first connection pad (figs. 1 & 4, combination of elements 110 & 80) includes copper (Cu) ([paragraph 0028] Baek states, “Any material may be used in the first and second circuit patterns 110 and 120 without limitation as long as it is used as a conductive metal for a circuit pattern. For example, copper (Cu) may be used”).
Regarding claim 13 – Baek teaches the circuit board of claim 1, wherein the first connection pad (figs. 1 & 4, combination of elements 110 & 80) is disposed in a bond finger region (figure 1 shows the claimed structure, the first connection pad 110/80 can be bonded to other components in the region shown above the insulating layer and appears to meet the limitation of “bond finger region” as described by the instant application).
Regarding claim 14 – Baek teaches the circuit board of claim 1, further comprising a second connection pad (fig. 1, 120 [paragraph 0026] Baek states, “second circuit pattern 120”) disposed on the second surface (bottom surface) of the insulating layers (200).
Regarding claim 15 – Baek teaches the circuit board of claim 1, wherein the insulating layer (fig. 5, 200) includes a plurality of insulating layers (200 & 500 [paragraph 0047] Baek states, “a buildup layer 500 may be further stacked on the other surface of the insulating layer 200”), and the circuit board further comprises a plurality of circuit layers (120 and wiring shown within the buildup layer 500) disposed in or on the plurality of insulating layers (200 & 500).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US PG. Pub. 2015/0101852) discloses a PCB.
Kaneko (US Patent 8754336) discloses a wiring board.
Kaneko (US PG. Pub. 2008/0298038) discloses a wiring board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847