DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaneko et al. (US PG. Pub. 2015/0014027).
Regarding claim 21 – Kaneko teaches a circuit board (figs. 1A-1B, 10 [paragraph 0021] Kaneko states, “wiring board 10”) comprising: an insulating layer (12 [paragraph 0023] Kaneko states, “insulating layer 12”) having a first surface (12a) and a second surface (bottom surface of insulating layer 12) opposing each other; a first connection pad (11 [paragraph 0023] Kaneko states, “pads 11”) having a first portion (upper portion of pad 11 as shown in annotated figure 1B below) embedded in the insulating layer (12) and at least partly exposed from the insulating layer (12) on the first surface (12a) and a second portion (lower portion of pad 11 as shown in annotated figure 1B below) closer to the second surface (bottom surface of 12) than the first portion; a protection layer (19 [paragraph 0020] Kaneko states, “solder resist layer 19”) disposed on the first surface (12a) of the insulating layer (12) and having an opening (19x [paragraph 0039] Kaneko states, “opening portion 19x”) to expose the first connection pad (11); and a first circuit wiring (21 [paragraph 0041] Kaneko states, “wiring patterns 21”) embedded in the insulating layer (12) and covered with the protection layer (19), wherein, a first width of the first portion in a direction parallel to the first surface (12a) is different from a second width of the second portion in the direction parallel to the first surface (claimed structure shown in annotated figure 1B), and a thickness (T [paragraph 0033] Kaneko states, “thickness T of the pads 11 may be about 10 .mu.m”) of the first connection pad (11) including the first portion and the second portion in a direction perpendicular to the first surface (12a) is equal to a thickness of the first circuit wiring (21) in the direction perpendicular to the first surface (12a; figure 1B shows the first connection pad 11 and the first circuit wiring 21 having the same thickness T).
PNG
media_image1.png
690
1146
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-10 and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US PG. Pub. 2016/0021744) in view of Sakai (US PG. Pub. 2017/0098600).
Regarding claim 1 – Baek teaches a circuit board (figs. 1, 4 & 5 [title] Baek states, “printed circuit board”) comprising: an insulating layer (200 [paragraph 0019] Baek states, “insulating layer 200”) having a first surface (top surface) and a second surface (bottom surface) opposing each other; and a first connection pad (fig. 4, combination of elements 110 & 80) having a first portion (110 [paragraph 0019] Baek states, “circuit pattern 110”) embedded in the insulating layer (200) and at least partly exposed (exposed top surface) from the insulating layer (200) on the first surface (top surface) and a second portion (80 [paragraph 0019] Baek states, “coupling pad 80”) closer to the second surface (bottom surface) than the first portion (110); a first circuit wiring (fig. 1, combination of wirings 110 & 150 [paragraph 0019 & 0029] Baek states, “first circuit pattern 110…via 150”) to be embedded in the insulating layer (200), and a protection layer (300 [paragraph 0030] Baek states, “solder resist 300”) disposed on the first surface (top surface) of the insulating layer (200) to cover the first circuit wiring (110) and having an opening (see opening exposing the first connection pad 80/110) to expose the first connection pad (80/110), wherein, a first width of the first portion (110) in a direction parallel to the first surface is different from a second width of the second portion (80) in the direction parallel to the first surface ([paragraph 0045] Baek states, “A width W.sub.P of the coupling pad 80 formed on the central portion of the first circuit pattern 100 may be narrower than the width W.sub.C of the first circuit pattern 110”).
Baek fails to explicitly teach a first circuit wiring extending from the first surface of the insulating layer to be embedded in the insulating layer.
Sakai teaches a circuit board (figs. 1A-2, 1 [paragraph 0021] Sakai states, “a wiring board 1”) with a first circuit wiring (13 [paragraph 0024] Sakai states, “wiring pattern 13”) extending form the first surface (20a) of the insulating layer (20 [paragraph 0024] Sakai states, “the insulating layer 20”) to be embedded in the insulating layer (20), and a protection layer (40 [paragraph 0035] Sakai states, “solder resist layer 40”) disposed on the first surface (20a) of the insulating layer (20) to cover the first circuit wiring (13) and having an opening to expose the first connection pad (11 [paragraph 0024] Sakai states, “external connection pads 11”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a first circuit wiring embedded in the insulating layer and a protective layer thereon as taught by Baek with the first circuit wiring extending from the first surface of the insulating layer as taught by Sakai because Sakai states, “the wiring layer 10 to make the upper surface 20a of the insulating layer 20 and the upper surface 10a of the wiring layer 10 substantially flush with each other with substantially no steps between the upper surface 20a of the insulating layer 20 and the upper surface 10a of the wiring layer 10. Therefore, it is possible to provide the wiring layer 10 buried in the insulating layer 20 with a desired thickness, and accordingly, to avoid breakage of the wiring patterns 13 of the wiring layer 10 even when the wiring patterns 13 are formed to be thin for miniaturization and a higher density of the wiring patterns 13” [paragraph 0072].
Regarding claim 2 – Baek in view of Sakai teach the circuit board of claim 1, wherein the first width is greater than the second width (Baek; fig. 4 [paragraph 0045] Baek states, “A width W.sub.P of the coupling pad 80 formed on the central portion of the first circuit pattern 100 may be narrower than the width W.sub.C of the first circuit pattern 110”).
Regarding claim 3 – Baek in view of Sakai teach the circuit board of claim 1, wherein the first portion (Baek; fig. 4, 110) and the second portion (80) are configured to have a step (see “step” structure between 110 and 80 that appears equivalent to that of the instant application).
Regarding claim 5 – Baek in view of Sakai teach the circuit board of claim 1, wherein a thickness of the first circuit wiring (Baek; fig. 1, combination of wirings 110 & 150) in a direction perpendicular to the first surface (top surface of insulating layer 200) is greater than a thickness of the first portion (110) of the first connection pad (combination of elements 110 & 80) in the direction perpendicular to the first surface (top surface of insulating layer 200).
Regarding claim 6 – Baek in view of Sakai teach the circuit board of claim 1, further comprising a conductive layer (Baek; fig. 3, 50 [paragraph 0019] Baek states, “bump pad 50”) disposed on the first connection pad (110/80).
Regarding claim 7 – Baek in view of Sakai teach the circuit board of claim 6, wherein the conductive layer (Baek; fig. 4, 50) is disposed on the exposed portion of the first connection pad (110/80).
Regarding claim 8 – Baek in view of Sakai teach the circuit board of claim 6, wherein the conductive layer (Baek; fig. 4, 50) protrudes on the first surface (top surface) of the insulating layer (200).
Regarding claim 9 – Baek in view of Sakai teach the circuit board of claim 6, wherein a width of the conductive layer (Baek; fig. 4, 50) in the direction parallel to the first surface (top surface) is greater than the second width of the second portion (80) of the first connection pad (110/80).
Regarding claim 10 – Baek in view of Sakai teach the circuit board of claim 6, wherein a width of the conductive layer (Baek; fig. 4, 50) in the direction parallel to the first surface (top surface) is equal to or greater than the first width of the first portion (110) of the first connection pad (110/80; figure 4 shows the conductive layer 50 extending beyond the width of the first portion 110).
Regarding claim 12 – Baek in view of Sakai teach the circuit board of claim 1, wherein the first connection pad (Baek; figs. 1 & 4, combination of elements 110 & 80) includes copper (Cu) ([paragraph 0028] Baek states, “Any material may be used in the first and second circuit patterns 110 and 120 without limitation as long as it is used as a conductive metal for a circuit pattern. For example, copper (Cu) may be used”).
Regarding claim 13 – Baek in view of Sakai teach the circuit board of claim 1, wherein the first connection pad (Baek; figs. 1 & 4, combination of elements 110 & 80) is disposed in a bond finger region (figure 1 shows the claimed structure, the first connection pad 110/80 can be bonded to other components in the region shown above the insulating layer and appears to meet the limitation of “bond finger region” as described by the instant application).
Regarding claim 14 – Baek in view of Sakai teach the circuit board of claim 1, further comprising a second connection pad (Baek; fig. 1, 120 [paragraph 0026] Baek states, “second circuit pattern 120”) disposed on the second surface (bottom surface) of the insulating layers (200).
Regarding claim 15 – Baek in view of Sakai teach the circuit board of claim 1, further comprising a second circuit wiring (Baek; fig. 1, right and left circuit wirings 80/110) disposed in the insulating layer (200; figure 1 shows two distinct circuit wirings).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. in view of Sakai as applied to claim 6 above, and further in view of Suzuki (US PG. Pub. 2016/0064319).
Regarding claim 11 – Baek in view of Sakai teach the circuit board of claim 6, but fails to teach wherein the conductive layer includes a gold (Au) plating layer.
Suzuki teaches a circuit board (figs. 1A-1B, 1) having a conductive layer (13) wherein the conductive layer includes a gold (Au) plating layer ([paragraph 0033] Suzuki states, “gold (Au) may be used as the material of the second metal layer 13”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a conductive layer as taught by Baek in view of Sakai with the conductive layer includes a gold (Au) plating layer as taught by Suzuki because a gold finishing layer upon a pad is known to improve the electrical and mechanical properties between the pad and the component contact and/or solder.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-15 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Prosecution Insights