Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-19 recite “silicone” which is NOT a semiconductor, thus it is assumed that the Applicant means silicon.
Allowable Subject Matter
Claims 2, 13, 14, 15, 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, 6-12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (US 20130168837 A1) hereafter referred to as Kato in view of Akiba et al. (US 20170229359 A1) hereafter referred to as Akiba
In regard to claim 1 Kato teaches a dual silicone no-lead (DSN) semiconductor device [see Fig. 2A, Fig. 2B “FIG. 4A illustrates the dimensions of the post-shaped electrodes and the pads of the in-plane wiring lines of the ESD protection device 101 illustrated in FIG. 2A. FIG. 4B illustrates a comparative example” “the shape of the post-shaped electrodes in a sectional view taken along a plane parallel or substantially parallel with the direction (thickness direction) in which the post-shaped electrodes extend is that of a trapezoid” see that the comparison is the trapezoid ] package comprising a bond pad [“terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film” “interlayer wiring lines 24A and 24B whose first ends are respectively connected to the input/output electrodes 21A and 21B, the in-plane wiring lines 25A and 25B whose first ends are respectively connected to the second ends of the interlayer wiring lines 24A and 24B, and the post-shaped electrodes 27A and 27B respectively connected to the second ends of the in-plane wiring lines 25A and 25B”] defined by a first set of layers and a semiconductor device [“Referring to FIG. 2A, the ESD protection device 101 includes a semiconductor substrate 20 including input/output electrodes 21A and 21B, and a rewiring layer 30 provided on the top surface of the semiconductor substrate 20. Although not illustrated in FIG. 2A, an ESD protection circuit is provided in the top layer of the semiconductor substrate 20, and the input/output electrodes 21A and 21B are connected to the ESD protection circuit”] defined by a second set of layers, the bond pad providing a terminal [“Referring to FIG. 2B, two rectangular or substantially rectangular terminal electrodes 28A and 28B are located on the upper surface of the ESD protection device 101”] of the DSN semiconductor device package;
wherein the first set of layers comprises a first metallization [27 and 28 see “terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] layer exposing the bond pad to the outside of the DSN semiconductor device package;
wherein the first metallization layer comprises a first area [see Fig. 2B] in a plane of the first metallization layer, wherein the first area comprises a rectangularly [see Fig. 2B] shaped area, and wherein the first area comprises [“terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] a first metal;
wherein the first set of layers further comprises a second metallization [24 and 25 see “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20, and the second ends are connected to first ends of the in-plane wiring lines 25A and 25B extending in an in-plane direction”] layer conductively connected to the first metallization layer, wherein the second metallization layer comprises a second area [“pads P27 of the in-plane wiring lines to which the post-shaped electrodes 27A and 27B are connected”] in a plane of the second metallization layer, wherein the second area is positioned below the first area, and wherein the second area comprises [“Under bump metal (UBM) layers made of Ti and Cu are provided in and around these openings, and these UBM layers define the interlayer wiring lines 24A and 24B. On the top surfaces of the UBM layers, the in-plane wiring lines 25A and 25B made of Cu are provided”] a second metal; and
wherein the second metallization layer further comprises a third area [see Fig. 4A, Fig. 4B, see the part of 24, 25 extending from the pads P27 to above “input/output electrodes 21A and 21B”] in the plane of the second metallization layer,
wherein the third area extends from one side of the second area towards [see the portion of 24, 25 extending from the pads P27 to above “input/output electrodes 21A and 21B” see Fig. 4A, Fig. 4B, “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20”] a location above the semiconductor device input/output electrodes,
wherein the third area where the third area touches the one side of the second area has a width [see Fig. 4A, Fig. 4B, see the part of 24, 25 extending from the pads P27 is a smaller width that the pads P27] that is smaller than a length of the one side of the second area, and wherein the third area [see Fig. 4A, Fig. 4B, see the same 24, 25 extend from over “input/output electrodes 21A and 21B” to form pads P27 ] comprises the second metal,
but does not state “wherein the third area is rectangularly shaped and extends from one side of the second area towards a location above the semiconductor device”
See Akiba Fig. 3, Fig. 32 see “rewiring layer 7 for electrically coupling the pads 2 and the bump electrodes 9” “the pad 2 having the probe region (first region) 10A on the periphery side of the device formation region and the coupling region (second region) 10B which is adjacent to the probe region 10A and is on the center side of the device formation region relative to the probe region 10A is formed over the semiconductor wafer 1W while electrically coupling it to an interconnect configuring the semiconductor circuit (S30)” “pad 2 is in a rectangular shape having a long side extending from the periphery side to the center side of the device formation region (which will be the semiconductor chip 1C later) as illustrated in FIG. 2 and FIG. 4” see Fig. 32 see paragraph 0156 “an opening portion 12 having a square planar shape which is similar to the opening portion 12 described in Embodiment 1 referring to FIG. 4 and formed on the pad 2 to couple with the rewiring layer; and a rectangular opening portion 12A smaller than the square opening portion 12” “thereby using the coupling via the opening portion 12 for, for example, power (large current), analogue, or low-resistance coupling and the coupling via the opening portion 12A for high-resistance coupling”, see that the opening 12 is square and within a rectangular rewiring layer 7 .
See in Kato Fig. 4A, Fig. 4B see that pads P27 are very large and Kato is concerned about the size because they are responsible for capacitance, see that by the teaching of Akiba the part of 24, 25 extending from the pads P27 to above “input/output electrodes 21A and 21B” can be wider and rectangular and having wiring lines 24A and 24B entirely within the rectangular region to give good current conduction.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kato to include “wherein the third area is rectangularly shaped and extends from one side of the second area towards a location above the semiconductor device”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain best conduction from input/output electrodes 21A and 21B to the post-shaped electrodes 27A and 27B in the device of Kato and to use the space under and in between (in plan view) input/output electrodes 21A and 21B for the semiconductor devices .
In regard to claim 3 Kato and Akiba as combined teaches wherein the second area is fully covered by the first area [see Kato Fig. 4B], and wherein the third area is not [see Kato Fig. 4B] covered by the first area.
In regard to claim 4 Kato and Akiba as combined teaches wherein the first set of layers further comprises a third metallization layer [see 24 is also in the via “interlayer wiring lines 24A and 24B whose first ends are respectively connected to the input/output electrodes 21A and 21B, the in-plane wiring lines 25A and 25B whose first ends are respectively connected to the second ends of the interlayer wiring lines 24A and 24B, and the post-shaped electrodes 27A and 27B respectively connected to the second ends of the in-plane wiring lines 25A and 25B”] providing a via between the third area of the second metallization layer and a device pad of the semiconductor device, and wherein the via comprises [see it is the same 24 that extends from 21 to under 27] the second metal.
In regard to claim 6 Kato and Akiba as combined teaches wherein the second metal [see Kato “Under bump metal (UBM) layers made of Ti and Cu are provided in and around these openings, and these UBM layers define the interlayer wiring lines 24A and 24B. On the top surfaces of the UBM layers, the in-plane wiring lines 25A and 25B made of Cu are provided”] is copper (Cu).
In regard to claim 7 Kato and Akiba as combined does not state wherein the width of the third area is about one third of the length of the one side of the second area.
However see combination when the width of the third area increases the series resistance reduces, thus it is a result effective variable.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the width of the third area is about one third of the length of the one side of the second area ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 8 Kato and Akiba as combined does not state wherein the third area extends from the middle of the one side of the second area to above an edge of the semiconductor device.
See Kato Fig. 4A, Fig. 4B are depicted as vertically symmetric and the Examiner notes that the pads P27 are passing current so if there is asymmetry, then a portion of pads P27 will get less current than the vertically opposite side of the pad thus reducing conduction, so there is no incentive for asymmetry i.e. the symmetry is a result effective variable.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kato to include wherein the third area extends from the middle of the one side of the second area to above an edge of the semiconductor device.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use symmetry to maximize current conduction in the input/output.
Also, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the third area extends from the middle of the one side of the second area to above an edge of the semiconductor device”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 9 Kato and Akiba as combined teaches wherein the second metallization layer is directly [See Kato Fig. 4A, Fig. 4B see 24 and 25 and 27 and 28 see “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20, and the second ends are connected to first ends of the in-plane wiring lines 25A and 25B extending in an in-plane direction” “terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] below the first metallization layer.
In regard to claim 10 Kato and Akiba as combined teaches wherein the first set of layers comprises one or more further metallization layers between and [see Kato Fig. 4A, Fig. 4B see 24 and 25 and 27 and 28 see “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20, and the second ends are connected to first ends of the in-plane wiring lines 25A and 25B extending in an in-plane direction” “terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] conductively connecting the first metallization layer and the second metallization layer.
In regard to claim 11 Kato and Akiba as combined teaches further comprising two similarly shaped bond pads each formed as the bond pad [see Kato Fig. 2A, Fig. 2B, Fig. 3, Fig. 4A, Fig. 4B], wherein the bond pads are positioned in a mirrored [see Kato Fig. 2A, Fig. 2B, Fig. 3, Fig. 4A, Fig. 4B] orientation, so that the third area of each of the bond pads extends towards [see Kato Fig. 2A, Fig. 2B, Fig. 3, Fig. 4A, Fig. 4B, see combination claim 1] the location above the semiconductor device.
In regard to claim 12 Kato and Akiba as combined teaches wherein the semiconductor device package is a [see claim 1 combination “to obtain best conduction from input/output electrodes 21A and 21B to the post-shaped electrodes 27A and 27B in the device of Kato and to use the space under and in between (in plan view) input/output electrodes 21A and 21B for the semiconductor devices” see all the structural limitations are shown by the prior art combination ] dual silicone no-lead (DSN) semiconductor device package.
In regard to claim 17 Kato and Akiba as combined teaches wherein the first metallization layer further comprises a fourth area [see Kato Fig. 4A, Fig. 4B see “The post-shaped electrodes 27A and 27B each preferably are pillar-shaped in an organic insulating film 26”] between the first areas of the bond pads, and wherein the fourth area comprises [“organic insulating film 26”] a protective, non-conductive coating.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato and Akiba as combined and further in view of Kim et al. (US 20220352059 A1) hereafter referred to as Kim
In regard to claim 5 Kato and Akiba as combined teaches wherein the first metal [see Kato “terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] is selected from the group consisting of: tin (Sn); nickel/gold (NiAu); and nickel/palladium/gold (NiPdAu) but does not actually state that it is an alloy.
See Kato Fig. 7A, Fig. 8A “terminal electrodes (29A, 29D, and the like) preferably defined by solder bumps are located on terminal electrodes (28A, 28D, and the like)”.
However alloy is common in the art, see Kim teaches see paragraph 0229 “In this case, on the surface of the external pad 150 in contact with the external connection terminal 160, a wetting layer 155 (a cover layer or a preliminary metal layer, etc.) having excellent wettability may be formed so that the external connection terminal 160 is well adhered” “In this case, the wetting layer 155 may be formed of gold (Au) or an alloy component including gold by an electroless gold plating method. Alternatively, the wetting layer 155 may be Au, Pd, Ni, Cu, Sn, or an alloy thereof” “For example, the external connection terminal 160 may include a solder bump”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kato to include that it is an alloy
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that such alloys are known in the art for good wettability and have adjustable properties based on the proportion of metals in the alloy.
Claim(s) 18, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (US 20130168837 A1) hereafter referred to as Kato in view of Akiba et al. (US 20170229359 A1) hereafter referred to as Akiba
In regard to claim 18 Kato teaches a method of manufacturing a dual silicone no-lead, DSN semiconductor device [see Fig. 2A, Fig. 2B “FIG. 4A illustrates the dimensions of the post-shaped electrodes and the pads of the in-plane wiring lines of the ESD protection device 101 illustrated in FIG. 2A. FIG. 4B illustrates a comparative example” “the shape of the post-shaped electrodes in a sectional view taken along a plane parallel or substantially parallel with the direction (thickness direction) in which the post-shaped electrodes extend is that of a trapezoid” see that the comparison is the trapezoid ] package comprising a bond pad [“terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film” “interlayer wiring lines 24A and 24B whose first ends are respectively connected to the input/output electrodes 21A and 21B, the in-plane wiring lines 25A and 25B whose first ends are respectively connected to the second ends of the interlayer wiring lines 24A and 24B, and the post-shaped electrodes 27A and 27B respectively connected to the second ends of the in-plane wiring lines 25A and 25B”] defined by a first set of layers and a semiconductor device [“Referring to FIG. 2A, the ESD protection device 101 includes a semiconductor substrate 20 including input/output electrodes 21A and 21B, and a rewiring layer 30 provided on the top surface of the semiconductor substrate 20. Although not illustrated in FIG. 2A, an ESD protection circuit is provided in the top layer of the semiconductor substrate 20, and the input/output electrodes 21A and 21B are connected to the ESD protection circuit”] defined by a second set of layers, the bond pad providing a terminal [“Referring to FIG. 2B, two rectangular or substantially rectangular terminal electrodes 28A and 28B are located on the upper surface of the ESD protection device 101”] of the DSN semiconductor device package, the method comprising the steps of:
creating a second metallization [24 and 25 see “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20, and the second ends are connected to first ends of the in-plane wiring lines 25A and 25B extending in an in-plane direction”] layer of the first set of layers; and
creating a first metallization [27 and 28 see “terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] of the first set of layers;
wherein the first set of layers comprises a first metallization layer [27 and 28 see “terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] exposing the bond pad to the outside of the DSN semiconductor device package;
wherein the first metallization layer comprises a first area [see Fig. 2B] in a plane of the first metallization layer, wherein the first area comprises a rectangularly [see Fig. 2B] shaped area, and wherein the first area comprises [“terminal electrodes 28A and 28B side surfaces of the post-shaped electrodes 27A and 27B, i.e., the surfaces to be connected to the motherboard, such as a printed circuit board, are provided with a plated metal film, such as a Ni/Au film or a Ni/Sn film”] a first metal;
wherein the first set of layers further comprises a second metallization [24 and 25 see “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20, and the second ends are connected to first ends of the in-plane wiring lines 25A and 25B extending in an in-plane direction”] layer conductively connected to the first metallization layer, wherein the second metallization layer comprises a second area [“pads P27 of the in-plane wiring lines to which the post-shaped electrodes 27A and 27B are connected”] in a plane of the second metallization layer, wherein the second area is positioned below the first area, and wherein the second area comprises [“Under bump metal (UBM) layers made of Ti and Cu are provided in and around these openings, and these UBM layers define the interlayer wiring lines 24A and 24B. On the top surfaces of the UBM layers, the in-plane wiring lines 25A and 25B made of Cu are provided”] a second metal; and
wherein the second metallization layer further comprises a third area [see Fig. 4A, Fig. 4B, see the part of 24, 25 extending from the pads P27 to above “input/output electrodes 21A and 21B”] in the plane of the second metallization layer,
wherein the third area extends from one side of the second area towards [see the portion of 24, 25 extending from the pads P27 to above “input/output electrodes 21A and 21B” see Fig. 4A, Fig. 4B, “First ends of the interlayer wiring lines 24A and 24B arranged in the thickness direction are connected to the input/output electrodes 21A and 21B arranged on the top surface of the semiconductor substrate 20”] a location above the semiconductor device input/output electrodes,
wherein the third area where the third area touches the one side of the second area has a width [see Fig. 4A, Fig. 4B, see the part of 24, 25 extending from the pads P27 is a smaller width that the pads P27] that is smaller than a length of the one side of the second area, and wherein the third area [see Fig. 4A, Fig. 4B, see the same 24, 25 extend from over “input/output electrodes 21A and 21B” to form pads P27 ] comprises the second metal.
but does not state “wherein the third area is rectangularly shaped and extends from one side of the second area towards a location above the semiconductor device”
See Akiba Fig. 3, Fig. 32 see “rewiring layer 7 for electrically coupling the pads 2 and the bump electrodes 9” “the pad 2 having the probe region (first region) 10A on the periphery side of the device formation region and the coupling region (second region) 10B which is adjacent to the probe region 10A and is on the center side of the device formation region relative to the probe region 10A is formed over the semiconductor wafer 1W while electrically coupling it to an interconnect configuring the semiconductor circuit (S30)” “pad 2 is in a rectangular shape having a long side extending from the periphery side to the center side of the device formation region (which will be the semiconductor chip 1C later) as illustrated in FIG. 2 and FIG. 4” see Fig. 32 see paragraph 0156 “an opening portion 12 having a square planar shape which is similar to the opening portion 12 described in Embodiment 1 referring to FIG. 4 and formed on the pad 2 to couple with the rewiring layer; and a rectangular opening portion 12A smaller than the square opening portion 12” “thereby using the coupling via the opening portion 12 for, for example, power (large current), analogue, or low-resistance coupling and the coupling via the opening portion 12A for high-resistance coupling”, see that the opening 12 is square and within a rectangular rewiring layer 7 .
See in Kato Fig. 4A, Fig. 4B see that pads P27 are very large and Kato is concerned about the size because they are responsible for capacitance, see that by the teaching of Akiba the part of 24, 25 extending from the pads P27 to above “input/output electrodes 21A and 21B” can be wider and rectangular and having wiring lines 24A and 24B entirely within the rectangular region to give good current conduction.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kato to include “wherein the third area is rectangularly shaped and extends from one side of the second area towards a location above the semiconductor device”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain best conduction from input/output electrodes 21A and 21B to the post-shaped electrodes 27A and 27B in the device of Kato and to use the space under and in between (in plan view) input/output electrodes 21A and 21B for the semiconductor devices .
In regard to claim 19 Kato and Akiba as combined teaches further comprising the steps of, creating two similarly shaped bond pads [see Fig. 2A, Fig. 2B “FIG. 4A illustrates the dimensions of the post-shaped electrodes and the pads of the in-plane wiring lines of the ESD protection device 101 illustrated in FIG. 2A. FIG. 4B illustrates a comparative example” “the shape of the post-shaped electrodes in a sectional view taken along a plane parallel or substantially parallel with the direction (thickness direction) in which the post-shaped electrodes extend is that of a trapezoid” see that the comparison is the trapezoid] each formed as the bond pad, wherein the bond pads are positioned in a mirrored [see Fig. 2A, Fig. 2B , FIG. 4A, FIG. 4B ] orientation, and wherein the third area of each of the bond pads extends towards the location above the semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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