DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 February 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-7, 10-16, 19 and 25-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-7,10 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Huangfu et al. (US 2023/0042966) in view of Kang et al. (KR 20210116793 A) and further in view of Sano et al. (US 2022/0123268).
Regarding claim 1, Huangfu et al. disclose a display apparatus (Figure 1 and 16-17) comprising:
a gate drive circuit configured to generate a light-emitting signal (Figure 16/17, 20/30 is a gate drive circuit. See paragraph [0539].);
a pixel circuit (Figure 2B) comprising a driving transistor (Figure 2B, M12 is a driving transistor.), a first light-emitting element (Figure 2B, L is a first light-emitting element), a third transistor configured to operate in response to the light-emitting signal (Figure 2B, M14 is a third transistor that operats in response to EMn.), a capacitor connected to a gate electrode of the driving transistor (Figure 2B, C4 is a capacitor connected to a gate of M12.) and including a first electrode and a second electrode (Figure 2B, C4 has a first and second electrode [at N1 and N2].), and a sixth transistor connected between a data line and the first electrode of the capacitor (Figure 2B, M12 is a sixth transistor connected between Data and the first electrode of C4 at N1.);
wherein during an initialization period (Figure 3, P1 is an initialization period.) of the pixel circuit, a reference voltage is applied to the first electrode of the capacitor (Figure 2, Vref1 is applied to N1, see paragraph [0123].) and an initialization voltage is applied to the second electrode of the capacitor while the reference voltage is applied to the first electrode of the capacitor (Figure 2, Vinit is applied to N2, see paragraph [0124].), and
wherein the sixth transistor includes a source electrode directly connected to the data line (Figure 2B, the source of M13 is directly connected to Data.), a drain electrode directly connected to the first electrode of the capacitor (Figure 2B, the drain of M13 is directly connected to the first electrode of C4 at N1.), and a gate electrode connected to a first scan signal line configured to transmit a first scan signal (Figure 2B, the gate of M13 is connected to Sn/S2 [first scan signal line configured to transmit a first scan signal.].), and
wherein the sixth transistor applies a data voltage to the first electrode of the capacitor in response to the first scan signal (Figure 2B and paragraph [0113].).
Huangfu et al. fail to teach the pixel circuit comprising a first transistor configured to receive a first control signal, a second transistor configured to receive a second control signal, the first light-emitting element connected to the first transistor, a second light-emitting element connected to the second transistor, the third transistor connected between the driving transistor, the first transistor, and the second transistor.
Kang et al. disclose a pixel circuit (Figure 15) comprising a driving transistor (Figure 15, T3 [driving transistor].), a first transistor configured to receive a first control signal (Figure 15, T1 [first transistor] receives CLi.), a second transistor configured to receive a second control signal (Figure 15, T2 receives CCLi.), a first light-emitting element connected to the first transistor (Figure 15, LD1 [first light-emitting element] is connected to T1.), a second light-emitting element connected to the second transistor (Figure 15, LD2 [a second light-emitting element] is connected to T2.), a third transistor connected between the driving transistor, the first transistor, and the second transistor and configured to operate in response to the light-emitting signal (Figure 15, T8 [third transistor] is connected between T3, LD1 and LD2.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the plural light-emitting elements teaching of Kang et al. in the display apparatus taught by Huangfu et al. so as to have first and second light-emitting elements and associated transistors in the pixel circuit. The motivation to combine would have been in order to use multiple ultra-small light emitting devices instead of one larger LED, resulting in higher, more uniform light output with better heat dissipation.
Huangfu et al. and Kang et al. fail to explicitly teach:
a first lens on the first light-emitting element; and
a second lens on the second light-emitting element.
Sano et al. disclose a display apparatus comprising:
a first lens on a first light-emitting element (Figure 1B shows a first lens of 113 on a first light-emitting element. See paragraph [0047].); and
a second lens on a second light-emitting element (Figure 1B shows a second lens of 113 on a second light-emitting element. See paragraph [0047].).
See marked up copy of Figure 1B of Sano et al. below:
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Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the lens teachings of Sano et al. in the display apparatus taught by the combination of Huangfu et al. and Kang et al. The motivation to combine would have been in order to improve the light extraction efficiency of the organic light-emitting device (See paragraph [0047] of Sano et al.).
Regarding claim 4, Huangfu et al., Kang et al. and Sano et al. disclose the display apparatus of claim 1, wherein the second electrode of the capacitor is connected to the gate electrode of the driving transistor (Huangfu et al.: Figure 2B).
Regarding claim 5, Huangfu et al., Kang et al. and Sano et al. disclose the display apparatus of claim 1, wherein in a sampling period of the pixel circuit, a data voltage is applied to the first electrode of the capacitor (Kang et al.: See page 44 of the provided document, in the discussion of Figure 15, lines 10-13, it is stated “The fourth transistor T4 may be turned on by the scan signal to transmit the data signal from the data line DLj to the first electrode of the third transistor T3.” Further, lines 14-18, recite “The fifth transistor T5 may be connected between the first node N1 and the second node N2 . A gate electrode of the fifth transistor T5 may be connected to the scan line SLi. When the fifth transistor T5 is turned on, the third transistor T3 may be diode-connected. A voltage corresponding to a difference between the data signal and the threshold voltage of the third transistor T3 may be supplied to the first node N2.” Thus meaning that T4, through T3 and T5, is connected to N1 and a data voltage is applied to the first electrode of the capacitor.), and the initialization voltage is applied to the first light-emitting element and the second light-emitting element (Kang et al.: See page 44 of the provided document, in the discussion of Figure 15, it is noted that the operation of T1 and T2 is the same as in Figure 3. On page 34 of the provided document, in the discussion of Figure 3, lines 30-31, it is stated that “In an embodiment, when the first transistor T1 is turned on, the voltage of the initialization power source Vint may be supplied….” Thus, since in Figure 15 T2 is connected to LD1, which is then connected to LD2, then when T1 is turned on Vint is applied to the first light-emitting element and the second light-emitting element.).
Regarding claim 6, Huangfu et al., Kang et al. and Sano et al. disclose the display apparatus of claim 1, wherein the pixel circuit further comprises:
a fourth-first transistor (Kang et al.: Figure 15, T6) applied with the initialization voltage (Kang et al.: Figure 15 shows T6 is applied with Vint.), the fourth-first transistor connected to the first light-emitting element and an electrode of the first transistor (Kang et al.: Figure 15 shows T6 is connected to LD1 and an electrode of T1.); and
a fourth-second transistor (Kang et al.: Figure 15, T5) applied with the initialization voltage (Kang et al.: Figure 15 shows T5 is applied with Vint [through T6].), the fourth-second transistor connected to the second light-emitting element and an electrode of the second transistor (Kang et al.: Figure 15 shows T5 is connected to LD2 and an electrode of T2 through T8 and LD1.).
Regarding claim 7, Huangfu et al., Kang et al. and Sano et al. disclose the display apparatus of claim 6, wherein the pixel circuit further comprises:
a fifth transistor (Huangfu et al.: Figure 2B, M10) connected to the first electrode of the capacitor (Huangfu et al.: Figure 2B, M10 is connected to the first electrode of C4.), the fifth transistor applied with the reference voltage (Huangfu et al.: Figure 2B, M10 is applied with Vref1.).
Regarding claim 10, this claim is rejected under the same rationale as claim 1, and furthermore Sano et al. also disclose wherein the first lens is on the first light-emitting element but not the second light-emitting element, and the second lens is on the second light-emitting element but not the first light-emitting element (Figure 1B. See, for example, the marked-up copy of Figure 1B in the rejection of claim 1 above.).
Regarding claim 13, this claim is rejected under the same rationale as claim 4.
Regarding claim 14, this claim is rejected under the same rationale as claim 5.
Regarding claim 15, this claim is rejected under the same rationale as claim 6.
Regarding claim 16, this claim is rejected under the same rationale as claim 7.
Claims 2-3 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Huangfu et al. (US 2023/0042966) in view of Kang et al. (KR 20210116793 A) and further in view of Sano et al. (US 2022/0123268) and Kim et al. (US 2023/0320134).
Regarding claim 2, Huangfu et al., Kang et al. and Sano et al. disclose the display apparatus of claim 1.
Huangfu et al., Kang et al. and Sano et al. fail to teach wherein the initialization voltage is applied to the second electrode of the capacitor through the first transistor and the third transistor while the first control signal is applied to the first transistor without the second control signal being applied to the second transistor.
Kim et al. disclose wherein an initialization voltage is applied to a second electrode of a capacitor through a first transistor and a third transistor while a first control signal is applied to the first transistor without a second control signal being applied to the second transistor (Figure 2, an initialization voltage VAINT is applied to a second electrode of a capacitor CST through a first transistor T6 and a third transistor T3 while a first control signal EM1 is applied to T6 without a second control signal EM2 being applied to a second transistor T9.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the transistor teachings of Kim et al. to provide for individual application of the initialization voltage to the first and second light-emitting elements in the display apparatus taught by the combination of Huangfu et al., Kang et al. and Sano et al. The motivation to combine would have been in order display an image in a wide viewing angle or a narrow viewing angle in which a viewing angle in a specific direction is limited based on an input mode. Accordingly, user's privacy may be protected if desired (See paragraph [0111] of Kim et al.).
Regarding claim 3, please refer to the rejection of claim 2, and furthermore Kim et al. also disclose wherein the initialization voltage is applied to the second electrode of the capacitor through the second transistor and the third transistor while the second control signal is applied to the second transistor without the first control signal being applied to the first transistor (Figure 2, an initialization voltage VAINT is applied to a second electrode of a capacitor CST through the second transistor T9 and the third transistor T3 while a second control signal EM2 is applied to T9 without a second control signal EM1 being applied to the first transistor T6.).
Regarding claim 11, this claim is rejected under the same rationale as claim 2.
Regarding claim 12, this claim is rejected under the same rationale as claim 3.
Claims 19 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Huangfu et al. (US 2023/0042966) in view of Kang et al. (KR 20210116793 A) and further in view of Kim et al. (US 2023/0320134).
Regarding claim 19, please refer to the rejection of claim 1 with respect to Huangfu et al. and Kang et al., and furthermore Huangfu et al. and Kang et al. also disclose where the claimed driving transistor includes a driving transistor including a first electrode of the driving transistor, a second electrode of the driving transistor, and a gate electrode of the driving transistor (Huangfu et al.: Figure 2B, M12 has a first electrode, second electrode and a gate, and Kang et al.: Figure 15, T3 has a first electrode, second electrode and a gate.), the claimed emission transistor is the same as the claimed third transistor of claim 1, which has a first electrode of the emission transistor that is connected to the second electrode of the driving transistor (Huangfu et al.: Figure 2B, M14 has a first electrode connected to the second electrode of M12, and Kang et al.: Figure 15, first electrode of T8 is connected to second electrode of T3.), a second electrode of the emission transistor (Huangfu et al.: Figure 2B, M14 has a second electrode, and Kang et al.: Figure 15, T8 has a second electrode.), and a gate electrode configured to receive a light-emitting signal (Huangfu et al.: Figure 2B, M14 has a gate electrode that receives EMn, and Kang et al.: Figure 15, T8 has a gate that receives ELi.), the claimed first mode transistor is the first transistor of claim 1, including a first electrode of the first mode transistor that is connected to the second electrode of the emission transistor (Kang et al.: Figure 15, T1 has a first electrode connected to the second electrode of T8.), a second electrode of the first mode transistor (Kang et al.: Figure 15, T1 has a second electrode.), and a gate electrode of the first mode transistor that is configured to receive a first control signal (Kang et al.: Figure 15, T1 has a gate that receives a first control signal CLi.), the claimed second mode transistor is the second transistor of claim 1, including a first electrode of the second mode transistor that is connected to the second electrode of the emission transistor and the first electrode of the first mode transistor (Kang et al.: Figure 15, T2 has a first electrode connected to the second electrode of T8 through LD1 and the first electrode of T1 through LD1.), a second electrode of the second mode transistor (Kang et al.: Figure 15, T2 has a second electrode.), and a gate electrode of the second mode transistor that is configured to receive a second control signal (Kang et al.: Figure 15, T2 has a gate that receives a second control signal CCLi.), the first light-emitting element of claim 1 is a first light emitting diode (Kang et al.: Figure 15, LD1) connected to the second electrode of the first mode transistor (Kang et al.: Figure 15, LD1 is connected to the second electrode of T1 through T1.), the first light emitting diode configured to emit light during a first mode (Kang et al.: Figure 15, LD1 emits light in a “first mode.”), the second light-emitting element of claim 1 is a second light emitting diode connected to the second electrode of the second mode transistor (Kang et al.: Figure 15, LD2 is connected to the second electrode of T2 .), the second light emitting diode configured to emit light during a second mode (Kang et al.: Figure 15, LD2 emits light in a “second mode.”).
Huangfu et al. and Kang et al. fail to explicitly teach:
a gate electrode of the first mode transistor that is configured to receive a first control signal responsive to a first mode of the pixel circuit associated with a first viewing angle; and
a gate electrode of the second mode transistor that is configured to receive a second control signal responsive to a second mode of the pixel circuit associated with a second viewing angle that is different from the first viewing angle;
wherein there is an initialization period of the pixel circuit in each of the first mode and the second mode.
Kim et al. disclose a pixel circuit comprising a first mode transistor (Figure 2, T6) and a second mode transistor (Figure 2, T9);
a gate electrode of the first mode transistor that is configured to receive a first control signal responsive to a first mode of the pixel circuit associated with a first viewing angle (Figure 2, T9 receives EM1 for a first mode corresponding to a first viewing angle. See paragraph [0109].); and
a gate electrode of the second mode transistor that is configured to receive a second control signal responsive to a second mode of the pixel circuit associated with a second viewing angle that is different from the first viewing angle (Figure 2, T9 receives EM1 for a first mode corresponding to a first viewing angle. See paragraph [0110].);
wherein there is an initialization period of the pixel circuit in each of the first mode and the second mode (In each of the viewing modes, GB is applied for application of VAINT [initialization voltage].).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the transistor teachings of Kim et al. to provide for individual application of the initialization voltage to the first and second light-emitting elements in the display apparatus taught by the combination of Huangfu et al. and Kang et al. The motivation to combine would have been in order to create different display modes to display an image in a wide viewing angle or a narrow viewing angle in which a viewing angle in a specific direction is limited based on an input mode. Accordingly, user's privacy may be protected if desired (See paragraph [0111] of Kim et al.).
Regarding claim 26, Huangfu et al., Kang et al. and Kim et al. disclose the pixel circuit of claim 19, wherein the second viewing angle is wider than the first viewing angle (Kim et al.: Paragraphs [0109]-[0111].).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Huangfu et al. (US 2023/0042966) in view of Kang et al. (KR 20210116793 A) and further in view of Kim et al. (US 2023/0320134) and Oon et al. (US 7,284,871).
Regarding claim 25, Huangfu et al., Kang et al. and Kim et al. disclose the pixel circuit of claim 19.
Huangfu et al., Kang et al. and Kim et al. fail to teach a first lens having a first shape is disposed over the first light emitting diode and a second lens having a second shape that is different from the first shape in a plan view of the pixel circuit is disposed over the second light emitting diode.
Oon et al. disclose wherein:
a first lens having a first shape is disposed over a first light emitting diode and a second lens having a second shape that is different from the first shape in a plan view of the pixel circuit is disposed over a second light emitting diode (Figure 2 and column 2, lines 57-67. There is a first lens 214 and a second lens 212 located over LEDs 204 and 202, respectively, which are different shapes.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the lens teachings of Oon et al. and apply them over the LEDs in the pixel circuit taught by the combination of Huangfu et al., Kang et al. and Kim et al. The motivation to combine would have been in order to further help guide the light for the different viewing angle modes the facilitating the privacy mode of the device.
Allowable Subject Matter
Claims 8-9, 17-18 and 20-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (Further, for claims 8-9, the 112(b) rejection of claim 1 would also need to be overcome.).
The following is a statement of reasons for the indication of allowable subject matter:
The primary reasons for indicating allowable subject matter in claim 8 is the inclusion of the limitations reciting “wherein the gate drive circuit is further configured to generate a first scan signal and a second scan signal…and the fourth-first transistor and the fourth-second transistor operate in response to the second scan signal” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Kang et al. disclose of a “fourth-first transistor” T6 and a “fourth-second transistor” T5 (See the rejection of claim 6). Kang et al. only disclose a first scan signal SLi being applied to the circuit of Figure 15. Thus, the prior art, alone or in combination, fails to teach the specifically claimed transistor circuit configuration along with “the fourth-first transistor and the fourth-second transistor operate in response to the second scan signal” of claim 8.
Claim 9 is objected to due to this dependency from claim 8.
Claim 17 is objected to for the same reasons as claim 8 above.
Claim 18 is objected to due to this dependency from claim 17.
The primary reasons for indicating allowable subject matter in claim 20 is the inclusion of the limitations reciting “…a reference transistor including a first electrode of the reference transistor that is connected to the second electrode of the data transistor and the first capacitor electrode, and a gate electrode of the reference transistor that is connected gate electrode of the emission transistor, the gate electrode of the reference transistor configured to receive the light-emitting signal; a first initialization transistor…a gate electrode of the first initialization transistor that is configured to receive a second scan signal; a second initialization transistor…a gate electrode of the second initialization transistor that is connected to the gate electrode of the first initialization transistor and configured to receive the second scan signal; and a connection transistor…a gate electrode of the connection transistor that is connected to the gate electrode of the first initialization transistor and the gate electrode of the second initialization transistor, the gate electrode of the connection transistor configured to receive the second scan signal” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Kang et al. disclose of a data transistor (Figure 15, T4) including a first electrode of the data transistor that is connected to a data line that applies a data voltage to the first electrode (Figure 15, a first electrode of T4 is connected to data line DLj that applied a data voltage.), a second electrode of the data transistor that is connected to the first capacitor electrode (Figure 15, a second electrode of T4 is connected to a first electrode of Cst through T7.), and a gate electrode of the data transistor that is configured to receive a first scan signal (Figure 15, a gate of T4 receives first scan signal SLi.). However, Kang et al. and the prior art, alone or in combination, fail to explicitly teach the claimed circuit configuration as claimed in claim 20 and highlighted above.
Claims 21-24 are objected to due to their dependency from claim 20.
Conclusion
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/STEPHEN G SHERMAN/Primary Examiner, Art Unit 2621
23 March 2026