DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/31/2025 have been fully considered but they are not persuasive.
The Applicant contends that prior art fails to teach “modifying transceiver settings of a transceiver of the memory controller for the communication channel based on the determined characteristic.
The Examiner disagrees and asserts that the characteristics mentioned in Chen (like Vt distributions and RBER) are physical properties of the memory cells and the data path to the controller, any adjustment to the controller's transceiver must, by definition, be an adjustment for that specific communication channel. The While Chen uses the term "read/write communication channel," a Person of Ordinary Skill in the Art (PHOSITA) would understand this to inherently include the physical interface between the SSD Memory Controller (100) and the Flash Memory (199). As noted in Paragraphs [0156]-[0157], Chen identifies channel characteristics such as: * Raw Bit Error Rate (RBER) * Signal-to-Noise Ratio (SNR) * Threshold Voltage (V_t) Distributions These characteristics are specific to the physical state of the memory cells and the integrity of the signal as it travels from those cells to the controller. Therefore, in this case, the "channel" being measured is the link between the memory and the controller. Chen explicitly teaches "modifying/adjusting transceiver settings" at the memory controller based on these characteristics (Step 707 in Figure 8 of Chen). In the context of high-speed memory interfaces, "transceiver settings" typically refer to parameters such as: Drive Strength - the power used to transmit signals and Equalization (EQ) - Compensating for signal degradation over the physical trace; and, Termination (ODT) - Reducing signal reflection on the communication line. Because the Controller (100) is the entity performing the modification (Step 707) and the Characteristics (Paragraph [0157]) are derived from the state of the Flash Memory (199), Chen teaches modifying the transceiver settings for the specific communication channel existing between the controller and the memory. The adjustment is a direct response to the "channel conditions" encountered on that specific path. By monitoring the BER, Chen’s controller determines the "health" of the communication channel. If the BER is too high, the controller modifies the Transceiver Settings to bring the error rate back within acceptable limits for the link between the controller and memory.
Election/Restrictions
Claims 6-9 and 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/02/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 10-11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Zhengang et al. (US 20150127883 A1, hereafter referred to as Chen).
Rejection of claims 1 and 10-11:
Chen teaches A method, comprising: determining, at a memory controller, a characteristic of a read communication channel in a device comprising the memory controller and a memory, wherein the characteristic relates to logic levels of data written to or read from the memory over the communication channel (Figures 2A and 8-9; and, paragraphs [0147]-[0159] on pages 16-17 of Chen teach A method, comprising: determining, at a SSD memory controller 100, a characteristic/channel condition of a read/write communication channel in a device comprising the SSD memory controller 100 and a flash memory 199, wherein the characteristic relates to VREAD1, VREAD2 and VREAD3 logic levels of data written to or read from the memory over the read/write communication channel), and modifying transceiver settings of a transceiver of the memory controller for the communication channel based on the determined characteristic (Figures 2A and 8-9; and, paragraphs [0147]-[0159] on pages 16-17 of Chen; and, in particular, Step 707 in Figure 8 teach modifying/adjusting transceiver settings of a read/write transceiver of the SSD memory controller 100 for the read/write communication channel based on the determined characteristic/channel condition).
Chen teaches that the characteristic pertain to the memory channel including the transmission channel between the memory controller and a memory (the communication/transmission channel is the read/write communication/transmission channel which comprises the communication/transmission channel between the memory controller and a memory).
The Examiner would like to point out that the characteristics mentioned in Chen (like Vt distributions and RBER) are physical properties of the memory cells and the data path to the controller, any adjustment to the controller's transceiver must, by definition, be an adjustment for that specific communication channel. The While Chen uses the term "read/write communication channel," a Person of Ordinary Skill in the Art (PHOSITA) would understand this to inherently include the physical interface between the SSD Memory Controller (100) and the Flash Memory (199). As noted in Paragraphs [0156]-[0157], Chen identifies channel characteristics such as: * Raw Bit Error Rate (RBER) * Signal-to-Noise Ratio (SNR) * Threshold Voltage (V_t) Distributions These characteristics are specific to the physical state of the memory cells and the integrity of the signal as it travels from those cells to the controller. Therefore, in this case, the "channel" being measured is the link between the memory and the controller. Chen explicitly teaches "modifying/adjusting transceiver settings" at the memory controller based on these characteristics (Step 707 in Figure 8 of Chen). In the context of high-speed memory interfaces, "transceiver settings" typically refer to parameters such as: Drive Strength - the power used to transmit signals and Equalization (EQ) - Compensating for signal degradation over the physical trace; and, Termination (ODT) - Reducing signal reflection on the communication line. Because the Controller (100) is the entity performing the modification (Step 707) and the Characteristics (Paragraph [0157]) are derived from the state of the Flash Memory (199), Chen teaches modifying the transceiver settings for the specific communication channel existing between the controller and the memory. The adjustment is a direct response to the "channel conditions" encountered on that specific path. By monitoring the BER, Chen’s controller determines the "health" of the communication channel. If the BER is too high, the controller modifies the Transceiver Settings to bring the error rate back within acceptable limits for the link between the controller and memory.
Paragraphs [0156]-[0157] on page 17 of Chen teaches that the characteristics/channel conditions can be signal-to-noise ratio, a bit error rate, raw bit error rate, and the means and variances of the device threshold voltage distributions, which are channel conditions which also pertain to a communication channel between a memory controller and a memory. Hence, one of ordinary skill in the art would recognize that the teachings in Chen are also applicable to a smaller portion of the complete rate/write communication channel, such as, the communication channel between a memory controller and a memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen by including use of channel conditions pertaining to a communication channel between a memory controller and a memory. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of channel conditions pertaining to a communication channel between a memory controller and a memory would have eliminated the read performance penalty associated with adjusting read reference voltages (paragraph [0014] on page 2 of Chen).
Rejection of claims 4 and 14:
Step 707 in Figure 8 of Chen.
Claim(s) 2-3 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Zhengang et al. (US 20150127883 A1, hereafter referred to as Chen), Pyeon; Hong Beom et al. (US 20150095733 A1, hereafter referred to as Pyeon) and KALE; SALIL et al. (US 20190198069 A1, hereafter referred to as Kale).
Rejection of claims 2 and 12:
Paragraph [0031] on page 3 of Pyeon, in an analogous art clearly suggests, a pilot signal/test pattern stored inside a memory controller.
Paragraph [0079] on pages 9-10 in Kale, in an analogous art, clearly suggests reading a pilot signal/test pattern stored in memory.
Paragraph [0031] on page 3 of Pyeon, in an analogous art clearly suggests comparing a pilot signal/test pattern from a memory with an expected pilot signal/test pattern stored inside the memory controller.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Chen the teachings of Pyeon and Kale by including use of storing a pilot signal at the memory controller; causing the pilot signal to be written to the memory via a write operation; performing a read operation to retrieve a read pilot signal corresponding to the pilot signal from the memory; and comparing the read pilot signal to the stored pilot signal to determine the characteristic of the channel. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of storing a pilot signal at the memory controller; causing the pilot signal to be written to the memory via a write operation; performing a read operation to retrieve a read pilot signal corresponding to the pilot signal from the memory; and comparing the read pilot signal to the stored pilot signal to determine the characteristic of the channel would have provided the testing procedure for locating defects on the surface of a PCB before product release (paragraph [0004] on page 1 of Pyeon) and would have also provided a means for identifying errors associated with two or more data states in a plurality of data states stored in non-volatile memory (paragraph [0093] on page 12 of Kale).
Rejection of claim 3-13:
Paragraph [0079] on pages 9-10 in Kale teach the use of error correction information/characteristic data can be used as an indication of logic levels being inverted/erroneous.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen; Zhengang et al. (US 20150127883 A1, hereafter referred to as Chen) and BAO; Jingchao et al. (US 20210185515 A1, hereafter referred to as BAO).
Rejection of claims 5 and 15:
Paragraph [0080] on page 5 of BAO in an analogous art, teaches the use of the neural network for estimating channel conditions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Chen the teachings of BAO by including use of determining the characteristic of the channel using a neural network. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of determining the characteristic of the channel using a neural network would have provided increased reliability and improved signal through good (paragraph [0080] on page 5 of BAO).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20100046359 A1 is directed to A channel characteristic estimating method for estimating a channel characteristic of a wireless channel between a wireless terminal and a base station in a system in which communication is performed between the wireless terminal and the base station by orthogonal frequency division multiplex, comprising steps of: outputting a time alignment adjustment amount to the wireless terminal and performing, at a previously determined timing, a time alignment of adjusting a packet transmission timing of the wireless terminal; determining whether a timing is a timing to execute the time alignment or not; estimating, at the timing when the time alignment is performed, the channel characteristic of the wireless channel based on a pilot signal included in the received signal; and obtaining, at the timing when the time alignment is not performed, a first channel characteristic estimated value based on the pilot signal included in the received signal of a first operation timing, reading a second channel characteristic estimated value estimated at a second operation timing older than the first operation timing and stored, and estimating the channel characteristic of the wireless channel by forgetting averaging of the first channel characteristic estimated value and the second channel characteristic estimated value; and, is a good teaching reference.
US 20140010031 A1 is directed to A method for estimating channel characteristics of a nonvolatile memory device including a plurality of memory cells, comprising the steps of: calculating first threshold voltage distributions of the memory cells programmed according to input data, based on the input data and a physical structure of the memory cells; calculating second threshold voltage distributions of the memory cells based on output data and the physical structure of the memory cells; selecting a part of the memory cells using a mask, and analyzing an interference effect which adjacent memory cells among the selected memory cells have on a victim cell; and analyzing a noise effect which the adjacent memory cells have on the victim cell; and, is a good teaching reference.
US 20230063890 A1 is directed to An apparatus, comprising: a memory device; and logic coupled with the memory device and operable to cause the apparatus to: receive a first signal from a host device; transmit, to the host device, a second signal that comprises feedback for the first signal; receive, from the host device, a third signal indicative of a command based at least in part on transmitting the second signal; and disable one or more features of the memory device based at least in part on the command; and, is a good teaching reference.
US 20170206130 A1 is directed to A decoding method, adapted to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, the decoding method comprising: programming first data into at least one first physical unit among the physical units; reading the at least one first physical unit to obtain second data; obtaining a first threshold voltage distribution corresponding to a first bit value and a second threshold voltage distribution corresponding to a second bit value according to the first data and the second data, wherein the first bit value and the second bit value are different; calculating first channel reliability information corresponding to the at least one first physical unit according to the first threshold voltage distribution and the second threshold voltage distribution; and decoding third data stored in the at least one first physical unit according to the first channel reliability information; and, is a good teaching reference.
US 20200265903 A1 is directed to A memory system, comprising: a memory device including memory cells, each having a state corresponding to any one of an erased state or one of a plurality of programmed states; and a memory controller in communication with the memory device and configured to estimate an optimal read voltage associated with at least one of the erased state or one of the plurality of programmed states based on a threshold voltage distribution corresponding to at least one of the plurality of programmed states, wherein the memory controller comprises: a threshold voltage distribution checker configured to check a first threshold voltage distribution corresponding to a first programmed state, among the plurality of programmed states, and determine an average threshold voltage of the first threshold voltage distribution; and an optimal read voltage estimator configured to estimate a second optimal read voltage corresponding to a second side of the first threshold voltage distribution, based on the average threshold voltage of the first threshold voltage distribution and a first optimal read voltage corresponding to a first side of the first threshold voltage distribution; and, is a good teaching reference.
US 9214963 B1 is directed to A data storage system, comprising: a non-volatile memory array comprising a plurality of memory pages; and a controller coupled to the non-volatile memory array through a data channel, the controller being configured to: use a first set of low-density parity-check (LDPC) coding parameters to encode at a first code rate first data to be stored into the non-volatile memory array through the data channel, wherein the first set of LDPC coding parameters define a characteristic of a first matrix used to encode the first data; detect a change in a condition of the data channel; and in response to said detecting, use a second set of LDPC coding parameters to encode at a second code rate different from the first code rate second data to be stored into the non-volatile memory array through the data channel, wherein the second set of LDPC coding parameters define a characteristic of a second matrix used to encode the second data and are different from the first set of LDPC coding parameters; and, is a good teaching reference.
US 5541956 A is directed to an adaptive equalizer in an adaptive diversity equalizer both used for the purpose of reducing the performance degradation in a transmission system; and, is a good teaching reference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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/JOSEPH D TORRES/ Primary Examiner, Art Unit 2112