Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/01/2024, 02/04/2025 and 02/13/2025 are being considered by the examiner. The submission is in compliance with the provisions of 37 CFR 1.97.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-
AIA ), second paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which the inventor or a joint inventor, or
for pre-AIA the applicant regards as the invention. Claim 11 and 20 states “send and receive send queues are implemented as queues managed by software or as embedded queues in hardware” however it is unclear and ambiguous how
the send and receive queues are implemented by software or hardware.
Also, from MPEP:
2173.05(p) Claim Directed to Product-By- Process or Product and Process
A single claim which claims both an apparatus and the method steps of using the
apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second
paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303,
1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011). In Katz, a claim directed to "[a]
system with an interface means for providing automated voice messages…to certain of
said individual callers, wherein said certain of said individual callers digitally enter data"
was determined to be indefinite because the italicized claim limitation is not directed to
the system, but rather to actions of the individual callers, which creates confusion as to
when direct infringement occurs. Katz, 639 F.3d at 1318, 97 USPQ2d at 1749
(citing IPXL Holdings v. Amazon.com, Inc., 430 F.3d 1377, 1384, 77 USPQ2d 1140,
1145 (Fed. Cir. 2005), in which a system claim that recited "an input means" and
required a user to use the input means was found to be indefinite because it was
unclear "whether infringement … occurs when one creates a system that allows the
user [to use the input means], or whether infringement occurs when the user actually
uses the input means."); Ex parte Lyell, 17 USPQ2d 1548 (Bd. Pat. App. & Inter. 1990)
(claim directed to an automatic transmission workstand and the method of using it held
ambiguous and properly rejected under 35 U.S.C. 112, second paragraph).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SEN et al. (US 20210075633 A1) hereinafter SEN.
Regarding claim 1, SEN teaches A method for using staging buffers in broadcast or multicast operations comprising: (See Fig 19, paragraph [0082] and [0142], illustrates multicast operation on network fabric which may include copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer)
providing a memory tier that is accessed by a plurality of accelerators; (See Fig 16A and 16B, paragraph [0086] and [0123], illustrates memory node 1680 can include one or more tiers of memory and memory pool 1650 may include plurality of accelerators)
receiving data in a send queue of the memory tier; (See Fig 19, paragraph [0143], illustrates program network interface 1900 may include transmit or send queue 1906, receive queue 1908 for data transfer of memory 1910)
establishing, by a server fabric adapter (SFA), an association between buffers of the send queue and one or more receive queues based on a pattern of sharing defined by one or more of the plurality of accelerators; and (See Fig 15, paragraph [0077] and [0108], illustrates orchestrator server 1520 similar to server fabric adapter may identify patterns in resource utilization phases of workloads and organize received data using relationship such as locations, groupings of managed nodes by customers or accelerators where managed nodes may share workloads and also send queue and receive queue can be used to transfer)
transmitting, by the SFA, the data to the one or more accelerators by sending the data from the send queue to the one or more receive queues based on the association. (See Fig 18, paragraph [0132], illustrates at step 1804 memory interface device can determine to transmit the packet to a group of memory nodes or accelerators if a destination address of the packet is associated with a destination memory node that is part of a memory node group)
Regarding claim 2, SEN teaches The method of claim 1, wherein providing the memory tier comprises at least one of: assembling the memory tier from coherent memory blocks including compute express link (CXL) memory; or attaching a standard compute unit via peripheral component interconnect express (PCIe). (See Fig 8 and 16B, paragraph [0052] and [0123], illustrates network interface controller (NIC) 832 may be connected to a bus 622, memory and processor using CXL or PCIe connection and memory node 1680 can include one or more tiers of memory)
Regarding claim 3, SEN teaches The method of claim 1, wherein the association is one-to-one, and wherein transmitting the data from the send queue to the one or more receive queues comprises sending the data directly to a single receive queue using a media access control (MAC) address combined with a virtual local area network (VLAN) number. (See Fig 19 and 20, paragraph [0138] and [0157], illustrates MAC circuitry 1916 can be configured to perform MAC address filtering on received packets, after verifying data integrity transmit data packets to destination and source servers who are connected by Local Area Networks (LANs) with appropriate switching and routing facilities)
Regarding claim 4, SEN teaches The method of claim 1, wherein the association is one-to-many, and wherein transmitting the data from the send queue to the one or more receive queues comprises sending the data to multiple receive queues using a multicast address, (See Fig 16, paragraph [0120], illustrates PMA 1662 can include a multicast identifier (ID) or address with a packet to switch 1670 and switch 1670 can send or transmit copies of the packet to multiple memory nodes of a group associated with the multicast address)
wherein the multicast address represents a list of destinations’ addresses, and each destination’s address includes a MAC address combined with a VLAN number. (See Fig 16, paragraph [0120], illustrates switch 1670 can be configured with a look-up-table or list that associates multicast ID or address with destination IP addresses of memory nodes of a group)
Regarding claim 5, SEN teaches The method of claim 1, further comprising: generating and providing an error descriptor in a receive queue from the one or more receive queues when the receive queue has an error or insufficient space; and (See Fig 2, paragraph [0029], illustrates each pod 110, 120, 130, 140 may be connected to a different number of pod switches if a failure or error occurs to the pods due to capacity)
resending, via the SFA, the data to the receive queue in response to determining that the receive queue includes an error descriptor. (See Fig 17, paragraph [0130], illustrates host or orchestrator similar to SFA may change the memory group to exclude failing node in case failing node acknowledgement is generated to administrator which is similar to error descriptor)
Regarding claim 6, SEN teaches The method of claim 1, wherein the one or more accelerators defining the pattern of sharing form a copy group. (See Fig 15, paragraph [0077], illustrates orchestrator server 1520 may define patterns in resource utilization phases of the workloads by grouping of managed nodes)
Regarding claim 7, SEN teaches The method of claim 6, further comprising creating an arbitrary number of copy groups to provide sufficient capacity without increasing memory bandwidth requirements. (See Fig 15, paragraph [0077] and [0081], illustrates orchestrator server 1520 may define patterns in resource utilization phases of the workloads based on memory capacity to reduce bandwidth utilization or without increasing bandwidth)
Regarding claim 8, SEN teaches The method of claim 7, further comprising performing collective operations, wherein the SFA is configured to move the data to selected accelerators by creating a multicast group with the selected accelerators and using a collective operation to move the data into the memory tier. (See Fig 15, paragraph [0114], illustrates multicasting operation of data coping across multiple memory nodes to a group of two or more memory nodes in a memory pool and enhance multicasting with reliability using a higher-level memory or memory tier)
Regarding claim 9, SEN teaches The method of claim 1, further comprising presenting, by the SFA, a virtualized view of memory to a CPU and the one or more accelerators to cause the CPU to access and write the data into the send queue of the memory tier and (See Fig 16B, paragraph [0118], illustrates PMA 1662 which is similar to SFA can copy or store data to virtualized storage nodes using a protocol such as non-volatile memory express (NVMe). In other words, PMA can use virtualized view of memory to CPU to access data into memory)
the SFA to copy the data from the memory tier into memory of the one or more accelerators based on the association between the send queue and the one or more receive queues. (See Fig 16A, paragraph [0108], illustrates send queue and receive queue can be used to transfer work requests and are referred to as a Queue Pair or in other words data transfer are done using the association between send queue and receive queue)
Regarding claim 10, SEN teaches The method of claim 9, further comprising mediating the CPU access by configuring the SFA to present a CXL memory device to the CPU. (See Fig 14, paragraph [0072], illustrates memory controllers 1420 like SFA may be embodied as any type of processor, controller, or control circuit to control the writing and reading access of data into the memory sets 1430, 1432 based on requests received via the communication circuit 830 which may be based on CXL)
Regarding claim 11, SEN teaches The method of claim 1, wherein one or more of the send and receive send queues are implemented as queues managed by software or as embedded queues in hardware. (See Fig 16, paragraph [0108], illustrates hardware network interface 1604 can be RDMA-enabled to setup remote RDMA operations including send queues and receive queues where RDMA can manage the queues for read and write access)
Regarding claim 12, SEN teaches A system for using staging buffers in broadcast or multicast operations comprising: (See Fig 19, paragraph [0082] and [0142], illustrates multicast operation on network fabric which may include copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer)
a memory tier comprising a send queue and configured to be accessed by a plurality of accelerators and (See Fig 16A and 16B, paragraph [0086] and [0123], illustrates memory node 1680 can include one or more tiers of memory and memory pool 1650 may include plurality of accelerators)
to receive data in the send queue; and (See Fig 19, paragraph [0143], illustrates program network interface 1900 may include transmit or send queue 1906, receive queue 1908 for data transfer of memory 1910)
a server fabric adapter (SFA) communicatively coupled to the memory tier and the plurality of accelerators, wherein the SFA is configured to: establish an association between buffers of the send queue and one or more receive queues based on a pattern of sharing defined by one or more of the plurality of accelerators; and (See Fig 15, paragraph [0077] and [0108], illustrates orchestrator server 1520 similar to server fabric adapter may identify patterns in resource utilization phases of workloads and organize received data using relationship such as locations, groupings of managed nodes by customers or accelerators where managed nodes may share workloads and also send queue and receive queue can be used to transfer)
transmit the data to the one or more accelerators by sending the data from the send queue to the one or more receive queues based on the association. (See Fig 18, paragraph [0132], illustrates at step 1804 memory interface device can determine to transmit the packet to a group of memory nodes or accelerators if a destination address of the packet is associated with a destination memory node that is part of a memory node group)
Regarding claim 13, SEN teaches The system of claim 12, wherein, to provide the memory tier, the SFA is further configured to perform at least one of assembling the memory tier from coherent memory blocks including compute express link (CXL) memory or attaching a standard compute unit via peripheral component interconnect express (PCIe). (See Fig 8 and 16B, paragraph [0052] and [0123], illustrates network interface controller (NIC) 832 may be connected to a bus 622, memory and processor using CXL or PCIe connection and memory node 1680 can include one or more tiers of memory)
Regarding claim 14, SEN teaches The system of claim 12, wherein, the association is one-to-one, and to transmit the data from the send queue to the one or more receive queues, the SFA is further configured to send the data directly to a single receive queue using a media access control (MAC) address combined with a virtual local area network (VLAN) number. (See Fig 19 and 20, paragraph [0138] and [0157], illustrates MAC circuitry 1916 can be configured to perform MAC address filtering on received packets, after verifying data integrity transmit data packets to destination and source servers who are connected by Local Area Networks (LANs) with appropriate switching and routing facilities)
Regarding claim 15, SEN teaches The system of claim 12, wherein, the association is one-to-many, and to transmit the data from the send queue to the one or more receive queues, the SFA is further configured to send the data to multiple receive queues using a multicast address, (See Fig 16, paragraph [0120], illustrates PMA 1662 can include a multicast identifier (ID) or address with a packet to switch 1670 and switch 1670 can send or transmit copies of the packet to multiple memory nodes of a group associated with the multicast address)
wherein the multicast address represents a list of destinations’ addresses, and each destination’s address includes a MAC address combined with a VLAN number. (See Fig 16, paragraph [0120], illustrates switch 1670 can be configured with a look-up-table or list that associates multicast ID or address with destination IP addresses of memory nodes of a group)
Regarding claim 16, SEN teaches The system of claim 12, wherein the SFA is further configured to: generate and provide an error descriptor in a receive queue from the one or more receive queues when the receive queue has an error or insufficient space; and (See Fig 2, paragraph [0029], illustrates each pod 110, 120, 130, 140 may be connected to a different number of pod switches if a failure or error occurs to the pods due to capacity)
resend the data to the receive queue in response to determining that the receive queue includes an error descriptor. (See Fig 17, paragraph [0130], illustrates host or orchestrator similar to SFA may change the memory group to exclude failing node in case failing node acknowledgement is generated to administrator which is similar to error descriptor)
Regarding claim 17, SEN teaches The system of claim 12, wherein the one or more accelerators defining the pattern of sharing form a copy group. (See Fig 15, paragraph [0077], illustrates orchestrator server 1520 may define patterns in resource utilization phases of the workloads by grouping of managed nodes)
Regarding claim 18, SEN teaches The system of claim 17, wherein the SFA is further configured to create an arbitrary number of copy groups to provide sufficient capacity without increasing memory bandwidth requirements. (See Fig 15, paragraph [0077] and [0081], illustrates orchestrator server 1520 may define patterns in resource utilization phases of the workloads based on memory capacity to reduce bandwidth utilization or without increasing bandwidth)
Regarding claim 19, SEN teaches The system of claim 18, wherein the SFA is further configured to perform collective operations to move the data to selected accelerators by creating a multicast group with the selected accelerators and using a collective operation to move the data into the memory tier. (See Fig 15, paragraph [0114], illustrates multicasting operation of data coping across multiple memory nodes to a group of two or more memory nodes in a memory pool and enhance multicasting with reliability using a higher-level memory or memory tier)
Regarding claim 20, SEN teaches The system of claim 12, wherein one or more of the send and receive send queues are implemented as queues managed by software or as embedded queues in hardware. (See Fig 16, paragraph [0108], illustrates hardware network interface 1604 can be RDMA-enabled to setup remote RDMA operations including send queues and receive queues where RDMA can manage the queues for read and write access)
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure.
a. SAPIO et al. (US 20220109587 A1) teaches Examples described herein relate to a switch circuitry that includes circuitry to cause transmission, to multiple destinations, of copies of a packet received from a sender network interface device and circuitry to indicate acknowledgement of packet receipt, from the multiple destinations, to the sender network interface device based on receipt of acknowledgements of packet receipt from the multiple destinations. In some examples, the circuitry is to indicate acknowledgement of packet receipt, from the multiple destinations, to the sender network interface device with a packet index value.
b. Sankar et al. (US 20220217085 A1) teaches A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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