Prosecution Insights
Last updated: July 17, 2026
Application No. 18/666,719

HIGH BANDWIDTH MEMORY SYSTEMS AND DEVICES

Non-Final OA §102§103
Filed
May 16, 2024
Priority
Feb 26, 2024 — continuation of PCTCN2024078561
Examiner
KUSUMAKAR, KAREN M
Art Unit
Tech Center
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
838 granted / 962 resolved
+27.1% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
23 currently pending
Career history
983
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
41.2%
+1.2% vs TC avg
§112
1.1%
-38.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 962 resolved cases

Office Action

§102 §103
DETAILED ACTION Information Disclosure Statement The information disclosure statements (IDS) submitted on 11/20/24, 6/13/25, 7/15/25, 11/25/25, 12/18/25, 3/2/26, 3/25/26, 5/6/26, and 6/16/26 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 8-11, and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (EP 2672511). As to claims 1, 2, 8, and 14, Chen teaches a semiconductor device and method of making said semiconductor device (MCM 61, see annotated fig. 18 below), comprising: a base die (68), a first layer (30), a second layer (30), a first die (70) between the first layer (30) and the second layer (30), and a second die (74) stacked together along a first direction (D1, [0038] – [0039], 68, 70, and 74 all contain active circuitry 20, which can be a memory chip), wherein: each of the base die (68), the first die (70), and the second die (74) has a conductive layer (24.0/”CL1”, 24.1/”CL2”, and 24.2/”CL3”, respectively, [0038]); the first die (70) and the second die (74) are bonded through the second layer (30, see fig. below); and the base die (68) and the first die (70) are bonded through the first layer (30, see fig. below); a first contact structure (60.0, “CS1”) coupled to the conductive layer (CL1) of the base die (68), wherein the first contact structure extends along the first direction (D1) and contacts the conductive layer (CL1) of the base die (68) without extending through the first layer (30, [0052], see fig. below); a second contact structure (60.1, “CS2”) coupled to the conductive layer (CL2) of the first die (70), wherein: the second contact structure (CS2) extends through the first layer (30) along the first direction (D1) without extending through the second layer (30); and the second contact structure (CS2) contacts the conductive layer (CL2) of the first die (70) without extending through the conductive layer (CL1) of the base die (68, [0052], see fig. below); and a third contact structure (60.3, “CS3”) coupled to the conductive layer (CL3) of the second die (74), wherein: the third contact structure (CS3) extends through the first layer (30) and the second layer (30) along the first direction (D1) without extending through the second die (74); and the third contact structure (CS3) contacts the conductive layer (CL3) of the second die (74) without extending through the conductive layer (CL2) of the first die (70, [0052], see fig. below). PNG media_image1.png 712 944 media_image1.png Greyscale As to claims 3, 4, 9, 10, and 15, Chen further teaches a first end (“E2”) of the conductive layer (CL2) of the first die (70) and a first end (“E3”) of the conductive layer (CL3) of the second die (74) are offset along a second direction (D2) perpendicular to the first direction (D1, see annotated fig. above); the second contact structure (CS2) is between the first end (E2) of the conductive layer (CL2) of the first die (70) and the first end (E3) of the conductive layer (CL3) of the second die (74) along the second direction (D2, see annotated fig. above); and the third contact structure (CS3) is between the first end (E2) of the conductive layer (CL2) of the first die (70) and the first end (E3) of the conductive layer (CL3) of the second die (74) along the second direction (D2, see annotated fig. above). As to claim 11, Chen further teaches the second layer (30) comprises at least one dielectric material and excludes a conductive bonding contact ([0038], it’s a hard mask); and the first layer (30) comprises at least one dielectric material and excludes a conductive bonding contact ([0038], it’s a hard mask as well). As to claim 13, Chen further teaches the base die (68) comprises an interconnect layer (110) extending along a second direction (D2) perpendicular to the first direction (D1); and each of the first contact structure (CS1), the second contact structure (CS2), and the third contact structure (CS3) is coupled to the interconnect layer (110, [0052], they are connected to active components on layer 110). As to claim 16, Chen further teaches thinning the first die by thinning a substrate comprised in the first die ([0040]). As to claim 17, Chen further teaches the first contact structure and the second contact structure are formed by a same process (etching process through a mask 54, figs. 16-18) comprising: forming a first contact hole (1) and a second contact hole (2, fig. 16, [0049]); forming an insulating layer (94) in each of the first contact hole (0) and the second contact hole (1, fig. 16, [0049]); and forming the first contact structure (CS2) and the second contact structure (CS3) by forming a conductive structure (96) in the insulating layer (94) of each of the first contact hole (CS2) and the second contact hole (CS3), wherein the first contact structure (CS2) comprises the insulating layer (94) and the conductive structure (96) in the first contact hole (1), and the second contact structure (CS3) comprises the insulating layer (94) and the conductive structure (96) in the second contact hole (2, fig. 18, [0049]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chen. As to claim 12, Chen doesn’t explicitly teach the first and second layers each have a top dielectric layer and a bottom dielectric layer. However, fabricating hard masks that comprise multiple dielectric layers (such as ONO layers) is known in the art and would have been obvious to use so as to adjust etching profiles and protection parameters. Allowable Subject Matter Claims 5-7 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. As to claims 5 and 18, the prior art fails to teach and the bonding layer(s) comprise(s) conductive bonding contacts and at least one dielectric material isolating the conductive bonding contacts. The bonding layers are hardmasks. They do not, and would not, comprise conductive bonding contacts. Claims 6, 7, 19, and 20 are allowable at least because they depend from allowable claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any response to this Office Action should be faxed to (571) 273-8300 or mailed to: Commissioner for Patents P.O. Box 1450 Alexandria, VA 22313-1450 Hand-Delivered responses should be brought to: Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22313 Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAREN KUSUMAKAR/ Primary Examiner, Art Unit 2897 6/24/26
Read full office action

Prosecution Timeline

May 16, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.8%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 962 resolved cases by this examiner. Grant probability derived from career allowance rate.

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