DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites that “the third bonding area has a third antenna ratio lower than the second pattern density.” As defined in the specification, an antenna ratio “refers to a ratio between the surface area of a line […] and the total surface area of vias that are connected to the line”, and is thus a unitless quantity. The second pattern density, in plain meaning, would be some sort of thing per unit area, volume, length, etc. Therefore, it does not make sense to compare an antenna ratio to a pattern density, and the claim is rendered indefinite. For the purposes of applying art, this limitation was interpreted to mean that the third antenna ratio is lower than the second antenna ratio.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 11, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20220013502 A1), hereinafter referred to as "Lee".
In regards to claim 1, Lee discloses A semiconductor structure, comprising: a semiconductor device (10C in figure 8) including: a substrate (10W in Lee figure 8); a device region over the substrate (region with 10TR in figure 4); a bonding region over the device region (MPR1, DPR1, and MPR2 in figure 7, above the substrate, see figure 8), wherein the bonding region includes a first bonding area having a first pattern density (MPR1 in figure 7 has pattern density D_MP1, see paragraph 0064), a second bonding area having a second pattern density adjacent to the first bonding area (DPR1 in figure 7 has pattern density D_DP1, see paragraph 0064), and a third bonding area having a third pattern density adjacent to the second bonding area (MPR2 in figure 7 has pattern density D_MP2, see paragraph 0064); and a plurality of bonding structures in the bonding region including a first bonding structure in the first bonding area (first main connection pad structures MP1 in figure 7, see paragraph 0063), a second bonding structure in the second bonding area (dummy connection pad structures DP1 in figure 7, see paragraph 0063), and a third bonding structure in the third bonding area (second main connection pad structures MP2 in figure 7, see paragraph 0063).
In regards to claim 2, Lee discloses all of the limitations of claim 1, and further discloses that the first pattern density is higher than the second pattern density (Lee paragraph 0065, see figure 7).
In regards to claim 3, Lee discloses all of the limitations of claim 2, and further discloses the second pattern density is higher than the third pattern density (Lee paragraph 0065, see figure 7).
In regards to claim 4, Lee discloses all of the limitations of claim 3, and further discloses the second bonding structure is electrically floating and does not have electrical functions (Lee discloses that “are not connected to transfer any signals to or from any integrated circuits of the respective semiconductor chip”, paragraph 0058).
In regards to claim 5, Lee discloses all of the limitations of claim 4, and further discloses the first and third bonding structures are active bonding structures having electrical functions (Lee paragraph 0058, the first bonding structure MP1 and third bonding structure MP2 may “be used to communicate or transfer signals from/to outside a respective semiconductor chip to/from an integrated circuit of the semiconductor chip”, paragraph 0058).
In regards to claim 16, Lee discloses all of the limitations of claim 1, and further discloses that the semiconductor device is a first semiconductor device, further comprising a second semiconductor device (20C in figure 8) including a fourth bonding structure (upper MPR1 in figure 8), a fifth bonding structure (upper DPR1 in figure 8), and a sixth bonding structure (upper MPR2 in figure 8) bonded to the first, second, and third bonding structures, respectively, at a bonding interface (see figure 8).
In regards to claim 17, Lee discloses all of the limitations of claim 1, and further discloses that the second bonding structure is electrically isolated from the first and third bonding structures by a first dielectric layer (bonding insulating layer 10UI, paragraph 0027, in between MPR1 and DPR1 in figure 8), and the fifth bonding structure is electrically isolated from the fourth and sixth bonding structures by a second dielectric layer (bonding insulating layer 20UI, paragraph 0027, in between MPR1 and DPR1 in figure 8), wherein the first dielectric layer and the second dielectric layer are bonded at the bonding interface (see figure 8).
In regards to claim 18, Lee discloses all of the limitations of claim 1, and further discloses that the bonding interface extends across the semiconductor structure (see figure 8).
In regards to claim 19, Lee discloses all of the limitations of claim 1, and further discloses that the fourth and sixth bonding structures are active bonding structures having electrical functions (Lee paragraph 0058).
In regards to claim 20, Lee discloses all of the limitations of claim 1, and further discloses that the fifth bonding structure is electrically floating and does not have electrical functions (The fifth bonding structure, upper DP1 in figure 8, is also a dummy pad, and thus electrically floating, Lee paragraph 0058).
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In regards to claim 6, Lee discloses all of the limitations of claim 1, specifically, it also discloses all limitations according to annotated figure 7 (each bonding region is an area encompassing the 1st 2nd or 3rd lines, and each one has a pattern density equal to each other). Lee further discloses that the first, second, and third bonding structures each comprises: a horizontal line structure (See lines marked in annotated figure 7); and at least one vertical via structure electrically connected to the line structure (at least 1 pad MP1 is electrically connected to each line).
In regards to claim 11, Lee discloses all of the limitations of claim 6, and further discloses that the line structure of the second bonding structure has a length substantially equal to the line structure of the first bonding structure (All of the line structures in annotated figure 7 are the same length).
In regards to claim 15, Lee discloses all of the limitations of claim 1, specifically, it also discloses all limitations if MPR2 is considered the first bonding area and MPR1 is considered the second bonding area. Lee then further discloses that the first bonding area has a first antenna ratio, the second bonding area has a second antenna ratio lower than the first antenna ratio (The antenna ratio is defined in the instant specification to be “a ratio between the surface area of a line […] and the total surface area of vias that are connected to the line” (paragraph 0031 of instant application). The second bonding area DPR1 has a greater pattern density, D_DP1 than MPR2, see paragraph 0064, and therefore has a greater number of pad structures per unit area. Thus, the area of the pads increases relative to the area of the line, which increases the denominator of the ratio and thus decreases the antenna ratio), and the third bonding area has a third antenna ratio lower than the second pattern density (see above 112b rejection. The third bonding area MPR1 has a greater pattern density, D_MP1 than DPR1, see paragraph 0064, and therefore has a greater number of pad structures per unit area. Thus, the area of the pads increases relative to the area of the line, which increases the denominator of the ratio and thus decreases the antenna ratio).
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Claims 1, 6-9, and 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 20240194624 A1), hereinafter referred to as "Kim".
In regards to claim 1, Kim discloses A semiconductor structure (200c in Kim figures 8 and 9), comprising: a semiconductor device including: a substrate (220 and 230 in figure 9 can act as a substrate); a device region over the substrate (204 in figure 9, see paragraph 0028); a bonding region over the device region (area above 204), wherein the bonding region includes a first bonding area having a first pattern density (see figure 8 annotations), a second bonding area having a second pattern density adjacent to the first bonding area (see figure 8 annotations), and a third bonding area having a third pattern density adjacent to the second bonding area (see figure 8 annotations; all three bonding areas have the same pattern density); and a plurality of bonding structures in the bonding region including a first bonding structure in the first bonding area (pads and vias in first bonding area), a second bonding structure in the second bonding area (pads and vias in first bonding area), and a third bonding structure in the third bonding area (pads and vias in first bonding area).
In regards to claim 6, Kim discloses all of the limitations of claim 1. Kim further discloses that the first, second, and third bonding structures each comprises: a horizontal line structure (254 in figure 8, extends horizontally in the x direction); and at least one vertical via structure electrically connected to the line structure (252 in figures 8 and 9, extend vertically in z direction).
In regards to claim 7, Kim discloses all of the limitations of claim 6. Kim further discloses that the line structure of the first, second, and third bonding structures are substantially parallel (see figure 8).
In regards to claim 8, Kim discloses all of the limitations of claim 6. Kim further discloses that the second bonding area further comprises a fourth bonding structure immediately between the first and second bonding structures (see figure 8 annotation), wherein the fourth bonding structure is spaced apart from the first bonding structure by a first distance and from the second bonding structure by a second distance different from the first distance (see figure 8).
In regards to claim 9, Kim discloses all of the limitations of claim 8. Kim further discloses that the first distance is wider than the second distance (see figure 8).
In regards to claim 12, Kim discloses all of the limitations of claim 6. Kim further discloses that the line structure of the second bonding structure has a shorter length than the line structure of the first bonding structure (see figure 8. The second structure’s line is shorter than the first structure’s line, only containing 1 via).
In regards to claim 13, Kim discloses all of the limitations of claim 12. Kim further discloses that the second bonding area further comprises a fourth bonding structure between the first and second bonding structures (see figure 8), wherein the fourth bonding structure has a shorter length than the line structure of the first bonding structure and a longer length than the line structure of the second bonding structure (see figure 8. The lengths of the lines, in this case in the x-direction in the figure, decrease as it goes from the first line to fourth line to second line).
In regards to claim 14, Kim discloses all of the limitations of claim 14. Kim further discloses that the at least one via structure is part of a plurality of via structures, and the plurality of via structures is arranged in an array configuration of rows and columns (see figure 8. Vias 252 are in rows and columns).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen et al. (US 20240088002 A1), hereinafter referred to as "Chen".
In regards to claim 10, Kim discloses all of the limitations of claim 9. Kim is silent on the exact spatial dimensions of the distances between the lines.
In the same field of hybrid bonding, Chen teaches that reducing the spacing between wiring layers to less than 1 µm minimizes the package volume and reduces the manufacturing cost (Chen paragraph 0058).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reduce the spacing of the horizontal lines to be less than 2 µm as in Chen in order to minimize the package volume and reduce the manufacturing cost.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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