Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-9, in the reply filed on August 8, 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
PNG
media_image1.png
647
589
media_image1.png
Greyscale
Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng (US 20190206888 A1), hereinafter referred to as "Peng".
Regarding claim 1, Peng discloses a SONOS memory element, comprising: a substrate (Substrate in Peng figure 2f); a plurality of source lines, formed in the substrate (source line in figure 2f); a semiconductor epitaxial layer, formed on the substrate (conduction channel and bit line in figure 2f. These can be epitaxially gown, see Peng paragraph 0018); a plurality of element isolation structures, formed in the semiconductor epitaxial layer and extending along a first direction to define a plurality of active regions in the semiconductor epitaxial layer (part of the oxide above the nitride and the bit line in figure 2f); a plurality of trenches, formed in the semiconductor epitaxial layer and spanning the element isolation structures along a second direction (a trench can be considered to be defined by the insulator layers on either side of the gate word lines and the epitaxial layer/substrate in figure 2f. In this regard it is still formed in the epitaxial layer due to the etched portions), wherein a bottom of each of the trenches exposes a part of each of the source lines (source lines in figure 2f are exposed at the bottom of the trench); a plurality of gates (Word line (Gate ) in figure 2f), respectively located in the trenches (They occupy the area between the insulator lines which define the trench); an oxide-nitride-oxide (ONO) stack layer (Oxide and Nitride in figure 2f, see Peng paragraph 0018), located between each of the gates and each of the trenches (see figure 2f); a plurality of drain regions (region of conductive channel closest to the bit Line in figure 2f. In order for the transistor to work there must be a drain region, and the Bit Line is also referred to as the drain electrode, see paragraph 0008), formed in the active regions on both sides of each of the gates (each deep gate part has an active region with a drain region on its left and right; figure 2f); and a plurality of bit lines (Bit Line in figure 2f), located on the semiconductor epitaxial layer and electrically connected to the drain regions (They are directly on the epitaxial layer and connected to the drain region, since they are also drain electrode, see paragraph 0008).
Regarding claim 8, Peng discloses all of the limitations of claim 1, and further discloses a part of the trenches intersecting with the element isolation structures has a first depth (seen by the part of the gate over the active stack in figure 2f), a part of the trenches not intersecting with the element isolation structures has a second depth (seen by the part of the gate that is between the active stacks in figure 2f), and the second depth is greater than the first depth (The depth between the active stacks is deeper than the depth on top of the active stacks).
Regarding claim 9, Peng discloses all of the limitations of claim 1, and further discloses that the bit lines are in direct contact with the drain regions (the bit lines are also drain electrodes, and are in direct contact with the conduction channel, see paragraph 0008 and figure 2f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
PNG
media_image2.png
382
483
media_image2.png
Greyscale
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Akaogi et al. (US 20140078832 A1), hereinafter referred to as "Akaogi".
Regarding claim 2, Peng discloses all of the limitations of claim 1. Peng further discloses that the bit lines are perpendicular to the gates (Peng figure 2f; the gates run left to right, and the bit lines run into and out of the page in the cross-sectional view).
Peng dos not explicitly disclose that the source lines are parallel to the gates.
Akaogi teaches a SONOS memory element where the source lines are parallel to the gates (Akaogi figure 7, source regions 204 are parallel to gate 202; see also paragraph 0026). Akaogi also teaches that this streamlines the spatial arrangement of the invention and facilitates memory scaledown (Akaogi paragraph 0038).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the source line parallel to the gates in order to streamline the spatial arrangement and facilitate memory scaledown.
Furthermore, since the bit line is perpendicular to the gate in Peng, if the source line is adjusted to be parallel to the gate, then the combined invention would have the bit lines perpendicular to the source lines.
Regarding claim 3, Peng in view of Akaogi teaches all of the limitations of claim 2. Peng further discloses that in a top view, each of the source lines overlaps with each of the gates (Peng figure 2f, since they are both in the same cross section they overlap).
Regarding claim 4, Peng in view of Akaogi teaches all of the limitations of claim 2. Peng further discloses that in a top view, the source lines are disposed on both sides of each of the gates (with the repeated structure of multiple source lines, and with at least one associated with each gate, there are source lines on each side of the gate when they are parallel).
PNG
media_image3.png
779
442
media_image3.png
Greyscale
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Riedel (US 20050006710 A1), hereinafter referred to as "Riedel".
Regarding claim 5, Peng discloses all of the limitations of claim 1. Peng further discloses that the bit lines are not parallel to the gates (bit lines are perpendicular to gates in Peng figure 2f), and the source lines are perpendicular to the gates (Peng figure 2f; the gates run left to right, and the source lines run into and out of the page in the cross-sectional view).
Peng does not explicitly disclose that the bit lines are not parallel to the source lines.
Riedel teaches a memory structure where the bit lines are at an acute angle with respect to the word lines (Riedel figure 4; bit lines 7 are at an acute angle with respect to word lines 6). Riedel also teaches that this allows the drain regions of the relevant memory transistor which are associated with a respective memory cell to be connected to two mutually adjacent bit lines. Since the source lines of Peng are perpendicular to the gates, if the bit line is at an acute angle with respect to the gate, it would also be at an acute angle with respect to the source line, and thus would not be parallel to the source line.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the bit lines at an acute angle with the gate word lines, and thus also the source lines, in order to allow the drain regions of the relevant memory transistor which are associated with a respective memory cell to be connected to two mutually adjacent bit lines
Regarding claim 6, Peng in view of Riedel teaches all of the limitations of claim 5. Riedel further discloses that in a top view, an angle is formed between the bit lines and the source lines, and the angle is between 20O and 60O (Riedel paragraph 0007; the angle between the bit lines and the word lines can be 45O, which would make the angle between the bit lines and source lines also 45O).
PNG
media_image4.png
637
909
media_image4.png
Greyscale
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Huang (US 9691907 B1), hereinafter referred to as "Huang".
Regarding claim 7, Peng discloses all of the limitations of claim 1. Peng does not disclose that a top of the gate is lower than a top of the trenches.
Huang teaches a SONOS memory element where a top of the gate is lower than a top of a trench (Huang figure 1 the top of gates 41G, 42G, and 44G is below the top of dielectric layer 36, which can define a trench similarly to in Peng). This allows room for a dielectric layer on top of the gate (34 in Huang figure 1), which provides additional electrical isolation from the other components.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a top of the gate be lower than a top of the trenches in order to add a dielectric layer as in Huang in order to provide additional electrical isolation from the other components.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights