DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 22 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 18 recite “wherein the memory controller dynamically generates at least one parameter regarding interrupt coalescing according to a real-time queue depth of the transmission interface circuit, and controls the interrupt coalescing according to the at least one parameter” (emphasis added). However, there is not support for the limitation “queue depth of the transmission interface circuit” in the originally filed specification. The claims require the “transmission interface circuit” be “within the memory controller” (lines 8 and 9 of claim 1) and the memory controller be within the memory device (line 4 of claim 1). However, the specification states that the queue depth (QD) is a “host side parameter” that the memory controller obtains from the host device through a bottom layer circuit (Original Specification; Paragraph [0033]), the bottom layer circuit being within the transmission interface circuit (Figure 1). In other words, the queue depth is obtained by the transmission interface circuit from the host device. Based on the teachings of the specification, the Examiner asserts that the queue depth is not “of the transmission interface circuit” but instead a queue depth of the host device. The Examiner is unable to locate anywhere in the originally filed specification any teaching or suggestion that the queue depth is of the transmission interface circuit located within the memory device. Therefore, the above limitation is considered new matter.
Claims 2 – 17 and 19 – 22 are also rejected because of their inheritance of the deficiencies of parent claims 1 and 18.
In the interest of compact prosecution, the above limitation is further examined based on an interpretation of the queue depth being of the host device, which is properly supported in the originally filed specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2021/0042039 (hereinafter Benisty) in view of US Patent No. 12,204,470 (hereinafter Kunt).
As per claim 1, Benisty teaches a method for performing access control of a memory device (Benisty; Figure 2A Item 100, Figure 4 Item 420) with aid of interrupt management, the method being applicable to a memory controller (Benisty; Figure 2A Item 102, Figure 3 Item 310, Figure 4 Item 422) of the memory device, the memory device comprising the memory controller (Benisty; Figure 2A Item 102, Figure 3 Item 310, Figure 4 Item 422) and a non-volatile (NV) memory (Benisty; Figure 2A Item 104, Figure 4 Item 450), the NV memory comprising at least one NV memory element (Benisty; Figure 2A Item 104, Figure 4 Item 450), the at least one NV memory element comprising a plurality of blocks (Benisty; Paragraph [0028]), the method comprising: utilizing the memory controller to receive a set of commands (Benisty; Figure 3 Step 3, Paragraph [0049] “4 commands” and “set of commands,” Paragraph [0051] “the memory device fetches the command(s) from the particular submission queue,” Paragraph [0053] “the memory device can obtain all of the new commands from the submission queue”) from a host device (Benisty; Figure 3 Item 300, Figure 4 Item 400) through a transmission interface circuit (Benisty; Figure 2A Items 108, 112, and 113, Figure 4 Items 432 and 448) within the memory controller, wherein a command count of the set of commands is greater than one (Benisty; Paragraph [0049] “4 commands” and “set of commands,” Paragraph [0051] “fetches the command(s)”), and any command among the set of commands indicates a request for accessing the memory device (Benisty; Paragraph [0054] “the command may comprise a read command” and “the command may comprise a write command”); and in response to the set of commands, utilizing the memory controller to perform a set of accessing operations upon the NV memory for the host device (Benisty; Figure 3 Step 4, Paragraph [0054]), and return a single message-signaled interrupt (MSI) (Benisty; Paragraph [0059] “MSIe”) corresponding to the set of commands to the host device by the transmission interface circuit (Benisty; Figure 3 Step 6, Paragraph [0059]), for notifying the host device of completion of device side access control of the memory device regarding the set of commands (Benisty; Paragraph [0059]), to allow the host device to complete host side access control of the host device regarding the set of commands (Benisty; Figure 3 Steps 7 and 8, Paragraphs [0060] and [0061]), wherein the set of accessing operations comprises a corresponding accessing operation performed by the memory controller in response to the command among the set of commands (Benisty; Paragraph [0054]).
Benisty does not teach wherein the memory controller dynamically generates at least one parameter regarding interrupt coalescing according to a real-time queue depth of the host device, and controls the interrupt coalescing according to the at least one parameter.
However, Kunt teaches an interrupt coalescing system in which a memory controller of a memory device dynamically generates at least one parameter regarding interrupt coalescing according to a real-time queue depth of the host device (Kunt; Col 2 Lines 44 – 64, Col 6 Lines 11 – 25, Col 7 Lines 14 – 24), and controls the interrupt coalescing according to the at least one parameter (Kunt; Col 2 Lines 44 – 64).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Benisty to include the dynamically generated parameters because doing so allows for maintaining quality of service (Kunt; Col 2 Lines 53 – 64).
As per claim 2, Benisty also teaches wherein the single MSI is implemented by one of a non-extended MSI and an extended MSI (MSI-X) (Benisty; Paragraph [0059] “MSIe”).
As per claim 3, Benisty in combination with Kunt teaches the invention as described per claim 1 (see rejection of claim 1 above).
Benisty in combination with Kunt does not explicitly teach wherein the set of commands represents a first set of commands among multiple sets of commands, and the multiple sets of commands comprise the first set of commands and a second set of commands; the set of accessing operations represents a first set of accessing operations among multiple sets of accessing operations, and the multiple sets of accessing operations comprise the first set of accessing operations and a second set of accessing operations; the single MSI represents a first MSI corresponding to the first set of commands among multiple MSIs, and the multiple MSIs comprise the first MSI and a second MSI; and the method further comprises: utilizing the memory controller to receive the second set of commands from the host device through the transmission interface circuit within the memory controller, wherein a command count of the second set of commands is greater than one, and any command among the second set of commands indicates a request for accessing the memory device; and in response to the second set of commands, utilizing the memory controller to perform the second set of accessing operations upon the NV memory for the host device, and return the second MSI corresponding to the second set of commands to the host device by the transmission interface circuit, for notifying the host device of completion of device side access control of the memory device regarding the second set of commands, to allow the host device to complete host side access control of the host device regarding the second set of commands, wherein the second set of accessing operations comprises a corresponding accessing operation performed by the memory controller in response to the command among the second set of commands.
However, such a modification is considered to be within the level of ordinary skill in the art as set forth by the following legal precedents; See Making Continuous - In re Dilnot, 319 F.2d 188, 138 USPQ 248 (CCPA 1963).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Benisty in combination with Kunt to include the second set of commands and second MSI because doing so allows for continued operation of the system beyond an initial set of commands, as is typical in computer systems.
As per claim 4, Benisty also teaches wherein the set of commands comprises a combination or one of a read command and a write command (Benisty; Paragraph [0054]).
As per claim 5, Benisty also teaches wherein: in response to the command among the set of commands being a read command, the memory controller is arranged to read stored data from the NV memory as read data (Benisty; Paragraph [0055], Paragraph [0066]), for transmitting to the host device; and in response to the command among the set of commands being a write command, the memory controller is arranged to write data from the host device into the NV memory (Benisty; Paragraph [0055], Paragraph [0067]).
As per claim 6, Benisty also teaches the device side access control regarding the set of commands comprises: accessing a host buffer (Benisty; Figure 4 Item 404) within the host device (Benisty; Figure 4 Item 400, Paragraph [0054], Paragraph [0063]); and pushing at least one completed command to at least one completion queue (CQ) (Benisty; Figure 3 Item 306) within the host device (Benisty; Figure 3 Step 5, Paragraph [0058]).
As per claim 7, Benisty also teaches wherein: in response to the command among the set of commands being a read command, accessing the host buffer within the host device comprises transmitting read data to the host buffer, wherein the read data is read from the NV memory (Benisty; Paragraph [0066]); and in response to the command among the set of commands being a write command, accessing the host buffer within the host device comprises obtaining write data from the host buffer, for being written into the NV memory (Benisty; Paragraph [0067]).
As per claim 8, Benisty also teaches wherein the host side access control regarding the set of commands comprises: obtaining completion information of at least one command from at least one completion queue (CQ) within the memory device (Benisty; Figure 3 Step 7, Paragraph [0060]); and writing at least one CQ head doorbell (Benisty; Figure 3 Item 314) within the memory device, to release at least one CQ entry in the at least one CQ (Benisty; Figure 3 Step 8, Paragraph [0061]).
As per claim 9, Benisty also teaches wherein the host side access control regarding the set of commands further comprises: before the device side access control regarding the set of commands is performed by the memory device, inserting at least one host command into at least one submission queue (SQ) (Benisty; Figure 3 Item 304) as at least one new command (Benisty; Figure 3 Step 1, Paragraph [0048]); and writing at least one SQ tail doorbell (Benisty; Figure 3 Item 312) within the memory device, for indicating the at least one new command by signaling (Benisty; Figure 3 Step 2, Paragraph [0049]).
As per claim 10, Benisty in combination with Kunt also teaches wherein the memory controller is arranged to dynamically adjust at least one configuration of at least one component within the memory controller (Kunt; Col 6 Lines 11 – 25), to minimize a total time of the host side access control of the host device regarding the set of commands (Benisty; Paragraph [0039], Paragraph [0074]).
As per claim 11, Benisty also teaches wherein the at least one component comprises the transmission interface circuit (Benisty; Figure 2A Items 108, 112, and 113, Figure 4 Items 432 and 448), and the at least one configuration comprises a set of configurations of a bottom layer circuit within the transmission interface circuit (Benisty; Paragraph [0039]).
As per claim 12, Benisty in combination with Kunt also teaches wherein the set of configurations of the bottom layer circuit represents configurations determined by multiple parameters of the bottom layer circuit (Benisty; Paragraph [0074] “PCIe and Host latency”) (Kunt; Col 7 Lines 14 – 24), wherein the at least one parameter comprises the multiple parameters of the bottom layer circuit (Kunt; Col 7 Lines 14 – 24).
As per claim 13, Benisty also teaches wherein the memory controller is arranged to dynamically adjust the at least one parameter of the transmission interface circuit, for accelerating completion of the host side access control regarding the set of commands (Benisty; Paragraph [0074] “adaptive”).
As per claim 14, Benisty also teaches wherein the memory controller is arranged to dynamically adjust the at least one parameter to perform access control in response to a latest state of the electronic device, for accelerating the completion of the host side access control regarding the set of commands (Benisty; Paragraph [0074]).
As per claim 15, Benisty also teaches wherein the at least one parameter comprises multiple parameters of a bottom layer circuit within the transmission interface circuit (Benisty; Paragraph [0074] “PCIe and Host latency”); and the memory controller is arranged to dynamically adjust the multiple parameters of the bottom layer circuit by at least one upper layer circuit within the memory controller (Benisty; Paragraph [0074] “adaptive”), for accelerating the completion of the host side access control regarding the set of commands.
As per claim 16, Benisty also teaches wherein the at least one parameter comprises multiple aggregation parameters (Benisty; Paragraph [0074] “PCIe and Host latency”); and the memory controller is arranged to dynamically adjust the multiple aggregation parameters (Benisty; Paragraph [0074] “adaptive”) according to at least one predetermined rule (Benisty; Paragraph [0078]), for accelerating the completion of the host side access control regarding the set of commands.
As per claim 17, Benisty in combination with Kunt teaches the invention as described per claim 13 (see rejection of claim 13 above). Benisty in combination with Kunt also teaches wherein the at least one parameter comprises multiple aggregation parameters (Benisty; Paragraph [0074] “PCIe and Host latency”) and the memory controller is arranged to dynamically adjust the multiple aggregation parameters (Benisty; Paragraph [0074] “adaptive,” Paragraph [0078]), to optimize timings of the MSI with respect to the set of commands.
Benisty does not explicitly teach wherein the set of commands represents a first set of commands among multiple sets of commands, the set of accessing operations represents a first set of accessing operations among multiple sets of accessing operations, and the single MSI represents a first MSI corresponding to the first set of commands among multiple MSIs.
However, such a modification is considered to be within the level of ordinary skill in the art as set forth by the following legal precedents; See Making Continuous - In re Dilnot, 319 F.2d 188, 138 USPQ 248 (CCPA 1963).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Benisty in combination with Kunt to include the multiple sets of commands, access operations, and MSIs because doing so allows for continued operation of the system beyond an initial set of commands, as is typical in computer systems.
As per claim 18, Benisty teaches a memory controller (Benisty; Figure 2A Item 102, Figure 3 Item 310, Figure 4 Item 422) of a memory device (Benisty; Figure 2A Item 100, Figure 4 Item 420), the memory device comprising the memory controller and a non-volatile (NV) memory (Benisty; Figure 2A Item 104, Figure 4 Item 450), the NV memory comprising at least one NV memory element (Benisty; Figure 2A Item 104, Figure 4 Item 450), the at least one NV memory element comprising a plurality of blocks (Benisty; Paragraph [0028]), the memory controller comprising: a processing circuit (Benisty; Figure 2A Items 110, 112, 113, 114, and 138, Figure 4 Items 424 and 436), arranged to control the memory controller according to a plurality of host commands from a host device (Benisty; Figure 3 Item 300, Figure 4 Item 400), to allow the host device to access the NV memory through the memory controller, wherein the processing circuit is arranged to perform access control of the memory device with aid of interrupt management (Benisty; Paragraph [0028]); and a transmission control circuit (Benisty; Figure 2A Items 108, 112, and 113, Figure 4 Items 432 and 448), arranged to perform communications with the host device; wherein: the memory controller receives a set of commands from the host device through the transmission interface circuit within the memory controller Benisty; Figure 3 Step 3, Paragraph [0049] “4 commands” and “set of commands,” Paragraph [0051] “the memory device fetches the command(s) from the particular submission queue,” Paragraph [0053] “the memory device can obtain all of the new commands from the submission queue”), wherein a command count of the set of commands is greater than one (Benisty; Paragraph [0049] “4 commands” and “set of commands,” Paragraph [0051] “fetches the command(s)”), and any command among the set of commands indicates a request for accessing the memory device (Benisty; Paragraph [0054] “the command may comprise a read command” and “the command may comprise a write command”); and in response to the set of commands, the memory controller performs a set of accessing operations upon the NV memory for the host device (Benisty; Figure 3 Step 4, Paragraph [0054]), and returns a single message-signaled interrupt (MSI) (Benisty; Paragraph [0059] “MSIe”) corresponding to the set of commands to the host device by the transmission interface circuit (Benisty; Figure 3 Step 6, Paragraph [0059]), for notifying the host device of completion of device side access control of the memory device regarding the set of commands (Benisty; Paragraph [0059]), to allow the host device to complete host side access control of the host device regarding the set of commands (Benisty; Figure 3 Steps 7 and 8, Paragraphs [0060] and [0061]), wherein the set of accessing operations comprises a corresponding accessing operation performed by the memory controller in response to the command among the set of commands (Benisty; Paragraph [0054]).
Benisty does not teach wherein the memory controller is configured to dynamically generate at least one parameter regarding interrupt coalescing according to a real-time queue depth of the host device, and controls the interrupt coalescing according to the at least one parameter.
However, Kunt teaches an interrupt coalescing system in which a memory controller of a memory device dynamically generates at least one parameter regarding interrupt coalescing according to a real-time queue depth of the host device (Kunt; Col 2 Lines 44 – 64, Col 6 Lines 11 – 25, Col 7 Lines 14 – 24), and controls the interrupt coalescing according to the at least one parameter (Kunt; Col 2 Lines 44 – 64).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Benisty to include the dynamically generated parameters because doing so allows for maintaining quality of service (Kunt; Col 2 Lines 53 – 64).
As per claim 19, Benisty also teaches wherein the memory device comprises: the NV memory (Benisty; Figure 2A Item 104 Figure 4 Item 450), arranged to store information (Benisty; Paragraph [0036], Paragraph [0040]); and the memory controller (Benisty; Figure 2A Item 102, Figure 4 Item 422), coupled to the NV memory (Benisty; Figure 2A, Figure 4), and arranged to control operations of the memory device (Benisty; Paragraph [0033]).
As per claim 21, Kunt also teaches wherein the multiple aggregation parameters comprise an aggregation time and an aggregation threshold (Kunt; Col 6 Lines 39 – 45).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2021/0042039 (hereinafter Benisty) in view of US Patent No. 12,204,470 (hereinafter Kunt), and further in view of US Patent Application Publication No. 2021/0034128 (hereinafter Suljic).
As per claim 20, Benisty in combination with Kunt teaches the invention as described per claim 19 (see rejection of claim 19 above). Benisty in combination with Kunt also teaches an electronic device (Benisty; Figure 4) (Kunt; Figure 1 Item 100) comprising the memory device (Benisty; Figure 4 Item 420) (Kunt; Figure 1 Item 102) and further comprising: the host device (Benisty; Figure 4 Item 400) (Kunt; Figure 1 Item 112), coupled to the memory device, wherein the host device comprises: at least one processor (Benisty; Figure 4 Item 402), arranged to control operations of the host device; wherein the memory device provides the host device with storage space (Benisty; Paragraph [0028]) (Kunt; Col 4 Lines 11 – 19).
Benisty in combination with Kunt does not explicitly teach wherein the host device comprises a power supply circuit, coupled to the at least one processor, and arranged to provide power to the at least one processor and the memory device.
However, Suljic teaches a memory system in which a host includes a power supply circuit which provides power to the memory device and the host system (Suljic; Paragraphs [0031], [0048], [0050], and [0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Benisty in combination with Kunt to include the power supply circuit because doing so allows for powering on the system.
Allowable Subject Matter
Claim 22 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 22 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein the aggregation threshold is equal to a third gain applied to the sum of a first gain applied to a previous processing result and a second gain applied to the queue depth, as required by dependent claim 22, in combination with the other claimed limitations (emphasis added). The prior art of record teaches generating an aggregation threshold parameter (Kunt; Col 6 Lines 39 – 45), but does not teach the specific method used to generate the aggregation threshold parameter as required by dependent claim 22.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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