Prosecution Insights
Last updated: October 04, 2026
Application No. 18/666,884

ARCHITECTURAL REDUCTION OF VOLTAGE AND CLOCK ATTACK WINDOWS

Non-Final OA §101
Filed
May 17, 2024
Priority
May 18, 2023 — provisional 63/467,335 +18 more
Examiner
LOTTICH, JOSHUA P
Art Unit
2113
Tech Center
2100 — Computer Architecture & Software
Assignee
Akeana Inc.
OA Round
3 (Non-Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
704 granted / 780 resolved
+35.3% vs TC avg
Minimal +4% lift
Without
With
+3.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
11 currently pending
Career history
788
Total Applications
across all art units

Statute-Specific Performance

§101
29.2%
-10.8% vs TC avg
§103
24.8%
-15.2% vs TC avg
§102
18.0%
-22.0% vs TC avg
§112
19.4%
-20.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 780 resolved cases

Office Action

§101
DETAILED ACTION The following is a Non-Final Office action in response to communications received 9/1/26. Claim(s) 21 has(have) been canceled. Claim(s) 26 has(have) been amended. Therefore, claim(s) 1-20 and 22-27 is(are) pending and addressed below. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 26 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter. As per claim(s) 26, the claimed system has been read in view of applicant's specification (the computer program product comprising code, [0061, 0062], A programmable apparatus which executes any of the above-mentioned computer program products, [0066], It will be understood that a computer may include a computer program product from a computer-readable storage medium, [0067], Any combination of one or more computer readable media may be utilized including but not limited to: a non-transitory computer readable medium for storage; an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor computer readable storage medium or any suitable combination of the foregoing; a portable computer diskette; a hard disk; a random access memory (RAM); a read-only memory (ROM); an erasable programmable read-only memory (EPROM, Flash, MRAM, FeRAM, or phase change memory); an optical fiber; a portable compact disc; an optical storage device; a magnetic storage device; or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device, [0069]). The examiner notes that the “non-transitory computer readable storage medium” is not being claimed. Instead the examiner notes that it is the “computer program product storing instructions” in the “non-transitory computer readable storage medium” that is being claimed and therefore the instructions stored on the medium and not the medium itself. The claimed apparatus appears to include elements which could be interpreted as including only software. Software is not one of the four categories of invention and therefore these claims are not statutory. Software is not a series of steps or acts and thus is not a process. Software is not a physical article or object and as such is not a machine or manufacture. Software is not a combination of substances and therefore not a composition of matter. Since the specification describes "a computer program product" as comprising both transitory and non-transitory media, the claim encompasses both and is therefore non-statutory. The examiner suggests amending the claim(s) to read as a "a non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, cause the processors to" and amending the specification to remove the term “non-transitory” so as to not redefine a “non-statutory computer-readable medium” to include non-statutory embodiments. Allowable Subject Matter Claims 1-20, 22-25, and 27 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Prior art was not found that explicitly teaches or fairly suggests “distributing, within the processor core, the one or more consistency units” in combination with “executing instructions, by the processor core, in an architecturally defined mode”, “detecting at least one error in the one or more consistency units that were distributed”, and “switching the processor core to a safe mode upon detection of the at least one error in the one or more consistency units”, as outlined in independent claims 1 and 27. The remaining claims, not specifically mentioned, are allowed because they are dependent upon one of the claims mentioned above. These limitations are considered allowable only in combination with all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 2/10/26 have been fully considered but they are not persuasive. In response to applicant’s argument (see p. 6 of remarks) that the applicant has amended claim 26 in accordance with examiner’s recommendation, the examiner respectfully disagrees. The examiner notes that the “non-transitory computer readable storage medium” is not being claimed. Instead the examiner notes that it is the “computer program product storing instructions” in the “non-transitory computer readable storage medium” that is being claimed and therefore the instructions stored on the medium and not the medium itself. The claimed apparatus appears to include elements which could be interpreted as including only software. Conclusion Rahbar (U.S. Patent No. 12,450,342) discloses using verification cores in an integrated circuit device that can be used to perform address checks and generate an alarm signal (col. 10, ln. 19-65, fig. 3, 5). Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA P LOTTICH whose telephone number is (571)270-3738. The examiner can normally be reached Mon - Fri, 9:00am - 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 5712723655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSHUA P LOTTICH/ Primary Examiner, Art Unit 2113
Read full office action

Prosecution Timeline

May 17, 2024
Application Filed
Sep 10, 2025
Non-Final Rejection mailed — §101
Feb 10, 2026
Response Filed
Apr 03, 2026
Final Rejection mailed — §101
Sep 01, 2026
Request for Continued Examination
Sep 03, 2026
Response after Non-Final Action
Sep 11, 2026
Non-Final Rejection mailed — §101 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12748648
SYSTEMS AND METHODS FOR DETERMINING ERRORS DURING EXECUTION OF MULTIPLE APPLICATIONS
1y 10m to grant Granted Sep 29, 2026
Patent 12711051
ERROR CHECKING FOR CODE
2y 11m to grant Granted Aug 18, 2026
Patent 12711009
DETECTING AND REPAIRING RELIABILITY ISSUES IN OPERATING SYSTEMS AND APPLICATIONS USING A GENERATIVE ARTIFICIAL INTELLIGENCE SYSTEM
2y 9m to grant Granted Aug 18, 2026
Patent 12711010
AUTODETECTION AND REMEDIATION OF HIGH PROCESSOR USAGE AT NETWORK DEVICES
2y 1m to grant Granted Aug 18, 2026
Patent 12699621
ENHANCED TECH SUPPORT BASED ON CUSTOMER FEEDBACK
2y 6m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
94%
With Interview (+3.5%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 780 resolved cases by this examiner. Grant probability derived from career allowance rate.

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