Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 8, and 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1).
Regarding independent claim 1, Li teaches a manufacturing method of an integrated structure of a semiconductor integrated structure having high and low voltage devices and a capacitor ([0018], “The PMOS and NMOS transistors may provide low voltage functionality including logic/memory devices and input/output devices, and high voltage functionality including power management devices…FIGS. 1A to 1O may also include…capacitors…”), comprising: forming a bottom thermal oxide layer on a substrate, wherein the bottom thermal oxide layer completely covers a high voltage device area, a low voltage device area ([0021], “The filled trench may have a multi-layer structure such as a thermal oxide liner layer…”); forming a high voltage well in the substrate of the high voltage device area ([0031], “Then, high-voltage p-type implanted regions (HVPBs) 158 are formed in the DPW 130…”); forming a chemical vapor deposition (CVD) oxide layer that completely covers the bottom thermal oxide layer (Fig. 1L, 210’; [0045], “the RP layer 210′ is formed of a dielectric layer such as silicon dioxide using chemical vapor deposition (CVD)…”); forming a polysilicon hard mask layer that completely covers the CVD oxide layer ([0030], “In still some other embodiments, a hard mask layer may be used and formed on the conductive film 164′.”); etching the polysilicon hard mask layer to simultaneously form a high voltage polysilicon hard mask in the high voltage device area ([0032], “The gate dielectric layer 162 and the gate electrode 164 formed on the semiconductor substrate 110 are then patterned to form a plurality of gate structures using a process including photolithography patterning and etching.”); etching the CVD oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form a high voltage CVD oxide region in the high voltage device area ([0046], “the RP layer 210′ (see FIG. 1L) is partially etched away, leaving the RP layer 210 over at least a portion of the gate structure…”); forming a low voltage well in the substrate of the low voltage device area (Fig. 1D, 154, 156; [0026], “Subsequently, shallow low-voltage p-type wells (SHPs) 156a, 156b, and 156c are formed in the semiconductor substrate 110 and near the top surface…”); etching the bottom thermal oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form a high voltage bottom thermal oxide region in the high voltage device area ([0030], “…optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, using chemical mechanical polishing (CMP) processing to etch back and planarize…”); forming a high voltage gate oxide layer over the high voltage device area on the substrate; forming a low voltage gate oxide layer over the low voltage device area on the substrate ([0028], “The gate dielectric film 162′ may include a silicon oxide layer.”); forming a gate polysilicon layer, connected and fully covering the high voltage gate oxide layer, the low voltage gate oxide layer ([0029], “The conductive film 164′ may include a doped polycrystalline silicon (or polysilicon).”); and etching the gate polysilicon layer to simultaneously form a high voltage gate in the high voltage device area, a low voltage gate in the low voltage device area, ([0032], “The gate dielectric layer 162 and the gate electrode 164 formed on the semiconductor substrate 110 are then patterned to form a plurality of gate structures using a process including photolithography patterning and etching.”). However, Li does not teach forming a bottom thermal oxide layer on a substrate, wherein the bottom thermal oxide layer completely covers…a capacitor area of the substrate, etching the polysilicon hard mask layer to simultaneously form…a first electrode plate in the capacitor area, etching the CVD oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form… a capacitor CVD oxide region in the capacitor area, etching the bottom thermal oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form…a bottom thermal oxide region in the capacitor area, and etching the gate polysilicon layer to simultaneously form…a second electrode plate in the capacitor area.
However, in the same field of endeavor, Lin teaches forming a bottom thermal oxide layer on a substrate, wherein the bottom thermal oxide layer completely covers…a capacitor area of the substrate (Fig. 2A, 206; [0019], “As also shown in FIG. 2A, a dielectric layer 206 can be formed on the surface layer 202, such as by growing a thermal oxide layer on the surface layer 202.”); etching the polysilicon hard mask layer to simultaneously form…a first electrode plate in the capacitor area ([0028], “For example, the plurality of trenches 410 can be formed by etching (e.g., plasma dry etching) to remove the oxide layer 406 and a portion of the ESS layer through a patterned masking layer 412.”, [0035], “The back side metal layer 430 can be deposited on the bottom side of the wafer to provide bottom plate contact for the trench capacitor 440.”); etching the CVD oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form…a capacitor CVD oxide region in the capacitor area (Fig. 4F, 422; [0033], “Examples of dielectric materials to form the inter-layer dielectric layer 422 include TEOS-derived oxide layers…”, [0034], “For example, the inter-layer dielectric layer 422 can be patterned and etched…”); etching the bottom thermal oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form…a bottom thermal oxide region in the capacitor area (Fig. 2F, 206; [0024], “…have been etched back to expose a surface of the dielectric layer 206.”); and etching the gate polysilicon layer to simultaneously form…a second electrode plate in the capacitor area (Fig. 4D, 418, 420; [0031], “The undoped polysilicon layer 420 can be formed by depositing polysilicon (e.g., using an LPCVD process) on the dielectric layer 418 to fill the trenches 410. For example, the undoped polysilicon layer 418 that fills the trenches is configured to operate a top plate of the capacitor being formed.”, [0032], “As shown in FIG. 4D, the undoped polysilicon layer 420 can be removed from the top surface by an etching process (e.g., plasma dry etching) to expose the dielectric layer 418 and the multi-layer stack…”).
Therefore, it would have been obvious for one of ordinary skill in the art to combine the high and low voltage areas of Li with the capacitor of Lin so as to implement a capacitor into the integrated circuit (Li, [0018]).
Regarding dependent claim 7, Li, as previously modified by Lin, teaches the manufacturing method of claim 1, and further teaches wherein the high voltage gate is in direct contact with the high voltage polysilicon hard mask (Fig. 1F, 164’, 162’, Fig. 1G, 160; [0030], “In still some other embodiments, a hard mask layer may be used and formed on the conductive film 164′.”, [0032], “The gate dielectric film 162′ and the conductive film 164′ in FIG. 1F are further patterned to form a gate structure 160 on the semiconductor substrate 110.”).
Regarding dependent claim 8, Li, as previously modified by Lin, teaches the manufacturing method of claim 1, and further teaches further comprising: after forming the high voltage gate, the low voltage gate, and the second electrode plate, forming two high voltage spacers corresponding to and connected on either side of the high voltage gate, and two low voltage spacers corresponding to and connected on either side of the low voltage gate (Fig. 1I, 170; [0036], “…sidewall spacers 170 are formed on opposite sides of the gate structure 160.”).
Regarding dependent claim 10, Li, as previously modified by Lin, teaches the manufacturing method of claim 1, and further teaches further comprising: simultaneously forming a high voltage source and a high voltage drain in the high voltage device area, and a low voltage source and a low voltage drain in the low voltage device area (Fig. 1J, 184a,b,c; [0037], “…N-type source/drain region 184a, N-type pick-up region 184b, and N-type source/drain region 184c are formed in the N-wells or P-wells.”).
Regarding dependent claim 11, Li, as previously modified by Lin, teaches the manufacturing method of claim 10, and further teaches further comprising: using a silicidation metal process step to simultaneously form a plurality of silicide metal layers corresponding to the upper surfaces of the high voltage gate, the high voltage source, the high voltage drain, the low voltage gate, the low voltage source, the low voltage drain, the first electrode plate, and the second electrode plate (Fig. 1N, 220; [0047], “Metal alloy layers 220 may be formed by silicidation, such as salicide, in which a metal material is formed next to a Si structure, then the temperature is raised to anneal and cause a reaction between underlying silicon and the metal so as to form silicide, and the un-reacted metal is etched away.”).
Regarding dependent claim 12, Li, as previously modified by Lin, teaches the manufacturing method of claim 1, and further teaches further comprising: forming an inter-layer dielectric (ILD) layer on the substrate, completely covering the high voltage gate, the low voltage gate, and the second electrode plate (Fig. 1O, 230; [0048], “An interlayer dielectric (ILD) 230 is formed above the structure in FIG. 1N.”).
Regarding dependent claim 13, Li, as previously modified by Lin, teaches the manufacturing method of claim 12, and further teaches further comprising forming a plurality of electrical contact plugs in the ILD layer, electrically connecting the multiple silicide metal layers (Fig. 1O, 242, 244, 246, 248, 252, and 254; [0049], “Then, a plurality of contacts 242, 244, 246, 248, 252, and 254 are formed in the ILD 230.”).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Jeon (US 20020017683 A1).
Regarding dependent claim 2, Li, as previously modified by Lin, teaches the manufacturing method of claim 1. However, as previously combined, they do not teach wherein the step of forming the low voltage well in the substrate of the low voltage device includes: using an ion implantation process step, with the bottom thermal oxide layer serving as a sacrificial layer, and accelerating ions to penetrate the sacrificial layer to implant into the low voltage device area to form the low voltage well.
However, in the same field of endeavor, Jeon teaches using an ion implantation process step, with the bottom thermal oxide layer serving as a sacrificial layer, and accelerating ions to penetrate the sacrificial layer to implant into the low voltage device area to form the low voltage well (Fig. 15, 601, 610, 608; [0076], “Referring to FIG. 15, first, a thermal oxide layer 601 having a thickness of about 2000 to 10000 .ANG. to serve as an ion buffer layer is formed on a p.sup.--type semiconductor substrate 601. A photoresist layer pattern 702 for forming an n.sup.+-type buried layer 608 is formed by exposure and development using a typical lithographic technique. Next, n-type impurity ions, for example, arsenic (As) ions or antimony (Sb) ions, are implanted using the photoresist layer pattern 702 as an ion implantation mask. After the photoresist layer pattern 702 is removed, an n.sup.+-type buried layer 608 is formed in each of the high voltage p-type MOS transistor 631 and the low voltage region 610 by thermal oxidation and thermal diffusion.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the ion implantation step of Jeon so as to implant p or n type ions into the low voltage region.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Lee (US 20130210222 A1).
Regarding dependent claim 3, Li, as previously modified by Lin, teaches the manufacturing method of claim 1. However, as previously combined, they do not teach wherein the step of etching the CVD oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form the high voltage CVD oxide region in the high voltage device area and the capacitor CVD oxide region in the capacitor area includes: using a wet etching process step to etch the CVD oxide layer.
However, in the same field of endeavor, Lee teaches using a wet etching process step to etch the CVD oxide layer ([0098], “…in a wet etching process using an HF-containing etchant (e.g., 200:1 diluted HF solution), the conventional CVD layer (e.g., TEOS) may have an etch rate of about 80 .ANG./min…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the wet etch of Lee so as to remove a portion of the CVD layer (Lee, [0098]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Yu (US 20060006453 A1).
Regarding dependent claim 4, Li, as previously modified by Lin, teaches the manufacturing method of claim 1. However, as previously combined, they do not teach wherein the step of etching the bottom thermal oxide layer using the high voltage polysilicon hard mask and the first electrode plate as etching barriers to simultaneously form the high voltage bottom thermal oxide region in the high voltage device area and the bottom thermal oxide region in the capacitor area includes: using a wet etching process step to etch the bottom thermal oxide layer, such that the high voltage side wall of the high voltage bottom thermal oxide region and the capacitor side wall of the bottom thermal oxide region each have an inclined angle with respect to the upper surface of the substrate.
However, in the same field of endeavor, Yu teaches using a wet etching process step to etch the bottom thermal oxide layer, such that the high voltage side wall of the high voltage bottom thermal oxide region and the capacitor side wall of the bottom thermal oxide region each have an inclined angle with respect to the upper surface of the substrate (Fig. 2, 14; [0013], “However, the tunnel insulating layer 14 is generally formed by wet etching a thermal oxide layer (not shown) to expose the substrate 10… Accordingly, a profile of the sidewall of the tunnel insulating layer 14 becomes inclined.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the wet etching process of Yu so as to “degrade an efficiency” of the device programming (Yu, [0013]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Kim (US 20100163984 A1).
Regarding dependent claim 5, Li, as previously modified by Lin, teaches the manufacturing method of claim 1. However, as previously combined, they do not teach further comprising: after forming the polysilicon hard mask layer, using an ion implantation process step to accelerate N-type or P-type ions to implant into the polysilicon hard mask layer.
However, in the same field of endeavor, Kim teaches using an ion implantation process step to accelerate N-type or P-type ions to implant into the polysilicon hard mask layer (Fig. 2B, 16; [0024], “Then, as shown in FIG. 2B, p-type impurity ions are implanted in a predetermined dose…using the polysilicon hard mask 16 as an ion-implantation mask.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the ion implantation process of Kim so as to form a p-type body region and/or an n-type body region (Kim, [0024]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Ke (US 20240136348 A1).
Regarding dependent claim 6, Li, as previously modified by Lin, teaches the manufacturing method of claim 1. However, as previously combined, they do not teach further comprising: after forming the polysilicon hard mask layer, using an ion implantation process step to accelerate N-type or P-type ions to implant into the polysilicon hard mask layer.
However, in the same field of endeavor, Ke teaches using an ion implantation process step to accelerate N-type or P-type ions to implant into the polysilicon hard mask layer (Fig. 4F, 441; [0068], “The phosphorus ions are used to implant through the N-plus hard mask for forming the plurality of N-plus regions 441.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the ion implantation process of Ke so as to form N+ regions.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Jeon (US 20130320405 A1, hereinafter Jeon2).
Regarding dependent claim 9, Li, as previously modified by Lin, teaches the manufacturing method of claim 8. However, as previously combined, they do not teach further comprising: after forming the high voltage gate, the low voltage gate, and the second electrode plate, forming two capacitor spacers corresponding to and connected on either side of the second electrode plate.
However, in the same field of endeavor, Jeon2 teaches forming two capacitor spacers corresponding to and connected on either side of the second electrode plate (Fig. 6B, 52, [0084], “The inner capacitor spacers 51 may be conformally formed on sidewalls of the capacitor insulating layer 32 and sidewalls of the capacitor electrode 42.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the capacitor spacers of Jeon2 so as to cover the sidewalls of the electrode (Jeon2, [0084]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20210367074 A1) in further view of Lin (US 20220416014 A1) and Hsiung (US 20230170262 A1).
Regarding dependent claim 14, Li, as previously modified by Lin, teaches the manufacturing method of claim 1. However, as previously combined, they do not teach further comprising: forming a high voltage body region in the high voltage well of the high voltage device area, wherein the high voltage source is located in the high voltage body region.
However, in the same field of endeavor, Hsiung teaches forming a high voltage body region in the high voltage well of the high voltage device area, wherein the high voltage source is located in the high voltage body region (Fig. 1G, 15, 21; [0010], “…wherein the high voltage source is located in the body region…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method as described by the combination of Li and Lin with the high voltage body region of Hsiung so as to “provide an inversion current channel of the high voltage device” (Hsiung [0036]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20240047574 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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