Prosecution Insights
Last updated: April 19, 2026
Application No. 18/666,999

POWER SELECTION CIRCUIT, DISPLAY PANEL, AND DISPLAY APPARATUS

Non-Final OA §102§103
Filed
May 17, 2024
Examiner
SUTEERAWONGSA, JARURAT
Art Unit
2623
Tech Center
2600 — Communications
Assignee
Kunshan Go Visionox Opto Electronics Co. Ltd.
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
99%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
283 granted / 427 resolved
+4.3% vs TC avg
Strong +34% interview lift
Without
With
+33.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
24 currently pending
Career history
451
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
74.1%
+34.1% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 427 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4-9, 11, 15-16, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0241688 A1 to Yin (Yin 688). As to claim 1, Yin 688 discloses Yin discloses a power selection circuit (20) (Figs. 1-2, 4, 6, 8, Par. 44) comprising a voltage signal line (electrode connecting 20 and L) (Figs. 1-2, 4, 6, 8, Par. 44), the voltage signal line (electrode connecting 20 and L) being configured to transmit a voltage signal to a first electrode of a light-emitting sub-pixel (cathode of L) (Figs. 1-2, 4, 6, 8, Par. 44) and control at least two groups of light-emitting sub-pixels to emit light group by group (aa_1, aa_2, aa_3, aa_4) (Figs. 15-16, Par. 134); wherein one group of light-emitting sub-pixels (aa_1, aa_2, aa_3, aa_4) comprises at least one row of light-emitting sub-pixels or at least one row of light-emitting sub-pixel units (Figs. 15-16, Par. 134), and one of the light-emitting sub-pixel units comprises at least two different light-emitting sub-pixels (Figs. 15-16, Par. 134). As to claim 4, Yin 688 discloses at least part of the at least two different light-emitting sub-pixels are located in different rows (Figs. 15-16, Par. 134). As to claim 5, Yin 688 discloses a first signal module (M2) (Fig. 1, Par. 57), the voltage signal line comprising a first voltage signal line (ELVSS) (Figs. 1-2, 4, 6, 8, Pars. 44, 57); a first terminal of the first signal module (M2) being connected to the first voltage signal line (ELVSS) Figs. 1-2, 4, 6, 8, Pars. 44, 57), a second terminal of the first signal module (M2) being connected to first electrodes (cathode of L) of one group of light-emitting sub-pixels (Figs. 1-2, 4, 6, 8, Pars. 44, 57), and a control terminal of the first signal module (gate of M2) being connected to a first control signal line (EM2) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58); wherein in a light-emitting stage, a voltage signal transmitted in the first voltage signal line (ELVSS) is less than a difference between a second electrode voltage of the light-emitting sub-pixel (anode of L) and a turn-on voltage of the light-emitting sub-pixel (10) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58). As to claim 6, Yin 688 discloses a second signal module (M1) (Fig. 1, Par. 57), the voltage signal line comprising a second voltage signal line (ELVDD at source of M1) (Figs. 1-2, 4, 6, 8, Pars. 44, 57); a first terminal of the second signal module (M1) being connected to the second voltage signal line (ELVDD at source of M1) (Figs. 1-2, 4, 6, 8, Pars. 44, 57), a second terminal of the second signal module (M1) being connected to the second terminal of the first signal module (M2) ) (Figs. 1-2, 4, 6, 8, Pars. 44, 57), and a control terminal of the second signal module (gate of M1) being connected to a second control signal line (EM1) ) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), wherein in a non-light-emitting stage, a voltage signal transmitted in the second voltage signal line (ELVDD at source of M1) is greater than the difference between the second electrode voltage of the light-emitting sub-pixel (anode of L) and the turn-on voltage of the light-emitting sub-pixel (10) (Figs. 1-2, 4, 6, 8, Pars. 44, 57). As to claim 7, Yin 688 discloses the first signal module (M2) comprises a first transistor (M2) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), a first electrode of the first transistor (M2) is connected to the first voltage signal line (ELVSS) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), a second electrode of the first transistor is connected to the first electrodes of one group of light-emitting sub-pixels (L) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), and a gate of the first transistor (M2) is connected to the first control signal line (EM2) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58); and the second signal module (M1) comprises a second transistor (M1) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), a first electrode of the second transistor (M1) is connected to the second voltage signal line (ELVDD) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), a second electrode of the second transistor (M1) is connected to the second electrode of the first transistor (M2) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58), and a gate of the second transistor (M1) is connected to the second control signal line (EM1) (Figs. 1-2, 4, 6, 8, Pars. 44, 57-58). As to claim 8, Yin 688 discloses a type of the first transistor (M2) is opposite to a type of the second transistor (M1) (Figs. 6, 8, Par. 90), and a signal in the first control signal line and a signal in the second control signal line are a same signal (EM1 of Figs. 6, 8, Par. 90); the first control signal line and the second control signal line are a same signal line (Figs. 6-9, Par. 90). As to claim 9, Yin 688 discloses a type of the first transistor (M2) is the same as a type of the second transistor (M1) (Figs. 2, 4, Par. 59), and a signal in the first control signal line and a signal in the second control signal line are opposite signals (Figs. 2-3, Par. 59). As to claim 11, Yin 688 discloses a plurality of groups of light-emitting sub-pixels arranged in an array (Figs. 15-16, Pars. 134, 138), each group of light-emitting sub-pixels (aa_1, aa_2, aa_3, aa_4) comprising at least one row of light-emitting sub-pixels or at least one row of light-emitting sub-pixel units (Figs. 15-16, Pars. 134, 138), one of the light-emitting sub-pixel units comprising at least two different light-emitting sub-pixels (Figs. 15-16, Pars. 134, 138), first electrodes of the light-emitting sub-pixels in a same group being electrically connected (Figs. 15-16, Pars. 134, 138), and first electrodes of the light-emitting sub-pixels in different groups being insulated from each other (Figs. 15-16, Pars. 134, 138); wherein one power selection circuit is connected to the first electrodes of one group of light-emitting sub-pixels (Figs. 15-16, Pars. 134, 138). As to claim 20, see claim 11 rejection above. Yin 688 further discloses a display apparatus (OLED Display), comprising the display panel (Par. 20). As to claim 15, Yin discloses the display panel comprises a display region (AA) and a non-display region (area surrounding AA) (Figs. 10, 12, Pars. 107, 109), the light-emitting sub-pixels (10) are located in the display region (AA) (Figs. 10, 12, Pars. 107, 109), and the power selection circuit (20) is located in the non-display region (area surrounding AA) (Figs. 10, 12, Pars. 107, 109) As to claim 16, Yin 688 discloses the non-display region is located on at least one side of the display region (Figs. 10, 12, Pars. 107, 109). Claim(s) 1 and 5-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0335234 A1 to Yin. As to claim 1, Yin discloses a power selection circuit (22, 24) (Figs. 1A, 3A, 5, Pars. 42-43), comprising a voltage signal line (at OTG) (Figs. 1A, 3A, 5, Pars. 42-43), the voltage signal line (at OTG) being configured to transmit a voltage signal to a first electrode (cathode of OLED) of a light-emitting sub-pixel (20) (Figs. 1A, 3A, 5, Pars. 42-43), and control at least two groups of light-emitting sub-pixels to emit light group by group (Figs. 1A, 3A, 5, Pars. 42-43, rows are driven sequentially); wherein one group of light-emitting sub-pixels comprises at least one row of light-emitting sub-pixels or at least one row of light-emitting sub-pixel units (Figs. 1A, 3A, 5, Pars. 42-43), and one of the light-emitting sub-pixel units comprises at least two different light-emitting sub-pixels (Figs. 1A, 3A, 5, Pars. 42-43, multiple pixels in a row). As to claim 5, Yin discloses a first signal module (14) (Fig. 1, Par. 41), the voltage signal line (OTG) comprising a first voltage signal line (ELVss) (Fig. 1, Par. 41); a first terminal of the first signal module (14) being connected to the first voltage signal line (ELVss) (Fig. 1, Par. 41), a second terminal of the first signal module (14) being connected to first electrodes (cathode of OLED) of one group of light-emitting sub-pixels (Fig. 1, Par. 41), and a control terminal (gate of T6) of the first signal module (14) being connected to a first control signal line (EM) (Fig. 1, Par. 41); wherein in a light-emitting stage, a voltage signal transmitted in the first voltage signal line (ELVss) is less than a difference between a second electrode voltage (anode of OLED) of the light-emitting sub-pixel and a turn-on voltage of the light-emitting sub-pixel (Fig. 1, Par. 42). As to claim 6, Yin discloses comprising a second signal module (12) (Fig. 1, Par. 41), the voltage signal line (OTG) comprising a second voltage signal line (ELVdd) (Fig. 1, Par. 41); a first terminal of the second signal module (OTG) being connected to the second voltage signal line (ELVdd) (Fig. 1, Par. 41), a second terminal of the second signal module being connected to the second terminal of the first signal module (14) (Fig. 1, Pars. 41-42), and a control terminal (gate of T5) of the second signal module (12) being connected to a second control signal line (SEN) (Fig. 1, Par. 41); wherein in a non-light-emitting stage, a voltage signal transmitted in the second voltage signal line (ELVdd) is greater than the difference between the second electrode voltage (anode) of the light-emitting sub-pixel and the turn-on voltage of the light-emitting sub-pixel (Fig. 1, Par. 42). As to claim 7, Yin discloses comprising the first signal module (14) comprises a first transistor (T6) (Fig. 1, Par. 41), a first electrode of the first transistor is connected to the first voltage signal line (Fig. 1, Par. 41), a second electrode of the first transistor is connected to the first electrodes of one group of light-emitting sub-pixels (Fig. 1, Par. 41), and a gate of the first transistor is connected to the first control signal line (EM) (Fig. 1, Par. 41); and the second signal module (12) comprises a second transistor (T5) (Fig. 1, Par. 41), a first electrode of the second transistor is connected to the second voltage signal line(Fig. 1, Par. 41), a second electrode of the second transistor (T5) is connected to the second electrode of the first transistor (T6) (Fig. 1, Par. 41), and a gate of the second transistor is connected to the second control signal line (SEN) (Fig. 1, Par. 41). As to claim 8, Yin discloses comprising a type of the first transistor is opposite to a type of the second transistor (Fig. 1, Par. 39), and a signal in the first control signal line and a signal in the second control signal line are a same signal; the first control signal line and the second control signal line are a same signal line (Figs. 3-6, Pars. 39, 51-52; it is inherent that when using p-type and n-type transistors with the same control signal, one signal will turn on while the other will turn off). As to claim 9, Yin discloses comprising a type of the first transistor is the same as a type of the second transistor (Fig. 1, Par. 39), and a signal in the first control signal line and a signal in the second control signal line are opposite signals (Figs. 3-6, Pars. 51-52). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0335234 A1 to Yin and US 11,763,747 to Zhou et la. (Zhou). As to claim 2, Yin does not expressly disclose a voltage signal less than a difference between a second electrode voltage of the light-emitting sub-pixel and a turn-on voltage of the light-emitting sub-pixel is intermittently transmitted in the voltage signal line. Zhou discloses a voltage signal less than a difference between a second electrode voltage of the light-emitting sub-pixel and a turn-on voltage of the light-emitting sub-pixel is intermittently transmitted in the voltage signal line (Fig. 2, Col. 12, lines 9-17). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Yin with the teaching of Zhou to prolong the life of the transistor as suggested by Zhou (Col. 12, lines 20-22). As to claim 3, Yin as modified discloses the voltage signal less than the difference between the second electrode voltage of the light-emitting sub-pixel and the turn-on voltage of the light-emitting sub-pixel (Zhou’s Figs. 2-3, Col. 12, lines 9-17) and a voltage signal greater than the difference between the second electrode voltage of the light-emitting sub-pixel and the turn-on voltage of the light-emitting sub-pixel are transmitted in the voltage signal line in a time-sharing manner (Zhou’s Figs. 2-3, Col. 12, lines 9-17). See claim 2 motivation above. Claim(s) 4, 11, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0335234 A1 to Yin and US 2023/0196979 A1 to Cok. As to claim 4, Yin does not expressly disclose at least part of the at least two different light-emitting sub-pixels are located in different rows. Cok discloses at least part of the at least two different light-emitting sub-pixels are located in different rows (Figs. 5-6, 8, 10-12, 25-26,, Pars. 116-117). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Yin with the teaching of Cok to transmit at a higher rate as suggested by Cok (Par. 116). As to claim 11, Yin discloses a display panel (Fig. 1, Par. 38) comprising power selection circuit (22, 24) of claim 1 (Figs. 1A, 3A, 5, Pars. 42-43); and a plurality of groups of light-emitting sub-pixels arranged in an array(Figs. 1A, 3A, 5, Pars. 42-43). Yin does not expressly disclose each group of light-emitting sub-pixels comprising at least one row of light-emitting sub-pixels or at least one row of light-emitting sub-pixel units, one of the light-emitting sub-pixel units comprising at least two different light-emitting sub-pixels, first electrodes of the light-emitting sub-pixels in a same group being electrically connected, and first electrodes of the light-emitting sub-pixels in different groups being insulated from each other; wherein one power selection circuit is connected to the first electrodes of one group of light-emitting sub-pixels. Cok discloses a plurality of groups (70) of light-emitting sub-pixels arranged in an array (Fig. 25, Pars. 116-117), each group of light-emitting sub-pixels comprising at least one row of light-emitting sub-pixels or at least one row of light-emitting sub-pixel units (Fig. 25, Pars. 116-117), one of the light-emitting sub-pixel units comprising at least two different light-emitting sub-pixels(Fig. 25, Pars. 116-117), first electrodes of the light-emitting sub-pixels in a same group being electrically connected (Fig. 25, Pars. 116-117), and first electrodes of the light-emitting sub-pixels in different groups being insulated from each other (Fig. 25, Pars. 116-117); wherein one power selection circuit is connected to the first electrodes of one group of light-emitting sub-pixels (Fig. 25, Pars. 116-117). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Yin with the teaching of Cok to transmit at a higher rate as suggested by Cok (Par. 116). As to claim 20, see claim 11 rejection above. Yin further discloses display apparatus (OLED Display), comprising the display panel (Figs. 1A, 3A, 5, Pars. 42-43). As to claim 15, Yin as modified discloses the display panel comprises a display region and a non-display region (Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75), the light-emitting sub-pixels are located in the display region ((Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75), and the power selection circuit is located in the non-display region (Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75). See claim 11 motivation above. As to claim 16, Yin as modified discloses the non-display region is located on at least one side of the display region (Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75). See claim 11 motivation above. As to claim 17, Yin as modified discloses the non-display region is located on two opposite sides of the display region (Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75), and the non-display region on each side comprises the power selection circuit (Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75). It would have been obvious to try with a reasonable expectation of success to use a power selection circuit on each non-display region opposite from each other to transmit at a higher rate as suggested by Cok (Par. 116). As to claim 18, Yin as modified discloses the first electrodes of the light-emitting sub-pixels in a same row of light-emitting sub-pixels or light-emitting sub-pixel units are connected to a plurality of power selection circuits (Yin’s Figs. 1A, 3A, 5, Pars. 42-43, Cok’s Figs. 5-6, 8, 10-12, 25-26, 5, Pars. 75, 116-117). See claim 11 motivation above. As to claim 19, Yin as modified discloses the first electrodes of the light-emitting sub-pixels in a same row of light-emitting sub-pixels or light-emitting sub-pixel units are connected to two power selection circuits (Yin’s Figs. 1A, 3A, 5, Pars. 42-43, Cok’s Figs. 5-6, 8, 10-12, 25-26, 5, Pars. 75, 116-117), and in the two power selection circuits connected to the first electrodes of the light-emitting sub-pixels in a same row of light-emitting sub-pixels or light-emitting sub-pixel units (Yin’s Figs. 1A, 3A, 5, Pars. 42-43, Cok’s Figs. 5-6, 8, 10-12, 25-26, 5, Pars. 75, 116-117), one of the power selection circuits is located in the non-display region on one side of the display region (Yin’s Figs. 1A, 3A, 5, Pars. 42-43, Cok’s Figs. 5-6, 8, 10-12, 25-26, 5, Pars. 75, 116-117), and the other of the power selection circuits is located in the non-display region on the opposite side of the display region (Yin’s Figs. 1-1A, Pars. 58-59, Cok’s Figs. 5-6, 8, 10-12, 25-26, Par. 75). It would have been obvious to try with a reasonable expectation of success to use a power selection circuit on each non-display region opposite from each other to transmit at a higher rate as suggested by Cok (Par. 116). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0241688 A1 to Yin (Yin688) and US 2018/0182283 to Lim et al. (Lim). As to claim 10, Yin 688 does not expressly disclose a signal in the first control signal line and a signal in the second control signal line are both step-by-step shift signals; a signal duty cycle in the first control signal line and a signal duty cycle in the second control signal line are both adjustable. Lim discloses a signal in the first control signal line and a signal in the second control signal line are both step-by-step shift signals (see Lim’s Figs. 1, 3, 8 and [0066-0067, 0164]); a signal duty cycle in the first control signal line and a signal duty cycle in the second control signal line are both adjustable (see Lim’s Figs. 1, 3, 8 and [0066-0067, 0164]). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Yin 688 with the teaching of Lim to provide a display with a high quality display image as suggested by Lim (Par. 15). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0335234 A1 to Yin and US 2018/0182283 to Lim et al. (Lim). As to claim 10, Yin does not expressly disclose a signal in the first control signal line and a signal in the second control signal line are both step-by-step shift signals; a signal duty cycle in the first control signal line and a signal duty cycle in the second control signal line are both adjustable. Lim discloses a signal in the first control signal line and a signal in the second control signal line are both step-by-step shift signals (see Lim’s Figs. 1, 3, 8 and [0066-0067, 0164]); a signal duty cycle in the first control signal line and a signal duty cycle in the second control signal line are both adjustable (see Lim’s Figs. 1, 3, 8 and [0066-0067, 0164]). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Yin with the teaching of Lim to provide a display with a high quality display image as suggested by Lim (Par. 15). Claim(s) 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0335234 A1 to Yin and and US 2023/0196979 A1 to Cok; in view of US 2022/0115484 to Lu et al. (Lu). As to claim 12, Yin as modified discloses the first electrodes of the light-emitting sub-pixels in the light-emitting sub-pixels or the light-emitting sub-pixel units in adjacent rows in a same group are electrically connected (Cok’s Fig. 25, Pars. 116-117). See claim 1 motivation above. Yin as modified does not expressly disclose pixels are electrically connected through an isolation pillar. Lu discloses cathodes(34) of pixels (100A, 100B, 100C) are electrically connected through an isolation pillar (16) (Figs. 21-22, Pars. 86, see also Par. 92, the source and drain electrodes are respectively connected with the source and drain connection regions of the corresponding transistors through conductive pillars). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Yin with the teaching of Lu to as suggested by thereby forming an improved conductive connection between regions as suggested by Lu (Par. 92). As to claim 14, Yin as modified discloses the power selection circuit is electrically connected to the isolation pillar (Lu’s 16) (Yin’s Figs. 1A, 3A, 5, Pars. 42-43, Lu’s Figs. 21-22, Pars. 86, see also Par. 92); the isolation pillar comprises a metal isolation pillar (Lu’s Figs. 21-22, Pars. 86, see also Par. 92); and in a direction perpendicular to an extension direction of a single group of the light-emitting sub-pixels (Yin’s Figs. 1A, 3A, 5, Pars. 42-43, Lu’s Figs. 21-22, Pars. 86, see also Par. 92), a cross-sectional shape of a conductive part of the isolation pillar comprises a T shape or an inverted trapezoid (Lu’s Par. 100). See claim 12 motivation above. Allowable Subject Matter Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The allowable subject matter is: herein a partition groove is provided in the isolation pillar between the light-emitting sub-pixels in the light-emitting sub-pixels or the light-emitting sub-pixel units in different groups and adjacent rows, the partition groove being configured to divide the isolation pillar into a first sub-isolation pillar and a second sub-isolation pillar, the first sub-isolation pillar and the second sub-isolation pillar being insulated, the light-emitting sub-pixels in one row of the light-emitting sub-pixels or the light-emitting sub-pixel units in different groups and adjacent rows are electrically connected to the first sub-isolation pillar, and the light-emitting sub-pixels in the other row of the light-emitting sub-pixels or the light-emitting sub-pixel units in different groups and adjacent rows are electrically connected to the second sub-isolation pillar, of claim 13 with all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0274086 to Wang et al. teaches a display with in each of row of pixels connected to each emission control unit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARURAT SUTEERAWONGSA whose telephone number is (571)270-7361. The examiner can normally be reached Monday thru Thursday, 8:30AM to 6:00PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lun Yi Lao can be reached at 571-272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JARURAT SUTEERAWONGSA/Examiner, Art Unit 2621 /LUNYI LAO/Supervisory Patent Examiner, Art Unit 2621
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Prosecution Timeline

May 17, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
99%
With Interview (+33.7%)
3y 1m
Median Time to Grant
Low
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