DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 10/29/2025 has been entered. Applicant has amended claims 1, 4, 8, 9, 14, and 15. Applicant has cancelled claims 2 and 3. Applicant has added claims 21 and 22. Claims 1 and 4-22 are currently pending in the instant application.
Response to Arguments
Applicant’s arguments, see page 1, filed 10/29/2025, with respect to claims 4, 9 and 15 have been fully considered and are persuasive. The 35 U.S.C. 112(b) rejection of claims 4, 9, and 15 has been withdrawn.
Applicant’s arguments, see page 1, filed 10/29/2025, with respect to claims 1-7 have been fully considered and are persuasive. The 35 U.S.C 101 rejection of claims 1-7 has been withdrawn.
Applicant’s arguments, see pages 1-7, filed 10/29/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 102have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in further view of McMillen et al (US 2008/0270764). McMillen teaches the amended limitations as seen below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 4-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Billa et al (US 2021/0097082) in view McMillen et al (US 2008/0270764).
Regarding claim 1, Billa discloses:
1. A method comprising: compiling a set of regular expression patterns to generate an output file, wherein the output file comprises information related to a deterministic finite automaton (DFA) graph, including fall-through information indicative of whether a transition associated with any nodes of the DFA graph comprises a fall-through transition ([0012] In one example, a system comprises a data source storing data, a data processing unit (DPU) comprising an integrated circuit having programmable processor cores and a hardware-based regular expression (RegEx) engine, and a control node configured to generate a data flow graph for configuring the DPUs to execute the analytical operation to be performed on the data. The analytical operation specifies a query having at least one query predicate. A controller is configured to receive the data flow graph and, in response, configures the DPU to input the data as one or more data streams, and configure the RegEx engine to operate according to one or more deterministic finite automata (DFAs) or non-deterministic finite automata (NFA) to evaluate the query predicate against the data by applying one or more regular expressions to the one or more data streams.); and during processing of a payload, executing transitions associated with the DFA graph, including any fall-through transitions ([0149] After compilation, the loader stores data representing the DFA graph initially in external memory 210 or a different computer-readable storage medium for loading when needed for stream processing. In some examples, control block 202 may receive work units including instructions to retrieve at least a portion of a DFA graph from external memory 210 allocated and structurally arranged for buffer memory 204 by the loader following compilation of the regular expression. In response, control block 202 may retrieve the designated portion of the DFA graph from external memory 210 and store the portion of the DFA graph to one or more of buffer memory 204, and in some cases may preload certain nodes into high-speed, on-chip DFA caches 208, which may operate as L1 caches. Likewise, after one or more searches have been conducted, control block 202 may receive work units including instructions to clear one or more of DFA caches 208 and/or unload portions of DFAs from buffer memory 204. Furthermore, control block 202 may receive work units including instructions to initiate a search, e.g., indicating a payload to be searched using a loaded DFA graph. In some examples, a single work unit may represent both a command to load a DFA and to perform a search using the loaded DFA.).
Billa does not explicitly teach loading the output file into a memory associated with a regular expression (reqex) accelerator; andduring processing of a payload by the reqex accelerator, wherein executing transitions associated with the DFA graph comprises traversing along an edge of the DFA graph, and as part of traversing the edge along the DFA graph,consuming a portion of a payload being processed, and wherein the fall-through transition comprises traversing along an edge of the DFA graph without consuming any portion of the payload being processed.
McMillen teaches loading the output file into a memory associated with a regular expression (reqex) accelerator; andduring processing of a payload by the reqex accelerator,( [0023] In the embodiment of FIG. 1, a compiler 150 is depicted in communication with the state machine engine 100 (also referred to herein as the “system 100”). In one embodiment, the compiler 150 is configured to compile a plurality of regular expressions, or other strings that identify character patterns of interest, into a state machine, such as a DFA, for example, that is usable by the state machine engine 100 in evaluating the data stream 130. In the embodiment of FIG. 1, the compiler comprises a compression module 152 that is configured to reduce the memory requirements for storage of state transition instructions that are generated by the compiler.) wherein executing transitions associated with the DFA graph comprises traversing along an edge of the DFA graph, and as part of traversing the edge along the DFA graph,consuming a portion of a payload being processed, and wherein the fall-through transition comprises traversing along an edge of the DFA graph without consuming any portion of the payload being processed.( [0051] FIG. 7 is a table illustrating an exemplary memory allocation of certain states of the state machine of FIG. 5 without multi-character compression. As illustrated in FIG. 7, each of these states comprises at least two instruction words in the table of FIG. 7, including one or more instructions associated with transitions to next states (e.g., non-terminal states) and/or instructions for an action and/or token (e.g., terminal states), as well as a failure transition that indicates a next state that should be activated in response to not matching transition conditions of the respective states. Thus, with reference to State 1, there are four transition instructions, one for each of the transitions to non-terminal states of the state machine and one for the failure transition that is executed if none of the transition conditions for the non-terminal states are matched. As noted in the transition instruction column 720 of FIG. 7, the first transition instruction is to non-terminal state S2, which occurs if the current character in the input data string is “c” (see FIG. 5), the second transition instruction is to non-terminal state S18, which occurs if the current character in the input data string is “d” (see FIG. 5), and the third transition instruction is to non-terminal state S31, which occurs if the current character in the input data string is “z” (see FIG. 5). As shown in FIG. 7, each of the states S4 to S10 comprises two transitions slots in the memory structure, one for a transition instruction to a next state and one for a failure transition. Accordingly, for these seven transitions, 14 memory slots of the state machine main memory and/or cache memory are required.)
Accordingly, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to have modified the teachings of Billa to include loading the output file into a memory associated with a regular expression (reqex) accelerator; andduring processing of a payload by the reqex accelerator, wherein executing transitions associated with the DFA graph comprises traversing along an edge of the DFA graph, and as part of traversing the edge along the DFA graph,consuming a portion of a payload being processed, and wherein the fall-through transition comprises traversing along an edge of the DFA graph without consuming any portion of the payload being processed. It would
be advantageous reduce the memory requirements for storage as taught by McMiilen [0023].
Billa in view of McMillen teaches the method of independent claim 1, Billa further teaches the dependent claims below.
4. The method of claim 1, wherein the information indicative of whether a transition associated with any nodes of the DFA graph comprises a fall-through transition comprises a fall-through bit ([0243] In other examples, FINAL instructions push a result (Y/N or 1/0) to the result buffer based upon the results of the previously executed array comparison instructions but, upon a failure, do not empty the instruction stack such that NFA engines 216 execute any instructions previously pushed to a given instruction stack. As such, NFA engines 216 generate output data flow 244 to include an affirmative result upon a match and also a negative indication if the predicate is not satisfied by the current data unit of the input data stream. As such, in this example implementation, NFA engines 216 may output data flow 244 as a bitmap, e.g., where a 1 or Y is reported for a match and 0 or N is reported for mismatch, as shown in FIG. 17.).
5. The method of claim 1, wherein a DFA graph with fall-through transitions has fewer transitions than a DFA graph without fall-through transitions ([0158] In some examples, before evaluating payload data, DFA engines 206 may preload at least a portion of a DFA graph into buffer memory 204 from external memory 210 or a different computer-readable medium based on the memory allocation specified by the compiler for each node. Additionally, or alternatively, DFA engines 206 may preload a portion of the DFA graph into memory of a thread of the one of DFA engines 206. In particular, DFA engines 206 may be configured to receive a DFA LOAD work unit, including instructions to direct the DFA engine to load at least a portion of a DFA graph (e.g., a root of the DFA graph, and/or other portions of the DFA graph) into buffer memory 204 and/or memory of one of the threads of the DFA engines 206. The at least portion of the DFA graph may include a root node of the DFA graph and/or data representing one or more nodes and/or arcs of the nodes of the DFA graph. Likewise, DFA engines 206 may be configured to unload a loaded portion of a DFA graph from the thread memory and/or from buffer memory 204, e.g., in response to a DFA UNLOAD work unit. The DFA UNLOAD work unit may include instructions indicating that one or more loaded arcs of a DFA graph are to be removed from thread memory and/or buffer memory 204, and/or to unlock and clear a root buffer for a DFA graph from the thread memory and/or buffer memory 204.).
6. The method of claim 5, further comprising caching a larger amount of information for the DFA graph with fall-through transitions relative to the DFA graph without fall-through transitions. ([0243] In other examples, FINAL instructions push a result (Y/N or 1/0) to the result buffer based upon the results of the previously executed array comparison instructions but, upon a failure, do not empty the instruction stack such that NFA engines 216 execute any instructions previously pushed to a given instruction stack. As such, NFA engines 216 generate output data flow 244 to include an affirmative result upon a match and also a negative indication if the predicate is not satisfied by the current data unit of the input data stream. As such, in this example implementation, NFA engines 216 may output data flow 244 as a bitmap, e.g., where a 1 or Y is reported for a match and 0 or N is reported for mismatch, as shown in FIG. 17.).
The method of claim 1, wherein during compiling, fall-through transitions are added to the DFA graph while reducing a total number of transitions associated with the DFA graph ([0158] In some examples, before evaluating payload data, DFA engines 206 may preload at least a portion of a DFA graph into buffer memory 204 from external memory 210 or a different computer-readable medium based on the memory allocation specified by the compiler for each node. Additionally, or alternatively, DFA engines 206 may preload a portion of the DFA graph into memory of a thread of the one of DFA engines 206. In particular, DFA engines 206 may be configured to receive a DFA LOAD work unit, including instructions to direct the DFA engine to load at least a portion of a DFA graph (e.g., a root of the DFA graph, and/or other portions of the DFA graph) into buffer memory 204 and/or memory of one of the threads of the DFA engines 206. The at least portion of the DFA graph may include a root node of the DFA graph and/or data representing one or more nodes and/or arcs of the nodes of the DFA graph. Likewise, DFA engines 206 may be configured to unload a loaded portion of a DFA graph from the thread memory and/or from buffer memory 204, e.g., in response to a DFA UNLOAD work unit. The DFA UNLOAD work unit may include instructions indicating that one or more loaded arcs of a DFA graph are to be removed from thread memory and/or buffer memory 204, and/or to unlock and clear a root buffer for a DFA graph from the thread memory and/or buffer memory 204.).
21. (New) The method of claim 1, wherein the information related to the DFA graph is organized in the memory as slices including slots, and wherein each of the slots corresponds to a transition arc from one node to another node of the DFA graph. (0156)
22. (New) The method of claim 21, wherein each of the slots includes information concerning how many times the fall-through transition can be executed from the one to the another node of the DFA graph. (0156)
8. A method comprising: loading an object file into a memory associated with a regular expression (regex) accelerator, wherein the object file includes information related to a deterministic finite automaton (DFA) graph and fall-through information indicative of whether a transition associated with any nodes of the DFA graph comprises a fall-through transition; the regex accelerator receiving a payload for processing ([0012] In one example, a system comprises a data source storing data, a data processing unit (DPU) comprising an integrated circuit having programmable processor cores and a hardware-based regular expression (RegEx) engine, and a control node configured to generate a data flow graph for configuring the DPUs to execute the analytical operation to be performed on the data. The analytical operation specifies a query having at least one query predicate. A controller is configured to receive the data flow graph and, in response, configures the DPU to input the data as one or more data streams, and configure the RegEx engine to operate according to one or more deterministic finite automata (DFAs) or non-deterministic finite automata (NFA) to evaluate the query predicate against the data by applying one or more regular expressions to the one or more data streams.); and during processing of the payload, based on the fall-through information, executing transitions associated with the DFA graph without consuming a portion of the payload ([0149] After compilation, the loader stores data representing the DFA graph initially in external memory 210 or a different computer-readable storage medium for loading when needed for stream processing. In some examples, control block 202 may receive work units including instructions to retrieve at least a portion of a DFA graph from external memory 210 allocated and structurally arranged for buffer memory 204 by the loader following compilation of the regular expression. In response, control block 202 may retrieve the designated portion of the DFA graph from external memory 210 and store the portion of the DFA graph to one or more of buffer memory 204, and in some cases may preload certain nodes into high-speed, on-chip DFA caches 208, which may operate as L1 caches. Likewise, after one or more searches have been conducted, control block 202 may receive work units including instructions to clear one or more of DFA caches 208 and/or unload portions of DFAs from buffer memory 204. Furthermore, control block 202 may receive work units including instructions to initiate a search, e.g., indicating a payload to be searched using a loaded DFA graph. In some examples, a single work unit may represent both a command to load a DFA and to perform a search using the loaded DFA.). .
Billa in view of McMillen teaches the method of independent claim 8, Billa further teaches the dependent claims below.
9. The method of claim 8, wherein the information indicative of whether a transition associated with any nodes of the DFA graph comprises a fall-through transition comprises a fall-through bit. ([0243] In other examples, FINAL instructions push a result (Y/N or 1/0) to the result buffer based upon the results of the previously executed array comparison instructions but, upon a failure, do not empty the instruction stack such that NFA engines 216 execute any instructions previously pushed to a given instruction stack. As such, NFA engines 216 generate output data flow 244 to include an affirmative result upon a match and also a negative indication if the predicate is not satisfied by the current data unit of the input data stream. As such, in this example implementation, NFA engines 216 may output data flow 244 as a bitmap, e.g., where a 1 or Y is reported for a match and 0 or N is reported for mismatch, as shown in FIG. 17.).
10. The method of claim 8, wherein a DFA graph with fall-through transitions has fewer transitions than a DFA graph without fall-through transitions ([0158] In some examples, before evaluating payload data, DFA engines 206 may preload at least a portion of a DFA graph into buffer memory 204 from external memory 210 or a different computer-readable medium based on the memory allocation specified by the compiler for each node. Additionally, or alternatively, DFA engines 206 may preload a portion of the DFA graph into memory of a thread of the one of DFA engines 206. In particular, DFA engines 206 may be configured to receive a DFA LOAD work unit, including instructions to direct the DFA engine to load at least a portion of a DFA graph (e.g., a root of the DFA graph, and/or other portions of the DFA graph) into buffer memory 204 and/or memory of one of the threads of the DFA engines 206. The at least portion of the DFA graph may include a root node of the DFA graph and/or data representing one or more nodes and/or arcs of the nodes of the DFA graph. Likewise, DFA engines 206 may be configured to unload a loaded portion of a DFA graph from the thread memory and/or from buffer memory 204, e.g., in response to a DFA UNLOAD work unit. The DFA UNLOAD work unit may include instructions indicating that one or more loaded arcs of a DFA graph are to be removed from thread memory and/or buffer memory 204, and/or to unlock and clear a root buffer for a DFA graph from the thread memory and/or buffer memory 204.).
11. The method of claim 10, further comprising caching a larger amount of information for the DFA graph with fall-through transitions relative to the DFA graph without fall-through transitions. ([0156] DFA engines 206 also include respective processing units for comparing a current symbol of the payload data to labels for arcs from the current node of the DFA graph. The threads of each of DFA engines 206 may share a common processing unit, or the threads may each include a corresponding processing unit. In general, the processing unit determines a node to which to transition from the current node (i.e., the node to which the arc having a label matching the current symbol of the payload data points). ).
12. The method of claim 8, wherein during compiling, fall-through transitions are added to the DFA graph while reducing a total number of transitions associated with the DFA graph ([0158] In some examples, before evaluating payload data, DFA engines 206 may preload at least a portion of a DFA graph into buffer memory 204 from external memory 210 or a different computer-readable medium based on the memory allocation specified by the compiler for each node. Additionally, or alternatively, DFA engines 206 may preload a portion of the DFA graph into memory of a thread of the one of DFA engines 206. In particular, DFA engines 206 may be configured to receive a DFA LOAD work unit, including instructions to direct the DFA engine to load at least a portion of a DFA graph (e.g., a root of the DFA graph, and/or other portions of the DFA graph) into buffer memory 204 and/or memory of one of the threads of the DFA engines 206. The at least portion of the DFA graph may include a root node of the DFA graph and/or data representing one or more nodes and/or arcs of the nodes of the DFA graph. Likewise, DFA engines 206 may be configured to unload a loaded portion of a DFA graph from the thread memory and/or from buffer memory 204, e.g., in response to a DFA UNLOAD work unit. The DFA UNLOAD work unit may include instructions indicating that one or more loaded arcs of a DFA graph are to be removed from thread memory and/or buffer memory 204, and/or to unlock and clear a root buffer for a DFA graph from the thread memory and/or buffer memory 204.).
13. The method of claim 8, further comprising, compiling a set of regular expression patterns to generate the output file. ([0243] In other examples, FINAL instructions push a result (Y/N or 1/0) to the result buffer based upon the results of the previously executed array comparison instructions but, upon a failure, do not empty the instruction stack such that NFA engines 216 execute any instructions previously pushed to a given instruction stack. As such, NFA engines 216 generate output data flow 244 to include an affirmative result upon a match and also a negative indication if the predicate is not satisfied by the current data unit of the input data stream. As such, in this example implementation, NFA engines 216 may output data flow 244 as a bitmap, e.g., where a 1 or Y is reported for a match and 0 or N is reported for mismatch, as shown in FIG. 17.).
14. A method comprising: loading an object file into a memory associated with a regular expression (regex) accelerator, wherein the object file includes information related to a deterministic finite automaton (DFA) graph and fall-through information indicative of whether a transition associated with any nodes of the DFA graph comprises a fall-through transition; receiving a payload from a service external to the regex accelerator; during processing of the payload, based on the fall-through information, executing transitions associated with the DFA graph without consuming a portion of the payload ([0149] After compilation, the loader stores data representing the DFA graph initially in external memory 210 or a different computer-readable storage medium for loading when needed for stream processing. In some examples, control block 202 may receive work units including instructions to retrieve at least a portion of a DFA graph from external memory 210 allocated and structurally arranged for buffer memory 204 by the loader following compilation of the regular expression. In response, control block 202 may retrieve the designated portion of the DFA graph from external memory 210 and store the portion of the DFA graph to one or more of buffer memory 204, and in some cases may preload certain nodes into high-speed, on-chip DFA caches 208, which may operate as L1 caches. Likewise, after one or more searches have been conducted, control block 202 may receive work units including instructions to clear one or more of DFA caches 208 and/or unload portions of DFAs from buffer memory 204. Furthermore, control block 202 may receive work units including instructions to initiate a search, e.g., indicating a payload to be searched using a loaded DFA graph. In some examples, a single work unit may represent both a command to load a DFA and to perform a search using the loaded DFA.). ; and upon a successful match between the payload and at least one of the set of regular expression patterns, indicating a match [0157] The processing unit or the thread of the corresponding one of DFA engines 206 may then update the current node locator and the payload offset. The processing unit may continue this evaluation until either the entire set of payload data has been examined without finding a match, or a resulting node of the DFA graph is a matching node. In response to reaching a matching node, the thread of the one of DFA engines 206 may return data indicating that a match has been identified..
Billa in view of McMillen teaches the method of independent claim 14, Billa further teaches the dependent claims below.
15. The method of claim 14, wherein the information indicative of whether a transition associated with any nodes of the DFA graph comprises a fall-through transition comprises a fall-through bit. ([0243] In other examples, FINAL instructions push a result (Y/N or 1/0) to the result buffer based upon the results of the previously executed array comparison instructions but, upon a failure, do not empty the instruction stack such that NFA engines 216 execute any instructions previously pushed to a given instruction stack. As such, NFA engines 216 generate output data flow 244 to include an affirmative result upon a match and also a negative indication if the predicate is not satisfied by the current data unit of the input data stream. As such, in this example implementation, NFA engines 216 may output data flow 244 as a bitmap, e.g., where a 1 or Y is reported for a match and 0 or N is reported for mismatch, as shown in FIG. 17.).
16. The method of claim 14, wherein a DFA graph with fall-through transitions has fewer transitions than a DFA graph without fall-through transitions. ([0158] In some examples, before evaluating payload data, DFA engines 206 may preload at least a portion of a DFA graph into buffer memory 204 from external memory 210 or a different computer-readable medium based on the memory allocation specified by the compiler for each node. Additionally, or alternatively, DFA engines 206 may preload a portion of the DFA graph into memory of a thread of the one of DFA engines 206. In particular, DFA engines 206 may be configured to receive a DFA LOAD work unit, including instructions to direct the DFA engine to load at least a portion of a DFA graph (e.g., a root of the DFA graph, and/or other portions of the DFA graph) into buffer memory 204 and/or memory of one of the threads of the DFA engines 206. The at least portion of the DFA graph may include a root node of the DFA graph and/or data representing one or more nodes and/or arcs of the nodes of the DFA graph. Likewise, DFA engines 206 may be configured to unload a loaded portion of a DFA graph from the thread memory and/or from buffer memory 204, e.g., in response to a DFA UNLOAD work unit. The DFA UNLOAD work unit may include instructions indicating that one or more loaded arcs of a DFA graph are to be removed from thread memory and/or buffer memory 204, and/or to unlock and clear a root buffer for a DFA graph from the thread memory and/or buffer memory 204.).
17. The method of claim 16, further comprising caching a larger amount of information for the DFA graph with fall-through transitions relative to the DFA graph without fall-through transitions. ([0156] DFA engines 206 also include respective processing units for comparing a current symbol of the payload data to labels for arcs from the current node of the DFA graph. The threads of each of DFA engines 206 may share a common processing unit, or the threads may each include a corresponding processing unit. In general, the processing unit determines a node to which to transition from the current node (i.e., the node to which the arc having a label matching the current symbol of the payload data points). ).
18. The method of claim 14, wherein the regex accelerator comprises multiple DFA instances and multiple non-deterministic finite automaton (NFA) instances. ([0173] FIG. 14 is a block diagram illustrating an example regular expression (RegEx) accelerator 211 having one or more hardware-based non-deterministic finite automata (NFA) engines 216 that operate to efficiently apply query predicates to data by performing pattern matching on streams of data units. As further explained below, in one example, rather than operate by storing and traversing NFA graphs, in some examples, NFA engines 216 are instruction-based engines that execute instructions generated in view of one or more NFA graphs, thereby implementing NFA regular expression operations without traversing NFA graphs while processing streams of data units.
19. The method of claim 18, wherein during compiling, fall-through transitions are added to the DFA graph while reducing a total number of transitions associated with the DFA graph. ([0158] In some examples, before evaluating payload data, DFA engines 206 may preload at least a portion of a DFA graph into buffer memory 204 from external memory 210 or a different computer-readable medium based on the memory allocation specified by the compiler for each node. Additionally, or alternatively, DFA engines 206 may preload a portion of the DFA graph into memory of a thread of the one of DFA engines 206. In particular, DFA engines 206 may be configured to receive a DFA LOAD work unit, including instructions to direct the DFA engine to load at least a portion of a DFA graph (e.g., a root of the DFA graph, and/or other portions of the DFA graph) into buffer memory 204 and/or memory of one of the threads of the DFA engines 206. The at least portion of the DFA graph may include a root node of the DFA graph and/or data representing one or more nodes and/or arcs of the nodes of the DFA graph. Likewise, DFA engines 206 may be configured to unload a loaded portion of a DFA graph from the thread memory and/or from buffer memory 204, e.g., in response to a DFA UNLOAD work unit. The DFA UNLOAD work unit may include instructions indicating that one or more loaded arcs of a DFA graph are to be removed from thread memory and/or buffer memory 204, and/or to unlock and clear a root buffer for a DFA graph from the thread memory and/or buffer memory 204.).
20. The method of claim 14, further comprising: (1) allocating a portion of the memory for a result buffer, and (2) for each transition into a match state associated with the DFA graph, appending a position of the payload at which the match occurred to the result buffer.
([0243] In other examples, FINAL instructions push a result (Y/N or 1/0) to the result buffer based upon the results of the previously executed array comparison instructions but, upon a failure, do not empty the instruction stack such that NFA engines 216 execute any instructions previously pushed to a given instruction stack. As such, NFA engines 216 generate output data flow 244 to include an affirmative result upon a match and also a negative indication if the predicate is not satisfied by the current data unit of the input data stream. As such, in this example implementation, NFA engines 216 may output data flow 244 as a bitmap, e.g., where a 1 or Y is reported for a match and 0 or N is reported for mismatch, as shown in FIG. 17.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL SHARPLESS whose telephone number is (571)272-1521. The examiner can normally be reached M-F 7:30 AM- 3:30 PM (ET).
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/S.C.S./Examiner, Art Unit 2165
/ALEKSANDR KERZHNER/Supervisory Patent Examiner, Art Unit 2165