DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 17, 2024 is being considered by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horibe (US 2019/0317350 A1).
Horibe teaches a liquid crystal display device and a method for driving a liquid crystal display device comprising:
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With regard to claim 1, a voltage and current generator (FIG. 1, timing controller 100) comprising: an operation interface (FIG. 5 in view of FIG. 1, Vref terminal) configured to receive an operation (precedently set for controlling the value of the applied voltage) from a user; an output stage (FIG. 1, power supply section 110) configured to output an electrical signal (voltages to be applied to the gate drivers and source drivers) to a load (FIG. 1, gate drivers 2 and source drivers 3); a detector (FIG. 1, voltage monitor line 102) configured to detect a measured value (FIGS. 1, 5, 6, 8 and 9, value Vm of the monitor voltage) of the electrical signal (voltages to be applied to the gate drivers and source drivers) outputted by the output stage (FIG. 1, power supply section 110); and a control calculator (FIG. 5 in view of FIG. 1, voltage controller 120) configured to control operation of the output stage (FIG. 1, power supply section 110), based on a deviation between a target value (target voltage value Vref) of the electrical signal (voltages to be applied to the gate drivers and source drivers) as set by the user (prescribed voltage value precedently set for controlling the value of the applied voltage) via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) and the measured value (FIGS. 1, 5, 6, 8 and 9, value Vm of the monitor voltage) of the electrical signal (voltages to be applied to the gate drivers and source drivers) as detected by the detector (FIG. 1, voltage monitor line 102), so that the measured value (FIGS. 1, 5, 6, 8 and 9, value Vm of the monitor voltage) of the electrical signal (voltages to be applied to the gate drivers and source drivers) approaches the target value (target voltage value Vref), wherein the control calculator (FIG. 9 in view of FIG. 1, voltage controller 120) is configured to perform control, including a compensation operation (smoothing processing) to cancel a low-pass filter effect (to eliminate high frequency noise included in the signal) in output resistance of the output stage (FIG. 1, power supply section 110) and the load (FIG. 1, gate drivers 2 and source drivers 3), based on an impedance of the load (FIG. 1, gate drivers 2 and source drivers 3) as set by the user (prescribed voltage value precedently set for controlling the value of the applied voltage) via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) (For more details, please read: Abstract; and paragraphs: [0027]-[0033], [0048], [0049], [0051], [0052], [0059], [0064], [0065], [0071] and [0084]-[0089]).
With regard to claim 2, the control calculator (FIG. 9 in view of FIG. 1, voltage controller 120) is configured to perform the control, including the compensation operation (smoothing processing) to cancel the low-pass filter effect (to eliminate high frequency noise included in the signal) in the output resistance and the load (FIG. 1, gate drivers 2 and source drivers 3), based on the output resistance of the output stage (FIG. 1, power supply section 110) corresponding to a range (voltage values of the applied voltages) of the electrical signal (voltages to be applied to the gate drivers and source drivers) as set by the user via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) (FIG. 10; paragraphs: [0032], [0064]-[0066], [0069] and [0071]).
With regard to claim 3, the output stage (FIG. 1, power supply section 110) is configured to output a constant voltage signal (FIGS. 1 and 3A-D, voltage value Vo) as the electrical signal (voltages to be applied to the gate drivers and source drivers) to the load (FIG. 1, gate drivers 2 and source drivers 3), the detector (FIG. 1, voltage monitor line 102) is configured to detect a voltage value (FIGS. 1, 5, 6, 8 and 9, value Vm of the monitor voltage) of the electrical signal (voltages to be applied to the gate drivers and source drivers) outputted by the output stage (FIG. 1, power supply section 110) as the measured value, and the control calculator (FIG. 5 in view of FIG. 1, voltage controller 120) is configured to control operation of the output stage (FIG. 1, power supply section 110) based on a deviation between a target value (target voltage value Vref) of voltage of the electrical signal (voltages to be applied to the gate drivers and source drivers) as set by the user via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) and the voltage value (FIGS. 1, 5, 6, 8 and 9, value Vm of the monitor voltage) of the electrical signal (voltages to be applied to the gate drivers and source drivers) as detected by the detector (FIG. 1, voltage monitor line 102), and perform control, including the compensation operation (smoothing processing) to cancel the low-pass filter effect (to eliminate high frequency noise included in the signal) in the output resistance and the load (FIG. 1, gate drivers 2 and source drivers 3), based on a resistance and a capacitance (impedance) of the load (FIG. 1, gate drivers 2 and source drivers 3) as set by the user via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) as the impedance of the load (FIG. 1, gate drivers 2 and source drivers 3) (Paragraphs: [0003], [0040]-[0041], [0049], [0053]-[0058] and [0090]-[0093]).
With regard to claim 4, the output stage (FIG. 1, power supply section 110) is configured to output a constant current signal as the electrical signal (voltages to be applied to the gate drivers and source drivers) to the load (FIG. 1, gate drivers 2 and source drivers 3), the detector (FIG. 1, voltage monitor line 102) is configured to detect a current value of the electrical signal (voltages to be applied to the gate drivers and source drivers) outputted by the output stage (FIG. 1, power supply section 110) as the measured value, and the control calculator (FIG. 5 in view of FIG. 1, voltage controller 120) is configured to control operation of the output stage (FIG. 1, power supply section 110) based on a deviation between a target value (target voltage value Vref) of current of the electrical signal (voltages to be applied to the gate drivers and source drivers) as set by the user via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) and the current value of the electrical signal (voltages to be applied to the gate drivers and source drivers) as detected by the detector (FIG. 1, voltage monitor line 102), and perform control, including the compensation operation (smoothing processing) to cancel the low-pass filter effect (to eliminate high frequency noise included in the signal) in the output resistance and the load (FIG. 1, gate drivers 2 and source drivers 3), based on a resistance and an inductance (impedance) of the load (FIG. 1, gate drivers 2 and source drivers 3) as set by the user via the operation interface (FIG. 5 in view of FIG. 1, Vref terminal) as the impedance of the load (FIG. 1, gate drivers 2 and source drivers 3) (Paragraphs: [0003], [0040]-[0041], [0049], [0053]-[0058] and [0090]-[0093]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Horibe in view of Kagan (US 8,907,657 B2).
Horibe teaches all that is claimed as discussed in the rejections of claims 1-4 above including the control to cancel the low-pass filter effect (to eliminate high frequency noise included in the signal) in the load (FIG. 1, gate drivers 2 and source drivers 3), the control calculator (FIG. 5 in view of FIG. 1, voltage controller 120), gains 123c to 123e, and an adder 123f to adjust the gains, but it does not specifically teach the following feature:
a characteristic limiting a maximum gain for the electrical signal in a band greater than a predetermined frequency.
It is noted that:
With regard to claim 5, this claim is directed to an apparatus whose feature (i.e., “a characteristic limiting a maximum gain for the electrical signal in a band greater than a predetermined frequency”) is recited functionally. Apparatus claims must be structurally distinguishable from the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function alone (See MPEP 2114). It has been held in the USPTO and EPO that an apparatus “configured to” perform a function has to be interpreted as meaning an apparatus set up to do something and not necessarily being an apparatus which actually does something. It has been held that the recitation that an element is "configured to" perform a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. In re Schreiber, 128 F.3d 1473, 1478, 44 USPQ2d 1429, 1432 (Fed. Cir. 1997). Therefore, a claim which has to be considered as being “configured to” carry out method steps, is not actually carrying out those method steps, and therefore, the unperformed method steps do not form part of the claim limitation in actuality. Therefore, as Horibe teaches the claimed structure, the limitation is met. The control calculator (FIG. 5 in view of FIG. 1, voltage controller 120) in combination with gains 123c to 123e and adder 123f to adjust the gains is fully capable of performing functions as recited in claim 5 (For more details, please read: Abstract; and paragraphs: [0027]-[0033], [0048], [0049], [0051], [0052], [0059], [0064], [0065], [0071] and [0084]-[0089]).
It is further noted that the feature upon which applicants rely (i.e., “a characteristic limiting a maximum gain for the electrical signal in a band greater than a predetermined frequency”) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such potential is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 (“The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.”); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997). Please see MPEP 2144.05 II. OPTIMIZATION OF RANGES: Optimization Within Prior Art Conditions or Through Routine Experimentation.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the liquid crystal display device and a method for driving a liquid crystal display device of Horibe to add a characteristic limiting a maximum gain for the electrical signal in a band greater than a predetermined frequency since such an arrangement is beneficial to provide desirable and exemplary choices for a specific configuration of the voltage controller for a liquid crystal display device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants’ attention is invited to the followings whose inventions disclose similar devices.
Kay et al. (US 2014/0009227 A1) teaches a power management system including a post-distortion filter circuit configured to filter the non-filtered parallel amplifier output impedance compensation signal to compensate for a low pass filter effect.
Yamamoto et al. (US 2005/0073317 A1) teaches an insulation resistance drop detector having a filter for eliminating a signal having a specific frequency from a voltage.
CONTACT INFORMATION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI-AN D. NGUYEN whose telephone number is (571) 272-2170. The examiner can normally be reached MON-THURS (7:00 AM - 5:00 PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEE E. RODAK can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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HOAI-AN D. NGUYEN
Primary Examiner
Art Unit 2858
/HOAI-AN D. NGUYEN/Primary Examiner, Art Unit 2858
Prosecution Insights