DETAILED ACTION
This action is in response to the Application filed on 05/17/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
Claims 1, 7 and 13 recite “normal operation mode”. Said term is defined in paragraph 015 of the original specifications as “not under a burst mode operation, or not under a start-up stage, or under a fault condition, etc.” Accordingly, normal operation mode has been interpretated by the Examiner as any operating mode except for burst, start-up or fault modes of operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 1, 2 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2020/0036280; (hereinafter Yang) in view US Pub. No. 20160181934; (hereinafter Kikuchi).
Regarding claim 1, Yang [e.g. Figs. 2 – 3B] discloses a flyback converter, comprising: a primary power switch [e.g. 20], coupled to a primary winding [e.g. W1] of a transformer [e.g. 10]; a secondary power switch [e.g. 50], coupled to a secondary winding [e.g. W2] of the transformer; and a control circuit [e.g. 1000], configured to provide a primary control signal [e.g. SW] and a secondary control signal [e.g. SG], to respectively control the primary power switch and the secondary power switch to be periodically turned on and off under a control of the control circuit [e.g. Figs. 3A-3B], to convert an input voltage [e.g. VIN] into an output voltage [e.g. VO]; wherein: when the flyback converter is under a normal operation mode [e.g. Fig. 3A], the secondary power switch is turned on [e.g. Fig. 3A; SG high at T1] after the primary power switch is turned off [e.g. SW low before T1], until an OFF condition is met [e.g. turn off control condition met by controller at end of demagnetization period T1]; then the secondary power switch is turned on again for an additional time [e.g. Fig. 3A; at T3] before the primary power switch is turned on at a next switching cycle [e.g. Fig. 3A at T5].
Yang fails to disclose when the flyback converter enters a burst mode and then exits from the burst mode, the secondary power switch is not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle.
Kikuchi [e.g. Figs. 2 and 6] teaches when the flyback converter [e.g. Fig. 2] enters a burst mode [e.g. Fig. 6 at t1; paragraph 096 recites “After the time point t1, the operation mode is set to the burst mode. In the burst mode, the pulse signal S1 is generated with a reduced frequency. Specifically, the time interval of generation of the pulse signal S1 becomes longer than the first time period τ1. In this state, the first detection signal S11 is asserted, and accordingly, the shutdown signal SDN is set to the high level, which suspends the switching of the synchronous rectification transistor M2”] and then exits from the burst mode [e.g. after t2; paragraph 097 recites “After the operation mode is returned to the non-burst mode at the time point t2, the switching transistor M1 continuously switches on and off. In this state, the time interval of generation of the pulse signal S1 becomes shorter than the first time period τ1. When the number of continuously generated pulse signals S1 exceeds a predetermined number N, the second detection signal S12 is asserted, and accordingly, the shutdown signal SDN is set to the low level, which restarts the switching of the synchronous rectification transistor M2”], the secondary power switch [e.g. Fig. 2 and 6; M2] is not turned on again for the additional time before a primary power switch's [e.g. Figs. 2 and 6; M1] turn-on at the next switching cycle [e.g. see annotated Fig. 3 below].
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It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by when the flyback converter enters a burst mode and then exits from the burst mode, the secondary power switch is not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle as taught by Kikuchi in order of being able to reduce power consumption, paragraph 017.
Regarding claim 2, Yang fails to disclose wherein: the primary power switch and the secondary power switch are idle when the flyback converter is under the burst mode.
Kikuchi [e.g. Figs. 2 and 6] teaches wherein: the primary power switch and the secondary power switch [e.g. M1, M2] are idle when the flyback converter is under the burst mode [e.g. as shown in Fig. 6 between t1-t2].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by wherein: the primary power switch and the secondary power switch are idle when the flyback converter is under the burst mode as taught by Kikuchi in order of being able to reduce power consumption, paragraph 017.
Regarding claim 7, Yang [e.g. Figs. 2 – 3B] discloses a control circuit used in a flyback converter, comprising: a first controller [e.g. Fig. 2; 100], configured to generate a secondary signal [e.g. SG] and a secondary control signal [e.g. VB], wherein the secondary control signal is used to control a secondary power switch [e.g. 50]; a delivery block [e.g. 70], configured to convert the secondary signal to a primary signal [e.g. VFB]; and a second controller [e.g. 200], configured to generate a primary control signal [e.g. SW] used to control a primary power switch [e.g. 20] in response to the primary signal [e.g. paragraph 034 recites “the pulse width of the switching signal SW is determined according to the feedback related signal VFB”]; wherein: when the flyback converter is under a normal operation mode [e.g. Fig. 3A], the first controller is configured to control the secondary power switch to be turned on [e.g. Fig. 3A; SG high at T1] after the primary power switch is turned off [e.g. SW low before T1], until an OFF condition of is met [e.g. turn off control condition met by controller at end of demagnetization period T1]; and control the secondary power switch to be turned on again for an additional time [e.g. Fig. 3A; SG high level at T3 (ZVS pulse)] before the primary power switch is turned on at a next switching cycle [e.g. Fig. 3A; SW at T5]; and Yang fails to disclose when the flyback converter enters a burst mode and then exits from the burst mode, the first controller is configured to control the secondary power switch to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle.
Yang fails to disclose when the flyback converter enters a burst mode and then exits from the burst mode, the first controller is configured to control the secondary power switch to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle.
Kikuchi [e.g. Figs. 2 and 6] teaches when the flyback converter [e.g. Fig. 2] enters a burst mode [e.g. Fig. 6 at t1; paragraph 096 recites “After the time point t1, the operation mode is set to the burst mode. In the burst mode, the pulse signal S1 is generated with a reduced frequency. Specifically, the time interval of generation of the pulse signal S1 becomes longer than the first time period τ1. In this state, the first detection signal S11 is asserted, and accordingly, the shutdown signal SDN is set to the high level, which suspends the switching of the synchronous rectification transistor M2”] and then exits from the burst mode [e.g. after t2; paragraph 097 recites “After the operation mode is returned to the non-burst mode at the time point t2, the switching transistor M1 continuously switches on and off. In this state, the time interval of generation of the pulse signal S1 becomes shorter than the first time period τ1. When the number of continuously generated pulse signals S1 exceeds a predetermined number N, the second detection signal S12 is asserted, and accordingly, the shutdown signal SDN is set to the low level, which restarts the switching of the synchronous rectification transistor M2”], the first controller [e.g. Fig. 2; 300] is configured to control the secondary power switch [e.g. Fig. 2; M2] to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle [e.g. see annotated Fig. 3 below].
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It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by when the flyback converter enters a burst mode and then exits from the burst mode, the first controller is configured to control the secondary power switch to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle as taught by Kikuchi in order of being able to reduce power consumption, paragraph 017.
Claims 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view Kikuchi, US Pub. No. 20150103567; (hereinafter Wang) and further in view of US Pub. No. 2015/0280573; (hereinafter Gong).
Regarding claim 5, Yang fails to disclose wherein the control circuit comprises: an error amplifier, configured to amplify and integrate a difference between a feedback voltage indicative of the output voltage and a reference voltage, to generate a compensation signal; a comparator, configured to compare the compensation signal with a voltage threshold, to generate an indicative signal, wherein the indicative signal indicates the flyback converter to enter and/or exit the burst mode; a first controller, configured to generate a secondary signal and the secondary control signal in response to the compensation signal, the indicative signal, and a signal indicative of a current flowing through the secondary power switch; a delivery block, configured to convert the secondary signal to a primary signal; and a second controller, configured to generate the primary control signal in response to the primary signal.
Wang [e.g. Fig. 9] teaches wherein the control circuit comprises: an error amplifier [e.g. 906], configured to amplify a difference between a feedback voltage [e.g. FB] indicative of the output voltage [e.g. Vout] and a reference voltage [e.g. VREF], to generate a compensation signal [e.g. COMP]; a comparator [e.g. 905], configured to compare the compensation signal with a voltage threshold [e.g. Vc], to generate an indicative signal [e.g. CMPO1], wherein the indicative signal indicates the flyback converter to enter and/or exit the burst mode [e.g. paragraph 045 recites “When the load current decreases, the compensation signal COMP as well as the feedback signal FB increases. The time period during which the modulation signal VM increases to reach the compensation signal COMP increases, which decreases the frequency of the first comparison signal CMPO1 and also the synchronous frequency fsync. When the compensation signal COMP increases to reach the breakdown voltage of the Zener diode ZD1, the switching converter enters into a burst mode and the synchronous frequency fsync is equal to fburst. If the load current keeps decreasing, the modulation signal VM will be clamped to be equal to the breakdown voltage of the Zener diode ZD1 and cannot become larger than the compensation signal COMP. The first comparison signal CMPO1 and the synchronous signal SYNC are maintained low until the compensation signal COMP drops below the breakdown voltage of the Zener diode ZD1”]; a first controller [e.g. 903,904,910, OR1, OR2, AND1], configured to generate a secondary signal [e.g. ISOIN] and the secondary control signal [e.g. CTRLS] in response to the compensation signal, the indicative signal, and a signal indicative of a current flowing through the secondary power switch [e.g. ISENS at 910 sensed at source of MS]; a delivery block [e.g. 902], configured to convert the secondary signal to a primary signal [e.g. SYNC]; and a second controller [e.g. 901], configured to generate the primary control signal [e.g. CTRL] in response to the primary signal [e.g. see control loop].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by wherein the control circuit comprises: an error amplifier, configured to amplify a difference between a feedback voltage indicative of the output voltage and a reference voltage, to generate a compensation signal; a comparator, configured to compare the compensation signal with a voltage threshold, to generate an indicative signal, wherein the indicative signal indicates the flyback converter to enter and/or exit the burst mode; a first controller, configured to generate a secondary signal and the secondary control signal in response to the compensation signal, the indicative signal, and a signal indicative of a current flowing through the secondary power switch; a delivery block, configured to convert the secondary signal to a primary signal; and a second controller, configured to generate the primary control signal in response to the primary signal as taught by Wang in order of being able to precisely control the primary and secondary switches and avoid shoot through, paragraph 09.
Gong [e.g. Fig. 1a and 2a] teaches an error amplifier [e.g. Fig. 2a; 208], configured to amplify and integrate [e.g. paragraph 029 recites “FIG. 2a illustrates an embodiment synchronous rectifying control circuit 200 that includes operational amplifiers (opamps) 206, 208”. Examiner note: It is well known in the art that a characteristic of an operational amplifier is that it amplify and integrates an error].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by an error amplifier, configured to amplify and integrate as taught by Gong in order of being able to provide precise analog signal processing, as it is well known in the art of op-amps characteristics.
Regarding claim 8, Yang fails to disclose further comprising: an error amplifier, configured to amplify and integrate a difference between a feedback voltage indicative of an output voltage and a reference voltage, to generate a compensation signal; and a comparator, configured to compare the compensation signal with a voltage threshold, to generate an indicative signal, wherein the indicative signal indicates the flyback converter to enter and/or exit the burst mode.
Wang [e.g. Fig. 9] teaches further comprising: an error amplifier [e.g. 906], configured to amplify a difference between a feedback voltage [e.g. FB] indicative of the output voltage [e.g. Vout] and a reference voltage [e.g. VREF], to generate a compensation signal [e.g. COMP]; a comparator [e.g. 905], configured to compare the compensation signal with a voltage threshold [e.g. Vc], to generate an indicative signal [e.g. CMPO1], wherein the indicative signal indicates the flyback converter to enter and/or exit the burst mode [e.g. paragraph 045 recites “When the load current decreases, the compensation signal COMP as well as the feedback signal FB increases. The time period during which the modulation signal VM increases to reach the compensation signal COMP increases, which decreases the frequency of the first comparison signal CMPO1 and also the synchronous frequency fsync. When the compensation signal COMP increases to reach the breakdown voltage of the Zener diode ZD1, the switching converter enters into a burst mode and the synchronous frequency fsync is equal to fburst. If the load current keeps decreasing, the modulation signal VM will be clamped to be equal to the breakdown voltage of the Zener diode ZD1 and cannot become larger than the compensation signal COMP. The first comparison signal CMPO1 and the synchronous signal SYNC are maintained low until the compensation signal COMP drops below the breakdown voltage of the Zener diode ZD1”]; a first controller [e.g. 903,904,910, OR1, OR2, AND1], configured to generate a secondary signal [e.g. ISOIN] and the secondary control signal [e.g. CTRLS] in response to the compensation signal, the indicative signal, and a signal indicative of a current flowing through the secondary power switch [e.g. ISENS at 910 sensed at source of MS]; a delivery block [e.g. 902], configured to convert the secondary signal to a primary signal [e.g. SYNC]; and a second controller [e.g. 901], configured to generate the primary control signal [e.g. CTRL] in response to the primary signal [e.g. see control loop].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by further comprising: an error amplifier, configured to amplify a difference between a feedback voltage indicative of an output voltage and a reference voltage, to generate a compensation signal; and a comparator, configured to compare the compensation signal with a voltage threshold, to generate an indicative signal, wherein the indicative signal indicates the flyback converter to enter and/or exit the burst mode as taught by Wang in order of being able to precisely control the primary and secondary switches and avoid shoot through, paragraph 09.
Gong [e.g. Fig. 1a and 2a] teaches an error amplifier [e.g. Fig. 2a; 208], configured to amplify and integrate [e.g. paragraph 029 recites “FIG. 2a illustrates an embodiment synchronous rectifying control circuit 200 that includes operational amplifiers (opamps) 206, 208”. Examiner note: It is well known in the art that a characteristic of an operational amplifier is that it amplify and integrates an error].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by an error amplifier, configured to amplify and integrate as taught by Gong in order of being able to provide precise analog signal processing, as it is well known in the art of op-amps characteristics.
Claims 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kikuchi, and further in view of Wang.
Regarding claim 12, Yang fails to disclose wherein the delivery circuit comprises: an isolation capacitor.
Wang [e.g. Fig. 2] teaches wherein the delivery circuit [e.g. 202] comprises: an isolation capacitor [e.g. paragraph 029 recites “The isolation circuit 202 may comprise opto-coupler, transformer, capacitor or other suitable electrical isolators”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by wherein the delivery circuit comprises: an isolation capacitor as taught by Wang in order of being able to provide voltage surge protection, low power consumption, and bi-directional signal transmission, as it is well known in the art.
Claims 13 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Yang, Kikuchi, and further in view of Gong.
Regarding claim 13, Wang [e.g. Fig. 9] discloses a control circuit used in a flyback converter, comprising: an error amplifier [e.g. 906], configured to amplify a difference between a feedback voltage [e.g. FB] indicative of an output voltage [e.g. Vout] and a reference voltage [e.g. VREF], to generate a compensation signal [e.g. COMP]; a comparator [e.g. 905], configured to compare the compensation signal with a voltage threshold [e.g. Vc], to generate an indicative signal [e.g. CMPO1], wherein the indicative signal indicates the flyback converter to enter and/or exit a burst mode [e.g. paragraph 045 recites “When the load current decreases, the compensation signal COMP as well as the feedback signal FB increases. The time period during which the modulation signal VM increases to reach the compensation signal COMP increases, which decreases the frequency of the first comparison signal CMPO1 and also the synchronous frequency fsync. When the compensation signal COMP increases to reach the breakdown voltage of the Zener diode ZD1, the switching converter enters into a burst mode and the synchronous frequency fsync is equal to fburst. If the load current keeps decreasing, the modulation signal VM will be clamped to be equal to the breakdown voltage of the Zener diode ZD1 and cannot become larger than the compensation signal COMP. The first comparison signal CMPO1 and the synchronous signal SYNC are maintained low until the compensation signal COMP drops below the breakdown voltage of the Zener diode ZD1”]; a first controller [e.g. 903,904,910, OR1, OR2, AND1], configured to generate a secondary signal [e.g. ISOIN] and a secondary control signal [e.g. CTRLS] in response to a signal indicative of a current flowing through the secondary power switch [e.g. ISENS at 910 sensed at source of MS], the compensation signal [e.g. see feedback loop] and the indicative signal [e.g. see feedback loop], wherein the secondary control signal is used to control a secondary power switch [e.g. MS]; a delivery block [e.g. 902], configured to convert the secondary signal to a primary signal [e.g. SYNC]; and a second controller [e.g. 901], configured to generate a primary control signal [e.g. CTRL] used to control a primary power switch [e.g. MP] in response to the primary signal [e.g. see control loop].
Wang fails to disclose the error amplifier, configured to amplify and integrate; wherein: when the flyback converter is under a normal operation mode, the first controller is configured to control the secondary power switch to be turned on after the primary power switch is turned off, until an OFF condition of is met; and control the secondary power switch to be turned on again for an additional time before the primary power switch is turned on at a next switching cycle; and when the flyback converter enters a burst mode and then exits from the burst mode, the first controller is configured to control the secondary power switch to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle.
Yang [e.g. Figs. 2 – 3B] teaches wherein: when the flyback converter [e.g. Fig. 2; 2] is under a normal operation mode [e.g. Fig. 3A], the first controller is configured to control the secondary power switch [e.g. 50 via SG] to be turned on [e.g. Fig. 3A; SG high at T1] after the primary power switch is turned off [e.g. SW low before T1], until an OFF condition of is met [e.g. turn off control condition met by controller at end of demagnetization period T1]; and control the secondary power switch to be turned on again for an additional time [e.g. Fig. 3A; SG high level at T3 (ZVS pulse)] before the primary power switch is turned on at a next switching cycle [e.g. Fig. 3A; SW at T5].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Wang by wherein: when the flyback converter is under a normal operation mode, the first controller is configured to control the secondary power switch to be turned on after the primary power switch is turned off, until an OFF condition of is met; and control the secondary power switch to be turned on again for an additional time before the primary power switch is turned on at a next switching cycle as taught by Yang in order of being able to reduce switching losses.
Kikuchi [e.g. Figs. 2 and 6] teaches when the flyback converter [e.g. Fig. 2] enters a burst mode [e.g. Fig. 6 at t1; paragraph 096 recites “After the time point t1, the operation mode is set to the burst mode. In the burst mode, the pulse signal S1 is generated with a reduced frequency. Specifically, the time interval of generation of the pulse signal S1 becomes longer than the first time period τ1. In this state, the first detection signal S11 is asserted, and accordingly, the shutdown signal SDN is set to the high level, which suspends the switching of the synchronous rectification transistor M2”] and then exits from the burst mode [e.g. after t2; paragraph 097 recites “After the operation mode is returned to the non-burst mode at the time point t2, the switching transistor M1 continuously switches on and off. In this state, the time interval of generation of the pulse signal S1 becomes shorter than the first time period τ1. When the number of continuously generated pulse signals S1 exceeds a predetermined number N, the second detection signal S12 is asserted, and accordingly, the shutdown signal SDN is set to the low level, which restarts the switching of the synchronous rectification transistor M2”], the first controller [e.g. Fig. 2; 300] is configured to control the secondary power switch [e.g. Fig. 2; M2] to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle [e.g. see annotated Fig. 3 below].
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It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by wherein: when the flyback converter is under a normal operation mode, the first controller is configured to control the secondary power switch to be turned on after the primary power switch is turned off, until an OFF condition of is met; and control the secondary power switch to be turned on again for an additional time before the primary power switch is turned on at a next switching cycle; and when the flyback converter enters a burst mode and then exits from the burst mode, the first controller is configured to control the secondary power switch to be not turned on again for the additional time before a primary power switch's turn-on at the next switching cycle as taught by Kikuchi in order of being able to reduce power consumption, paragraph 017.
Gong [e.g. Fig. 1a and 2a] teaches an error amplifier [e.g. Fig. 2a; 208], configured to amplify and integrate [e.g. paragraph 029 recites “FIG. 2a illustrates an embodiment synchronous rectifying control circuit 200 that includes operational amplifiers (opamps) 206, 208”. Examiner note: It is well known in the art that a characteristic of an operational amplifier is that it amplify and integrates an error].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Wang by wherein the delivery circuit comprises: an isolation capacitor as taught by Wang in order of being able to provide voltage surge protection, low power consumption, and bi-directional signal transmission, as it is well known in the art.
Regarding claim 17, Wang, Fig. 9 fails to explicitly disclose wherein the delivery circuit comprises: an isolation capacitor.
Wang [e.g. Fig. 2] teaches wherein the delivery circuit [e.g. 202] comprises: an isolation capacitor [e.g. paragraph 029 recites “The isolation circuit 202 may comprise opto-coupler, transformer, capacitor or other suitable electrical isolators”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Yang by wherein the delivery circuit comprises: an isolation capacitor as taught by Wang in order of being able to provide voltage surge protection, low power consumption, and bi-directional signal transmission, as it is well known in the art.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claim(s) 3 – 4, 6, 9 – 11 and 14 – 16 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein: at a first one switching cycle just after exiting from the burst mode, the control circuit is configured to not control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and after the first one switching cycle since the flyback converter exits from the burst mode, the control circuit is configured to control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle”.
The primary reason for the indication of the allowability of claim 4 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein: at first N switching cycles just after the flyback converter exits from the burst mode, the control circuit is configured to not control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and after the first N switching cycles since the flyback converter exits from the burst mode, the control circuit is configured to control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and wherein N is an integer larger than 1”.
The primary reason for the indication of the allowability of claim 6 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the first controller comprises: a first signal generator, configured to generate a first control signal in response to the signal indicative of the current flowing through the secondary power switch, to control a freewheeling of the secondary power switch; a second signal generator, configured to generate a second control signal in response to the compensation signal and the indicative signal; and a select circuit, configured to select the second control signal or the compensation signal as the second signal in response to the indicative signal”.
The primary reason for the indication of the allowability of claim 9 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the first controller comprises: a first signal generator, configured to generate a first control signal in response to a signal indicative of a current flowing through the secondary power switch, to control a freewheeling of the secondary power switch; a second signal generator, configured to generate a second control signal in response to the compensation signal and the indicative signal; and a select circuit, configured to select the second control signal or the compensation signal as the second signal in response to the indicative signal”.
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein: at a first one switching cycle just after exiting from the burst mode, the control circuit is configured to not control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and after the first one switching cycle since the flyback converter exits from the burst mode, the control circuit is configured to control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle.
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: at first N switching cycles just after the flyback converter exits from the burst mode, the control circuit is configured to not control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and after the first N switching cycles since the flyback converter exits from the burst mode, the control circuit is configured to control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and wherein N is an integer larger than 1”.
The primary reason for the indication of the allowability of claim 14 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the first controller comprises: a first signal generator, configured to generate a first control signal in response to a signal indicative of a current flowing through the secondary power switch, to control a freewheeling of the secondary power switch; a second signal generator, configured to generate a second control signal in response to the compensation signal and the indicative signal; and a select circuit, configured to select the second control signal or the compensation signal as the second signal in response to the indicative signal.
The primary reason for the indication of the allowability of claim 15 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “at a first one switching cycle just after exiting from the burst mode, the first controller is configured to not control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and after the first one switching cycle since the flyback converter exits from the burst mode, the first controller is configured to control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle.
The primary reason for the indication of the allowability of claim 16 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: at first N switching cycles just after the flyback converter exits from the burst mode, the first controller is configured to not control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and after the first N switching cycles since the flyback converter exits from the burst mode, the first controller is configured to control the secondary power switch to be turned on again for the additional time before the primary power switch's turn-on at the next switching cycle; and wherein N is an integer larger than 1.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838