DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Regarding Applicant’s traversal in the reply filed 22 July 2026 of the election of species requirement filed 24 June 2026, Applicant’s arguments are acknowledged, have been fully considered, and are found persuasive. Accordingly, the election of species requirement is withdrawn in whole, and all pending claims are examined on the merits.
Claim Objections
Claims 1, 15, and 19 are objected to because of the following informalities:
Regarding Claim 1,
This claim recites “an upper surface of the first molding layer”. While not inaccurate, the instant specification and many of the claims, including those dependent upon Claim 1, recite what appears to be the same element as “an/the uppermost surface of the first molding layer”. For consistency and clarity of record, the Examiner recommends this limitation be amended to recite “an uppermost surface of the first molding layer”. For the purposes of examination, this limitation will also be interpreted as such.
Further regarding Claim 1,
This claim recites “a first molding layer surrounding a portion of an upper surface of the first semiconductor chip”. However, this appears to be inconsistent with the disclosed relationship shown in Fig. 1 of the instant application, wherein “a first molding layer covering a portion of an upper surface of the first semiconductor chip” is shown. For the sake of clarity of record, the Examiner recommends the preceding amended language and will interpret this limitation as such for the purposes of examination.
Regarding Claim 15,
This claim recites “a first molding layer surrounding a portion of an upper surface of the first semiconductor chip”. However, this appears to be inconsistent with the disclosed relationship shown in Fig. 1 of the instant application, wherein “a first molding layer covering a portion of an upper surface of the first semiconductor chip” is shown. For the sake of clarity of record, the Examiner recommends the preceding amended language and will interpret this limitation as such for the purposes of examination.
Further regarding Claim 15,
This claim recites “an upper surface of the first molding layer into the first molding layer”. While not inaccurate, the instant specification and many of the claims, including those dependent upon Claim 15, recite what appears to be the same element as “an/the uppermost surface of the first molding layer”. For consistency and clarity of record, the Examiner recommends this limitation be amended to recite “an uppermost surface of the first molding layer into the first molding layer”. For the purposes of examination, this limitation will also be interpreted as such.
Regarding Claim 19,
This claim recites “a plurality of first through electrodes configured to penetrate the first semiconductor substrate”. However, this appears to be inconsistent with the disclosed relationship shown in Fig. 1 of the instant application, wherein “a plurality of first through electrodes
Further regarding Claim 19,
This claim recites “an upper surface of the first molding layer into the first molding layer”. While not inaccurate, the instant specification and many of the claims, including those dependent upon Claim 19, recite what appears to be the same element as “an/the uppermost surface of the first molding layer”. For consistency and clarity of record, the Examiner recommends this limitation be amended to recite “an uppermost surface of the first molding layer into the first molding layer”. For the purposes of examination, this limitation will also be interpreted as such.
Further regarding Claim 19,
This claim recites “a plurality of second through electrodes configured to penetrate the second semiconductor substrate”. However, this appears to be inconsistent with the disclosed relationship shown in Fig. 1 of the instant application, wherein “a plurality of second through electrodes
Further regarding Claim 19,
This claim recites “the first side surface of the first molding layer includes a side surface of the first molding layer that is exposed”. However, this language appears circular. For the sake of clarity of the record, the Examiner recommends this claim language be amended to “the first side surface of the first molding layer
Further regarding Claim 19,
This claim recites “the second side surface of the first molding layer includes a side surface that is in contact”. However, this language appears circular. For the sake of clarity of the record, the Examiner recommends this claim language be amended to “the second side surface of the first molding layer .
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2, 5, 10, 12, 14 – 15, and 17 – 19—as well as their respective dependent claims—are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Regarding Claim 2,
Lin. 2 recites the limitation "an uppermost surface of the first molding layer". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as "the uppermost surface of the first molding layer".
Lin. 3 – 4 recite “a corner of a side surface of the first molding layer that is exposed to the outside of the semiconductor package”. However, it is unclear which noun the clause “that is exposed to the outside of the semiconductor package” modifies, rendering this claim indefinite. For the purposes of examination, this limitation will be interpreted as “a corner of a side surface of the first molding layer, wherein the first molding layer
Regarding Claim 5,
Lin. 2 recites the limitation "an uppermost surface of the first molding layer". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as "the uppermost surface of the first molding layer".
Regarding Claim 10,
Lin. 5 recites the limitation "an uppermost surface of the first molding layer". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as "the uppermost surface of the first molding layer".
Regarding Claim 12,
Lin. 2 recites the limitation “a thickness of each of the plurality of second semiconductor chips” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “[[a]] the thickness of each of the plurality of second semiconductor chips”.
Lin. 4 recites the limitation “a thickness of the dummy chip” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “[[a]] the thickness of the dummy chip”.
Regarding Claim 14,
Lin. 1 – 2 recite “a horizontal area of the dummy chip” and “a horizontal area of each of the plurality of second semiconductor chips”, respectively. However, the meaning of these limitations is unclear, as they fail to meet the metes and bounds of the disclosed invention. Specifically, Fig. 1 of the Instant Drawings shows corresponding horizontal lengths—W_400 and W_200, respectively—to the contrary. Accordingly, for the purposes of examination, these limitations will be interpreted as “a horizontal length of the dummy chip” and “a horizontal length of each of the plurality of second semiconductor chips”, which meets the metes and bounds of the of the disclosed invention.
Regarding Claim 15,
Lin. 14 – 15 recites the limitation "filling the trench, and covering an upper surface of the first molding layer". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as "filling the trench, and covering the uppermost surface of the first molding layer ".
Regarding Claim 17,
Lin. 8 recites “the uppermost second semiconductor chip is connected to the dummy chip only by the support bonding insulating layer”. However, the meaning of this limitation is unclear, as it fails to meet the metes and bounds of the disclosed invention. Specifically, Fig. 1 of the Instant Drawings shows the uppermost second semiconductor chip is connected to the dummy chip by the support bonding insulating layer—at their shared horizontal interface—as well as by the first and second molding layers covering their vertical sidewalls. Accordingly, for the purposes of examination, this limitation will be interpreted as “the uppermost second semiconductor chip is connected to the dummy chip
Regarding Claim 18,
Lin. 1 – 2 recite the limitation "an uppermost surface of the first molding layer". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as "the uppermost surface of the first molding layer".
Regarding Claim 19,
Lin. 14 recites “the dummy chip having a horizontal area identical to a horizontal area of each of the plurality of second semiconductor chips”. However, the meaning of this limitation is unclear, as it fails to meet the metes and bounds of the disclosed invention. Specifically, Fig. 1 of the Instant Drawings shows corresponding horizontal lengths—W_400 and W_200, respectively—to the contrary. Accordingly, for the purposes of examination, these limitations will be interpreted as “the dummy chip having a horizontal length identical to a horizontal length of each of the plurality of second semiconductor chips”, which meets the metes and bounds of the of the disclosed invention.
Lin. 26 – 27 recite the limitation "an uppermost surface of the first molding layer". There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as "the uppermost surface of the first molding layer".
Examiner’s Note
In addition to the original figures, for the prior art rejections to follow, consider the annotated figure below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 11, 14, & 19 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by CHEN (US 20190355637 A1).
PNG
media_image1.png
675
813
media_image1.png
Greyscale
Regarding Claim 1,
CHEN discloses:
A semiconductor package (Fig. 3: 300) comprising:
a first semiconductor chip (105; Par. 27 & 34);
a plurality of second semiconductor chips (405/407 combined of each 113, hereinafter denoted CHP2)
stacked on the first semiconductor chip (105),
each of the plurality of second semiconductor chips (CHP2) including
a semiconductor substrate (405; Par. 27 & 34) comprising
an active surface (405/407 interface: “front surface” of 405, comprising devices; Par. 27 & 28) and
an inactive surface (405/703 interface: “backside surface” of 405, silent to comprising and not comprising devices; Par. 21 & 28) opposite to the active surface (405/407);
Note, the adjective “inactive” for the limitation “inactive surface” constitutes a recitation with respect to the manner in which the claimed device is intended to be employed. Further, the prior art of record teaches all of the structural limitations of the claimed invention. Accordingly, this limitation does not differentiate the claimed invention from that of prior art, consistent with Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987); MPEP § 2114(II).
a first molding layer (117/107 combined; Par. 20 & 21 where a “molding layer” is understood to be formed of an “encapsulant” under a broadest reasonable interpretation.)
covering a portion of an upper surface of the first semiconductor chip (105) and side surfaces of the plurality of second semiconductor chips (CHP2),
the first molding layer (117/107) including
a (communicating) trench (TR) that extends from (and above) an uppermost surface (117_U) of the first molding layer (117 of 117/107) into the first molding layer (117 of 117/107);
Note, 117 of 117/107 includes a “communicating trench” TR that extends into and through the entire thickness of 117 of 117/107, as seen from Fig. 9A. And, a “trench” may be construed to be a “communicating trench” under a broadest reasonable interpretation.
a dummy chip (115; Par. 21)
stacked on an uppermost second semiconductor chip (CHP2 of 113_1) of the plurality of second semiconductor chips (CHP2); and
a second molding layer (307; Par. 25 where a “molding layer” is understood to be formed of an “encapsulant” under a broadest reasonable interpretation.)
surrounding side surfaces of the dummy chip (115), and
covering the first molding layer (117/107).
Regarding Claim 2,
CHEN discloses:
The semiconductor package of claim 1,
wherein the trench (TR) extends from (and above) a corner (117_UC) of the uppermost surface (117_U) of the first molding layer (117 of 117/107) to a corner (117_SC) of a side surface of the first molding layer (117 of 117/107),
wherein the first molding layer (107 of 117/107) is exposed to the outside of the semiconductor package (300), and
wherein the second (307) molding layer (partially) fills the trench (TR).
Regarding Claim 3,
CHEN does not disclose:
The semiconductor package of claim 2, wherein
the trench (TR) comprises a curved surface portion (CSP) in which an internal horizontal width of the trench (TR) decreases toward the first semiconductor chip (105).
Note, the surface of CSP changes direction—e.g. from D3 to D1—at the bottom of TR. Therefore, CSP comprises (sharply) curved surfaces.
Note, the internal horizontal width of TR within CSP is constant until it instantaneously decreases to zero at the bottom of CSP toward 105.
Regarding Claim 4,
CHEN discloses:
The semiconductor package of claim 2, wherein
the second molding layer (307) is spaced apart (by 609) from the first semiconductor chip (105) in a vertical direction (D1) with the first molding layer (107 of 117/107) therebetween (307 and 105 in a second direction, D2), and
the second molding layer (307) is spaced apart (by 117) from the plurality of second semiconductor chips (CHP2) in a horizontal direction (D3) with the first molding layer (117 of 117/107) therebetween (307 and CHP2 in D3).
Regarding Claim 5,
CHEN discloses:
The semiconductor package of claim 1, wherein
a horizontal length (117_UW) of the uppermost surface (117_U) of the first molding layer (117 of 117/107) is less than a horizontal length (107_LW) of a lower surface of the first molding layer (107 of 117/107).
Regarding Claim 6,
CHEN discloses:
The semiconductor package of claim 1, wherein
a vertical length (117_H) of a side surface of the first molding layer (117 of 117/107) that is in contact with the plurality of second semiconductor chips (CHP2) among side surfaces of the first molding layer (117/107) is greater than a vertical length (107_H) of a side surface of the first molding layer (107 of 117/107) that is exposed to the outside of the semiconductor package (300) among the side surfaces of the first molding layer (117/107).
Regarding Claim 7,
CHEN discloses:
The semiconductor package of claim 1, wherein
a vertical length (307_H) of a side surface of the second molding layer (307) that is in contact with the dummy chip (115) among side surfaces of the second molding layer (307) is less than a vertical length (307_H2) of a side surface of the second molding layer (307) that is exposed to the outside of the semiconductor package (300) among the side surfaces of the second molding layer (307).
Regarding Claim 8,
CHEN discloses:
The semiconductor package of claim 1, wherein
a vertical length (307_H2) of a side surface of the second molding layer (307) that is exposed to the outside of the semiconductor package (300) among side surfaces of the second molding layer (307) is greater than a vertical length (107_H) of a side surface of the first molding layer (107 of 117/107) that is exposed to the outside of the semiconductor package (300) among side surfaces of the first molding layer (117/107).
Regarding Claim 9,
CHEN discloses:
The semiconductor package of claim 1, wherein
a composition material of the first molding layer (117 of 117/107) is identical to a composition material of the second molding layer (307), and
(Part. 25)
a boundary surface (BS) is between the first molding layer (117 of 117/107) and the second molding layer (307).
Regarding Claim 10,
CHEN discloses:
The semiconductor package of claim 1,
wherein the uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor chips (CHP2) further comprises a bonding insulating material layer (701; Par. 46) on an upper surface of the uppermost second semiconductor chip (CHP2 of 113_1), and
wherein the uppermost surface (117_U) of the first molding layer (117 of 117/107) is coplanar with the (bottom of the) bonding insulating material layer (701).
Regarding Claim 11,
CHEN discloses:
The semiconductor package of claim 1, wherein
a thickness (CPH) of each of the plurality of second semiconductor chips (CHP2) is less than a thickness (307_H) of the dummy chip (115).
Regarding Claim 14,
CHEN discloses:
The semiconductor package of claim 1, wherein
a horizontal (overhang) length (115_O) of the dummy chip (115) is equal to or less than a (full) horizontal length of each of the plurality of second semiconductor chips (CHP2).
Regarding Claim 19,
CHEN discloses:
A semiconductor package (Fig. 3: 300) comprising:
a first semiconductor chip (405/407 combined of 105, hereinafter denoted CHP1; Par. 27 & 34) including
a first semiconductor substrate (405; Par. 27 & 34) comprising
an active surface (405/407 interface: “front surface” of 405, comprising devices; Par. 27 & 28) and
an inactive surface (405/607 interface: “backside surface” of 405, silent to comprising and not comprising devices; Par. 28) opposite to the active surface (405/407), and
Note, the adjective “inactive” for the limitation “inactive surface” constitutes a recitation with respect to the manner in which the claimed device is intended to be employed. Further, the prior art of record teaches all of the structural limitations of the claimed invention. Accordingly, this limitation does not differentiate the claimed invention from that of the prior art, consistent with Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987); MPEP § 2114(II).
a plurality of first through electrodes (409; Par. 28, See also Fig. 6F) penetrate the first semiconductor substrate (405);
a plurality of second semiconductor chips (405/407 combined of each 113, hereinafter denoted CHP2)
stacked on the first semiconductor chip (CHP1),
each of the plurality of second semiconductor chips (CHP2) including
a second semiconductor substrate (405) comprising
an active surface (405/407) and
an inactive surface (405/703 interface: “backside surface” of 405, silent to comprising and not comprising devices; Par. 28) opposite to the active surface (405/407) of the second semiconductor substrate (405);
Note, the adjective “inactive” for the limitation “inactive surface” constitutes a recitation with respect to the manner in which the claimed device is intended to be employed. Further, the prior art of record teaches all of the structural limitations of the claimed invention. Accordingly, this limitation does not differentiate the claimed invention from that of prior art, consistent with Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987); MPEP § 2114(II).
a first molding layer (117/107 combined; Par. 20 & 21 where a “molding layer” is understood to be formed of an “encapsulant” under a broadest reasonable interpretation.) including
a (communicating) trench (TR) that
surrounds side surfaces of the plurality of second semiconductor chips (CHP2) and
extends from (and above) an uppermost surface (117_U) of the first molding layer (117 of 117/107) into the first molding layer (117 of 117/107),
Note, 117 of 117/107 includes a “communicating trench” TR that extends into and through the entire thickness of 117 of 117/107, as seen from Fig. 9A. And, a “trench” may be construed to be a “communicating trench” under a broadest reasonable interpretation.
the first molding layer (117/107) including
a first side surface (107_S) and a second side surface (117_S) opposite to the first side surface (107_S);
Note, the normal of 107_S points in a direction opposite to the normal of 117_S. Accordingly, 117_S is opposite to 107_S under a broadest reasonable interpretation.
a dummy chip (115; Par. 21)
stacked on the plurality of second semiconductor chips (CHP2),
the dummy chip (115) having
a horizontal (overlapping) length (115_LP) identical to a (full) horizontal length of each of the plurality of second semiconductor chips (CHP2) and having
a height (307_H) greater than a height (CPH) of each of the plurality of second semiconductor chips (CHP2);
a second molding layer (307; Par. 25 where a “molding layer” is understood to be formed of an “encapsulant” under a broadest reasonable interpretation.)
surrounding side surfaces of the dummy chip (115),
filling the trench (TR), and
covering (the sides of) the first molding layer (117 of 117/107);
a package redistribution layer (RDL) under a lower surface of the first semiconductor chip (CHP1); and
a plurality of package connection terminals (111; Par. 24) electrically connected to the package redistribution layer (RDL),
wherein at least one of the plurality of second semiconductor chips (CHP2) comprises
a plurality of second through electrodes (409, see also Fig. 4A) penetrate the second semiconductor substrate (405) of the at least one of the plurality of second semiconductor chips (CHP2),
wherein the trench (TR) is arranged at a periphery of the uppermost surface (117_U) of the first molding layer (117 of 117/107),
wherein the first side surface (107_S) of the first molding layer (107 of 117/107) is exposed to an outside of the semiconductor package (300), and
the second side surface (117_S) of the first molding layer (117 of 117/107) is in contact with the plurality of second semiconductor chips (CHP2), and
wherein a height (107_H) of the first side surface (107_S) of the first molding layer (107 of 117/107) is less than a height (117_H) of the second side surface (117_S) of the first molding layer (117 of 117/107).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of UZOH (US 20200411483 A1).
Regarding Claim 12,
CHEN does not disclose:
The semiconductor package of claim 11, wherein
the thickness (CPH) of each of the plurality of second semiconductor chips (CHP2) is 20 μm to 80 μm, and the thickness (307_H) of the dummy chip (115) is 100 μm to 500 μm.
UZOH cures this deficiency by disclosing:
the thickness of each of the plurality of second semiconductor chips (Fig. 1: 102) is 20 μm to 80 μm (Par. 3), and the thickness of the dummy chip (106) is 100 μm to 500 μm (Par. 3).
And, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of CHEN with those of UZOH such that the chip thicknesses of CHEN follow the corresponding chip thicknesses of UZOH, thereby curing the aforementioned deficiency of CHEN, because CHEN discloses said plurality of second semiconductor chips and said dummy chip but does not disclose their corresponding thicknesses. Therefore, said person having ordinary skill would have been motivated to look to the prior art for appropriate thicknesses. Further, the corresponding thicknesses of UZOH are suitably appropriate, as both CHEN and UZOH regard a directly bonded chip stack package (CHEN Par. 19; UZOH Abstract). Moreover, said person having ordinary skill would have had a reasonable expectation of success in using the thicknesses of UZOH for the device of CHEN because doing so utilizes known methods—as presented by UZOH Par. 2 – 6 & 31 – 32—and said person having ordinary skill would have recognized that the associated results—as presented by UZOH Par. 2 – 6 & 31 – 32—were predictable. Accordingly, the claimed invention is not found to be patentably distinct from that of CHEN in view of UZOH, consistent with KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007); MPEP § 2143(I)(G).
Further, UZOH teaches the range 90 μm to 400 μm for the thickness of the dummy chip, which discloses the corresponding claimed range of 100 μm to 500 μm with sufficient specificity, as the instant disclosure provides no criticality for the instant claimed range relative to the disclosed range of UZOH, the disclosed range of UZOH is narrow about the instant claimed range, and the instant claimed range largely falls within the disclosed range of UZOH, consistent with MPEP § 2131.03(II).
Claim 13 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of BORST “Chemical-mechanical polishing of SiOC organosilicate glasses: the effect on film carbon content” (2001).
Regarding Claim 13,
CHEN discloses:
The semiconductor package of claim 1, wherein
…an upper surface (CPU) of the uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor (CHP2) chips is [subjected to a damascene process] (Par. 30).
CHEN does not disclose:
a surface roughness of an upper surface (CPU) of the uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor (CHP2) chips is 0.1 nm to 6 nm.
BORST cures this deficiency by disclosing:
a surface roughness of an upper surface of an analogous structure subjected to a damascene process is 0.1 nm to 6 nm (Table 4).
And, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of CHEN with those of BORST such that the damascene process of CHEN include the corresponding chemical mechanical polishing of BORST, thereby curing the aforementioned deficiency of CHEN, because CHEN discloses said damascene process but does not disclose many details pertaining thereto, including the known chemical mechanical polishing portion thereof (BORST Intro. & Par. 2.3). Therefore, said person having ordinary skill would have been motivated to look to the prior art for such details. Further, the corresponding details of BORST are suitably operative, as both CHEN and BORST regard a damascene process for forming copper interconnects in an SiOC layer (CHEN Par. 30; BORST Par. 2.3). Moreover, said person having ordinary skill would have had a reasonable expectation of success because they could have executed said modification by known methods—as presented by BORST Par. 2.3—and they would have recognized that the results of said modification—as presented by BORST Table 4—were predictable. Accordingly, the claimed invention is not found to be patentably distinct from that of CHEN in view of BORST, consistent with KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007); MPEP § 2143(I)(G).
Regarding Claim 20,
CHEN discloses:
The semiconductor package of claim 19, further comprising
a chip bonding insulating layer (417/501/703 combined of adjacent 113s; Par. 32, 34, & 49; See also Fig. 7E),
a support bonding insulating layer (701 combined with 417 of 113_1, hereinafter 417/701; Par. 46, See also Fig. 7A), and
a plurality of bonding pads (505; Par. 35, See also Fig. 7E),
wherein the plurality of bonding pads (505) are arranged between adjacent ones of the plurality of second semiconductor chips (CHP2), and electrically connect (Par. 50) the plurality of second semiconductor chips (CHP2) to each other,
wherein the chip bonding insulating layer (417/501/703) surrounds the plurality of bonding pads (505) and fills remaining spaces between the adjacent ones of the plurality of second semiconductor chips (CHP2),
wherein…an upper surface (CPU) of an uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor chips (CHP2) is [subjected to a damascene process] (Par. 30),
wherein the support bonding insulating layer (417/701)
is arranged between the uppermost second semiconductor chip (CHP2 of 113_1) and the dummy chip (115), and
has a (total vertical) thickness that is less than a (total horizontal) thickness of the chip bonding insulating layer (417/501/703), and
wherein a vertical level of the uppermost surface (117_U) of the first molding layer (117 of 117/107) is
lower than a vertical level of an upper surface (of 701) of the support bonding insulating layer (417/701), and
higher than a vertical level of a lower surface (of 417) of the support bonding insulating layer (417/701).
CHEN does not disclose:
a mean roughness of an upper surface (CPU) of an uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor chips (CHP2) is 0.1 nm to 6 nm
BORST cures this deficiency by disclosing:
The mean roughness of an upper surface of an analogous structure subjected to a damascene process is 0.1 nm to 6 nm (Table 4).
And, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of CHEN with those of BORST such that the damascene process of CHEN include the corresponding chemical mechanical polishing of BORST, thereby curing the aforementioned deficiency of CHEN, because CHEN discloses said damascene process but does not disclose many details pertaining thereto, including the known chemical mechanical polishing portion thereof (BORST Intro. & Par. 2.3). Therefore, said person having ordinary skill would have been motivated to look to the prior art for such details. Further, the corresponding details of BORST are suitably operative, as both CHEN and BORST regard a damascene process for forming copper interconnects in an SiOC layer (CHEN Par. 30; BORST Par. 2.3). Moreover, said person having ordinary skill would have had a reasonable expectation of success because they could have executed said modification by known methods—as presented by BORST Par. 2.3—and they would have recognized that the results of said modification—as presented by BORST Table 4—were predictable. Accordingly, the claimed invention is not found to be patentably distinct from that of CHEN in view of BORST, consistent with KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007); MPEP § 2143(I)(G).
Claim 15 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN as evidenced by CHEN2 (US 20210375819 A1).
Regarding Claim 15,
CHEN discloses:
A semiconductor package (Fig. 3: 300) comprising:
a first semiconductor chip (105; Par. 27 & 34) including
a first semiconductor substrate (405; Par. 27 & 34) comprising
an active surface (405/407 interface: “front surface” of 405, comprising devices; Par. 27 & 28) and
an inactive surface (405/607 interface: “backside surface” of 405, silent to comprising and not comprising devices; Par. 28) opposite to the active surface (405/407);
Note, the adjective “inactive” for the limitation “inactive surface” constitutes a recitation with respect to the manner in which the claimed device is intended to be employed. Further, the prior art of record teaches all of the structural limitations of the claimed invention. Accordingly, this limitation does not differentiate the claimed invention from that of the prior art, consistent with Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987); MPEP § 2114(II).
a plurality of second semiconductor chips (405/407 combined of each 113, hereinafter denoted CHP2)
stacked on the first semiconductor chip (105),
each of the plurality of second semiconductor chips (CHP2) including
a second semiconductor substrate (405) comprising
an active surface (405/407) and
an inactive surface (405/703: “backside surface” of 405, silent to comprising and not comprising devices; Par. 28) opposite to the active surface (405/407) of the second semiconductor substrate (405);
Note, the adjective “inactive” for the limitation “inactive surface” constitutes a recitation with respect to the manner in which the claimed device is intended to be employed. Further, the prior art of record teaches all of the structural limitations of the claimed invention. Accordingly, this limitation does not differentiate the claimed invention from that of prior art, consistent with Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987); MPEP § 2114(II).
a first molding layer (117/107 combined; Par. 20 & 21 where a “molding layer” is understood to be formed of an “encapsulant” under a broadest reasonable interpretation.)
covering a portion of an upper surface of the first semiconductor chip (105) and side surfaces of the plurality of second semiconductor chips (CHP2),
the first molding layer (117/107) including
a (communicating) trench (TR) that extends from (and above) an uppermost surface (117_U) of the first molding layer (117 of 117/107) into the first molding layer (117 of 117/107);
Note, 117 of 117/107 includes a “communicating trench” TR that extends into and through the entire thickness of 117 of 117/107, as seen from Fig. 9A. And, a “trench” may be construed to be a “communicating trench” under a broadest reasonable interpretation.
a dummy chip (115; Par. 21)
stacked on an uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor chips (CHP2); and
a second molding layer (307; Par. 25 where a “molding layer” is understood to be formed of an “encapsulant” under a broadest reasonable interpretation.)
surrounding side surfaces of the dummy chip (115),
filling the trench (TR), and
covering the uppermost surface (117_U) of the first (117 of 117/107) molding layer (when viewed from D2 or D2 ± π/2),
wherein the plurality of second semiconductor chips (CHP2) are
stacked with the active surface (405/407) of the second semiconductor substrate (405) of each of the plurality of second semiconductor chips (CHP2) facing [away from] the first semiconductor chip (105).
CHEN does not disclose:
the plurality of second semiconductor chips (CHP2) are
stacked with the active surface (405/407) of the second semiconductor substrate (405) of each of the plurality of second semiconductor chips (CHP2) facing the first semiconductor chip (105).
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of CHEN such that the plurality of second semiconductor chips are stacked with the active surface of the second semiconductor substrate of each of the plurality of second semiconductor chips facing the first semiconductor chip, thereby curing the aforementioned deficiency of CHEN, because this claimed arrangement is a matter of design choice, as Applicant does not disclose said claimed arrangement solves a stated problem; presents a novel or unexpected result; functions; achieves a purpose; or provides factual benefits different than the corresponding known arrangement, wherein the plurality of second semiconductor chips are stacked with the active surface of the second semiconductor substrate of each of the plurality of second semiconductor chips facing away from the first semiconductor chip. Moreover, said person having ordinary skill would have had a reasonable expectation of success because they could have executed said modification by known methods—as evidenced by CHEN2 Par. 24 – 37—and they would have recognized that the results of said modification—the similar device of CHEN2 Fig. 9—were predictable. Accordingly, the claimed invention is not found to be patentably distinct from that of CHEN as evidence by CHEN2, consistent with In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975); MPEP § 2144.04(VI)(C).
Regarding Claim 16,
CHEN discloses:
The semiconductor package of claim 15, further comprising
a plurality of bonding pads (505; Par. 35, See also Fig. 7E) and
a plurality of chip bonding insulating layers (417/501/703 combined of adjacent 113s; Par. 32, 34, & 49; See also Fig. 7E),
wherein the plurality of bonding pads (505) are arranged between adjacent ones of the plurality of second semiconductor chips (CHP2), and
electrically connect (Par. 50) the plurality of second semiconductor chips (CHP2) to each other, and
wherein each of the plurality of chip bonding insulating layers (417/501/703) surrounds the plurality of bonding pads (505) and
fills a remaining space between the adjacent ones of the plurality of second semiconductor chips (CHP2).
Regarding Claim 17,
CHEN discloses:
The semiconductor package of claim 16, further comprising
a support bonding insulating layer (701 combined with 417 of 113_1, hereinafter 417/701; Par. 46, See also Fig. 7A) having a (total vertical) thickness that is less than a (total horizontal) thickness of each of the plurality of chip bonding insulating layers (417/501/703),
wherein the support bonding insulating layer (417/701) is arranged between the dummy chip (115) and the uppermost second semiconductor chip (CHP2 of 113_1) among the plurality of second semiconductor chips (CHP2), and
wherein the uppermost second semiconductor chip (CHP2 of 113_1) is connected to the dummy chip (115) by the support bonding insulating layer (417/701).
Regarding Claim 18,
CHEN discloses:
The semiconductor package of claim 17, wherein
a vertical level of the uppermost surface (117_U) of the first molding layer (117 of 117/107) is
lower than a vertical level of an upper surface (of 701) of the support bonding insulating layer (417/701), and
higher than a vertical level of a lower surface (of 417) of the support bonding insulating layer (417/701).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
