Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Authorization for Internet Communications in a Patent Application
Applicant is encouraged to file an Authorization for Internet Communications in a Patent Application form (http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) along with the response to this office action to facilitate and expedite future communication between Applicant and the examiner. If the form is submitted then Applicant is requested to provide a contact email address in the signature block at the conclusion of the official reply.
35 USC § 112(f) – Claim Interpretation
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “a progress detection subunit having circuitry configured to”, “a transmission subunit having circuitry configured to”, and “a transfer subunit having circuitry configured to” in claims 1 and 14.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If Applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) Applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-6, 12-14, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hyodo et al. (US 2007/0021847) (hereinafter Hyodo) in view of Branover et al. (US 2021/0173715) (hereinafter Branover).
As per claim 1, Hyodo primarily teaches the invention as claimed including a task scheduling unit, comprising:
a progress detection subunit having circuitry configured to obtain first progress information of a first chip in which the task scheduling unit is located, the first progress information indicating a task execution progress of the first chip ([0053] judge whether the ECU can complete task execution to strictly observe deadlines for execution of all executable tasks and judge whether remaining tasks in an executable state can be executed to completion no later than the respective deadlines);
a transmission subunit having circuitry configured to transmit the first progress information to a second chip ([0042]-[0043] when task execution is requested from ECU 1 to ECU 2, input data that was collected into the RAM area of ECU 1 is rearranged into a packet format inside a communications device COM 1 and then delivered to a communications device COM 2 of the ECU 2 so that ECU 2 can execute the task transferred from ECU 1 using the task input data in the memory and [0054]-[0056] ECU 1 judges whether the selected task, when its processing is requested to be transferred to ECU 2, can be executed to completion no later than its time deadline. The judgment is based on an execution time of the task, a data transfer time thereof, and other information given beforehand. ECU 1 inquiries of ECU 2 whether it can accept the transfer of the task to guarantee that the task deadline is met based on the aforementioned task information and the workload of ECU 2), and the task execution progress of the first chip is less than a task execution progress of the second chip ([0052] CPU monitor of ECU 1 monitors a workload of its own CPU, and if the CPU workload exceeds a previously set threshold, ECU 1 can start to transfer a task. ECU 2 also has a CPU monitor which enables ECU 2 to determine from its CPU workload monitoring results whether a task transfer and execution request from the ECU 1 is to be accepted and [0056]-[0057] ECU 1 inquires of ECU 2 whether ECU 2 can guarantee completion of selected task to be transferred within the deadline, and if ECU 2 accepts the request then ECU 1 transfers the task to ECU 2 and ECU 2 executes the transferred task); and
a transfer subunit having circuitry configured to:
receive first request information transmitted by the second chip in response to the first progress information ([0055] the ECU that has received the above inquiry refers to the workload monitor of the ECU's own CPU or to previously given information on the corresponding task and judges whether the execution request can be accepted. The ECU sends judgment results as a reply to the request source ECU); and
transfer at least some of tasks executed by the first chip to the second chip for execution based on the first request information ([0056]-[0057] ECU 1 inquires of ECU 2 whether ECU 2 can guarantee completion of selected task to be transferred within the deadline, and if ECU 2 accepts the request then ECU 1 transfers the task to ECU 2 and ECU 2 executes the transferred task), wherein the first request information is generated by the second chip based on the first progress information and the task execution progress of the second chip ([0052] CPU monitor of ECU 1 monitors a workload of its own CPU, and if the CPU workload exceeds a previously set threshold, ECU 1 can start to transfer a task. ECU 2 also has a CPU monitor which enables ECU 2 to determine from its CPU workload monitoring results whether a task transfer and execution request from the ECU 1 is to be accepted and [0055] the ECU that has received the above inquiry refers to the workload monitor of the ECU's own CPU or to previously given information on the corresponding task and judges whether the execution request can be accepted. The ECU sends judgment results as a reply to the request source ECU).
Hyodo does not explicitly teach:
wherein the first chip and the second chip are located on a same wafer.
However, Branover teaches:
wherein the first chip and the second chip are located on a same wafer ([0027] a CPU and GPU located on the same die, or one or more processor cores and [0048] on a condition that a direct memory access progress rate of the relatively less-powerful processor is below its associated threshold, the system determines that the relatively less-powerful processor is over-utilized and unable to make sufficient progress in processing the task. As such, the task is relocated to the relatively more-powerful processor and abstract to relocate one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor and [0040] system on a chip and [0063] different circuits).
Branover and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover because it would provide a way for a task to be moved to the relatively more-powerful processor from the relatively less-powerful processor so that the relatively less-powerful processor can be powered down or otherwise placed in a low-power state thereby resulting in improved performance efficiency by avoiding unnecessary power consumption.
As per claim 3, Hyodo further teaches wherein the transfer subunit has circuitry configured to transmit first transfer information to the second chip ([0042]-[0043] when task execution is requested from ECU 1 to ECU 2, input data that was collected into the RAM area of ECU 1 is rearranged into a packet format inside a communications device COM 1 and then delivered to a communications device COM 2 of the ECU 2 so that ECU 2 can execute the task transferred from ECU 1 using the task input data in the memory and [0054]-[0056] ECU 1 judges whether the selected task, when its processing is requested to be transferred to ECU 2, can be executed to completion no later than its time deadline. The judgment is based on an execution time of the task, a data transfer time thereof, and other information given beforehand. ECU 1 inquiries of ECU 2 whether it can accept the transfer of the task to guarantee that the task deadline is met based on the aforementioned task information and the workload of ECU 2).
As per claim 5, the combination of references above further teaches the task scheduling unit according to claim 1, wherein the transfer subunit has circuitry configured to receive second progress information transmitted by a third chip (Hyodo [0053] judge whether the ECU can complete task execution to strictly observe deadlines for execution of all executable tasks and judge whether remaining tasks in an executable state can be executed to completion no later than the respective deadlines), wherein the first chip and the third chip are located on the same wafer (Branover [0027] a CPU and GPU located on the same die, or one or more processor cores and [0048] on a condition that a direct memory access progress rate of the relatively less-powerful processor is below its associated threshold, the system determines that the relatively less-powerful processor is over-utilized and unable to make sufficient progress in processing the task. As such, the task is relocated to the relatively more-powerful processor); and the transmission subunit is further configured to: determine a task execution progress of the third chip based on the second progress information (Hyodo [0055] the ECU that has received the above inquiry refers to the workload monitor of the ECU's own CPU or to previously given information on the corresponding task and judges whether the execution request can be accepted. The ECU sends judgment results as a reply to the request source ECU); and transmit second request information to the third chip when the task execution progress of the third chip and the task execution progress of the first chip satisfy a task transfer condition, to request to transfer at least some of tasks executed by the third chip to the first chip for execution (Hyodo [0056]-[0057] ECU 1 inquires of ECU 2 whether ECU 2 can guarantee completion of selected task to be transferred within the deadline, and if ECU 2 accepts the request then ECU 1 transfers the task to ECU 2 and ECU 2 executes the transferred task), wherein the first request information is generated by the second chip based on the first progress information and the task execution progress of the second chip ([0052] CPU monitor of ECU 1 monitors a workload of its own CPU, and if the CPU workload exceeds a previously set threshold, ECU 1 can start to transfer a task. ECU 2 also has a CPU monitor which enables ECU 2 to determine from its CPU workload monitoring results whether a task transfer and execution request from the ECU 1 is to be accepted and [0055] the ECU that has received the above inquiry refers to the workload monitor of the ECU's own CPU or to previously given information on the corresponding task and judges whether the execution request can be accepted. The ECU sends judgment results as a reply to the request source ECU).
As per claim 6, Hyodo further teaches wherein the transfer subunit has circuitry configured to: receive second transfer information transmitted by the third chip in response to the second request information ([0055] the ECU that has received the above inquiry refers to the workload monitor of the ECU's own CPU or to previously given information on the corresponding task and judges whether the execution request can be accepted. The ECU sends judgment results as a reply to the request source ECU); and execute a task of transferring from the third chip to the first chip based on the second transfer information ([0056]-[0057] ECU 1 inquires of ECU 2 whether ECU 2 can guarantee completion of selected task to be transferred within the deadline, and if ECU 2 accepts the request then ECU 1 transfers the task to ECU 2 and ECU 2 executes the transferred task).
As per claim 12, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 13, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 16, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 6 and is therefore rejected using the same rationale.
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hyodo in view of Branover in view of Braun et al. (US 2017/0206139) (hereinafter Braun).
As per claim 2, Hyodo in view of Branover do not explicitly teach wherein the progress detection subunit has circuitry configured to: detect a number of completions of an operation loop in the first chip; and determine the number of completions as the first progress information, wherein the operation loop comprises at least one operation instruction.
However, Braun teaches wherein the progress detection subunit has circuitry configured to: detect a number of completions of an operation loop in the first chip; and determine the number of completions as the first progress information, wherein the operation loop comprises at least one operation instruction ([0007] check whether the single-chip system is in a cyclic reset loop. If a cyclic reset loop of this kind for the single-chip system is detected, then the restart monitoring device may be designed to deactivate the single-chip system or to transfer it to an idle mode in order to prevent a single-chip system from constantly consuming current when this reset loop is executed. In this case, the restart monitoring device may be embodied as a reset counter that deactivates the single-chip system or transfers it to the idle mode when the number of reset loops executed exceeds a prescribed threshold value).
Braun and Hyodo are both concerned with task execution in vehicular computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of Braun because it would provide a way to ensure that the battery of the motor vehicle is not discharged by an erroneous cycle of restarts by the single-chip system. That is to say that this protects the battery of the motor vehicle against discharge and that the availability and reliability of the battery is therefore also increased.
As per claim 15, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hyodo in view of Branover in view of Shows (US 2015/0007187).
As per claim 4, Hyodo in view of Branover do not explicitly teach wherein the transfer subunit has circuitry configured to: determine to-be-transferred tasks that need to be transferred to the second chip based on a number of tasks that the first request information requests to transfer and a number of to-be-executed tasks of the first chip; and transfer the to-be-transferred tasks to the second chip for execution, wherein the number of the to-be-transferred tasks is less than the number of the to-be-executed tasks.
However, Shows teaches wherein the transfer subunit has circuitry configured to: determine to-be-transferred tasks that need to be transferred to the second chip based on a number of tasks that the first request information requests to transfer and a number of to-be-executed tasks of the first chip; and transfer the to-be-transferred tasks to the second chip for execution, wherein the number of the to-be-transferred tasks is less than the number of the to-be-executed tasks ([0038]-[0040] and [0043] determine number of threads to be reassigned for execution based on number of threads to be executed on assigned cores and based on an overall maximum threshold count e.g., an assignment of threads to greater than a certain percentage of cores).
Shows and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of Shows because it would provide for a thread optimizer, which is an enhancement to thread scheduling logic that performs the symmetric re-distribution of turbo mode threads among the multiple available sockets, during the initial assignment of the turbo mode threads, to enable higher overall CPU performance. The thread optimizer identifies computing resource intensive threads or threads requiring turbo mode execution and determines if execution of the turbo mode threads can be more efficiently accomplished on another processor.
As per claim 17, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hyodo in view of Branover in view of He et al. (US 2014/0181825) (hereinafter He).
As per claim 7, Hyodo in view of Branover do not explicitly teach wherein the task transfer condition comprises: a difference between the task execution progress of the first chip and the task execution progress of the third chip is greater than an execution progress threshold; or a difference between a predicted time for the second chip to execute the remaining tasks and a predicted time for the first chip to execute the remaining tasks is greater than a time threshold.
However, He teaches wherein the task transfer condition comprises: a difference between the task execution progress of the first chip and the task execution progress of the third chip is greater than an execution progress threshold; or a difference between a predicted time for the second chip to execute the remaining tasks and a predicted time for the first chip to execute the remaining tasks is greater than a time threshold ([0064] scheduling module determines whether there is an in-progress job on a lower-performing processing module that has a level of urgency which exceeds a prescribed urgency threshold by determining whether any in-progress job has been running on a lower-performing processing module for more than a prescribed amount of time without completing. If so, the scheduling module determines whether there is a higher-performing processing module that is available. And if so, the scheduling module moves the in-progress job to the highest-performing processing module that is currently available).
He and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of He because it would enable a scheduling module to dynamically adapt to changes in the nature of job requests that are received over time, and changes in the volume of such requests. This may have certain performance advantages in certain circumstances over a fixed heterogeneous configuration, e.g., as measured in terms of average quality, throughput, and/or energy efficiency; these advantages may be more pronounced when the traffic that is received is highly variable.
As per claim 20, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hyodo in view of Branover in view of Lai (US 2022/0357392).
As per claim 8, Hyodo in view of Branover do not explicitly teach wherein the transmission subunit has circuitry configured to: transmit to-be-transmitted information to a target chip located on the same wafer as the first chip through broadcasting.
However, Lai teaches wherein the transmission subunit has circuitry configured to: transmit to-be-transmitted information to a target chip located on the same wafer as the first chip through broadcasting ([0011] generate broadcast test signals configured to be distributed to the chips in parallel according to the selected test signal. In this way, the chips on the semiconductor wafer may be tested in parallel according to the received broadcast test signals).
Lai and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of Lai because it would result in improved testing efficiency because the number of parallel tests may be increased, so the efficiency of chip testing is improved, and complexity and costs of the test fixture may also be reduced. In addition, the accuracy of chip testing may be improved, and the probability of overkilling may be reduced.
As per claim 10, Hyodo in view of Branover do not explicitly teach wherein the transfer subunit has circuitry configured to: receive information transmitted by a source chip located on the same wafer as the first chip through broadcasting.
However, Lai teaches wherein the transfer subunit has circuitry configured to: receive information transmitted by a source chip located on the same wafer as the first chip through broadcasting ([0011] generate broadcast test signals configured to be distributed to the chips in parallel according to the selected test signal. In this way, the chips on the semiconductor wafer may be tested in parallel according to the received broadcast test signals).
Lai and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of Lai because it would result in improved testing efficiency because the number of parallel tests may be increased, so the efficiency of chip testing is improved, and complexity and costs of the test fixture may also be reduced. In addition, the accuracy of chip testing may be improved, and the probability of overkilling may be reduced.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hyodo in view of Branover in view of Zortman et al. (US 10,429,438) (hereinafter Zortman).
As per claim 9, Hyodo in view of Branover do not explicitly teach wherein the transmission subunit has circuitry configured to: attach to-be-transmitted information to interaction data between the first chip and a target chip located on the same wafer as the first chip.
However, Zortman teaches wherein the transmission subunit has circuitry configured to: attach to-be-transmitted information to interaction data between the first chip and a target chip located on the same wafer as the first chip (col. 10, ll. 46-48 measured data is stored to be combined with data from other chips on the same wafer as they arrive).
Zortman and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of Zortman because it would provide a way for a customer to monitor full and partial wafer data for statistical differences and correlate that with other indicators. As full wafer sets are built, some integrated chips can be selected for destructive testing to facilitate further confidence that the remainder of the integrated chips from that wafer have the same, expected qualities.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hyodo in view of Branover in view of Tailliet et al. (US 2012/0250429) (hereinafter Tailliet).
As per claim 11, Hyodo in view of Branover do not explicitly teach wherein the transfer subunit is configured to: parse information transmitted by a source chip to the first chip from interaction data transmitted by the source chip to the first chip, where the source chip and the first chip are located on a same wafer.
However, Tailliet teaches wherein the transfer subunit is configured to: parse information transmitted by a source chip to the first chip from interaction data transmitted by the source chip to the first chip, where the source chip and the first chip are located on a same wafer ([0027] the second entity has an integrated-circuit fabrication device including a reader for reading the test result data from the memory of the processing chips on the wafer. The device then dices the various chips and separates off the defective chips, identified by the data read during the preceding step).
Tailliet and Hyodo are both concerned with task execution in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hyodo in view of Branover in view of Tailliet because it would provide for an advantageous test procedure, and more generally a process for fabricating integrated circuits, to be implemented. The test procedure includes a step of writing data representing the results of the test into a memory present on the wafer itself. This avoids having to mark the wafer with ink, or having to manage an external file independent of the wafer. This is advantageous and allows for an effective automatic processing of the wafer, and provides a rapid and reliable process for fabricating integrated circuits.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Woo et al. (US 2024/0248609) disclose the managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.
Arimilli et al. (US 2009/0064168) disclose dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner’s supervisor, Pierre Vital, can be reached at the following telephone number: (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 September 8, 2026
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