DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device Metal Pads with Carbon Film Filled Recess and Manufacturing Method of The Same.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9, 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Uozumi (US 2021/0091024) in view of Wakatsuki (US 2021/0296253).
Regarding Claim 1, Uozumi discloses a semiconductor device (semiconductor device 1A [0020] Fig 1) comprising:
a first chip (first semiconductor substrate 2 [0021] Fig 1) including a first metal pad (first metal pad 5 [0022] Fig 1) provided on a first surface of the first chip (2 Fig 1) and a first circuit (first circuit region 12 [0022] Fig 1) connected to the first metal pad (5 Fig 1); and
a second chip (second semiconductor substrate 3 [0022] Fig 1) having a second surface bonded to the first surface of the first chip (2 Fig 1), the second chip (3 Fig 1) including a second metal pad (second metal pad 8 [0021] Fig 1) provided on the second surface and bonded to the first metal pad (5 Fig 1), and
a second circuit (second circuit region 14 [0022] Fig 1) connected to the second metal pad (8 Fig 1).
Uozumi does not disclose
wherein the first metal pad as a first recess formed in the first surface, and a first carbon film is provided in the first recess.
Wakatsuki, in the related art of semiconductor devices that include memory devices, discloses
wherein the first metal pad (second metal pad 62 [0041] Fig 3) as a first recess (recess [0041]) formed in the first surface, and a first carbon film (carbon is introduced which may be determined depending on the degrees of recess [0041] Fig 3) is provided in the first recess.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Uozumi to include a first carbon film provided in the first recess as taught by Wakatsuki in order to increase the volume of the metal pads to correct for dishing [0038]. Further, a person of ordinary skill in the art would have recognized that correcting for dishing would be advantageous in providing a bonding surface with less defects which would improve the electrical functioning while improving the reliability of the device (see MPEP 2143.I(D)).
Regarding Claim 2, the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein the first chip (first semiconductor substrate 2 [0021] Fig 1 Uozumi) includes a first substrate (substrate 17 [0024] Uozumi) on which the first metal pad (first metal pad 5 [0022] Fig 1 Uozumi) and the first circuit (first circuit region 12 [0022] Fig 1 Uozumi) are provided.
Regarding Claim 3, the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein one of the first circuit (first circuit region 12 [0022] Fig 1 Uozumi) and the second circuit (second circuit region 14 [0022] Fig 1 Uozumi) includes a memory cell array (second circuit region 14 may be a memory cell array [0022] Uozomi), which is connected to a corresponding one of the first metal pad (5 Fig 1 Uozumi) and the second metal pad (8 Fig 1 Uozumi) via a wiring (wiring layer (not shown) [0022] Uozumi), and
the other of the first circuit (12 Fig 1 Uozumi) and the second circuit (14 Uozumi) includes a control circuit (first chip 2 that is related to first circuit region 12 may be a control chip [0022] Uozumi) configured to control the memory cell array, the control circuit including a transistor (first circuit may be a peripheral circuit such as a transistor like a CMOS [0022] Uozumi), which is connected to the other of the first metal pad (5 Fig 1 Uozumi) and the second metal pad (8 Fig 1 Uozumi) via a wiring (wiring layer (not shown) [0022] Uozumi).
Regarding Claim 4, the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein the first carbon film (carbon is introduced which may be determined depending on the degrees of recess [0041] Fig 3 Wakatsuki) is provided along an outer periphery of the first metal pad (second metal pad 62 [0041] Fig 3 Wakatsuki) on the first surface.
Regarding Claim 5, the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein a surface area of the first metal pad (5 Fig 1 Uozumi) on the first surface and a surface area of the second metal pad (8 Fig 1 Uozumi) on the second surface are substantially the same (shown in Fig 3 Uozumi, the examiner notes that the first metal pad 5 and the second metal pad 8 in a plan view would show a substantially the same surface area), and
the first metal pad (3 Fig 1 Uozumi) and the second metal pad (8 Fig 1 Uozumi) are bonded with an offset (shown in Fig 3 Uozumi) from each other in a direction that is parallel to the first and second surfaces (shown in Fig 3 Uozumi).
Regarding Claim 6, the combination of Uozumi and Wakatsuki discloses the limitations of claim 5 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein at least a part of the first carbon film (carbon [0041] Wakatsuki) on the first surface is not in contact (the examiner notes that although the top surface of the carbon filled recess would be in physical contact with the second metal pad, the remaining lower portion of the carbon filled recess would not be in physical contact with the second metal pad and would meet this claim limitation) with the second metal pad (8 Fig 1 Uozumi/first metal pad 72 [0041] Fig 3 Wakatsuki).
Regarding Claim 7, the combination of Uozumi and Wakatsuki discloses the limitations of claim 6 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein at least a part of the first carbon film (carbon [0041] Wakatsuki) on the first surface is in contact (the examiner notes that at least the top surface of the carbon filled recess would be in physical contact with the second metal pad and would meet this claim limitation) with the second metal pad (8 Fig 1 Uozumi/first metal pad 72 [0041] Fig 3 Wakatsuki).
Regarding Claim 8, the combination of Uozumi and Wakatsuki discloses the limitations of claim 5 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein the second metal pad (8 Fig 1 Uozumi/72 Fig 3 Wakatsuki) has a second recess [0041] formed in the second surface, and a second carbon film (carbon [0041]) is provided in the second recess [0041].
Regarding Claim 9, the combination of Uozumi and Wakatsuki discloses the limitations of claim 9 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein at least a part of the second carbon film on the second surface is not in contact with the first metal pad (3 Fig 1 Uozumi/62 Fig 3 Wakatsuki), and at least a part of the second carbon film (carbon [0041]) on the second surface is in contact (the examiner notes that at least the top surface of the second carbon filled recess would be in physical contact with the first metal pad and would meet this claim limitation) with the first metal pad (3 Fig 1 Uozumi/62 Fig 3 Wakatsuki).
Regarding Claim 14, the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein the first chip (first semiconductor substrate 2 [0021] Fig 1 Uozumi) further includes a first insulating layer (first insulating layer 7 [0021] Fig 1 Uozumi) in which the first metal pad (first metal pad 5 [0022] Fig 1 Uozumi) is formed, the first surface being formed with the first insulating layer (7 Fig 1 Uozumi), the first metal pad (first metal pad 5 [0022] Fig 1 Uozumi), and the first carbon film (carbon [0041] Wakatsuki), and
the second chip (second semiconductor substrate 3 [0022] Fig 1 Uozumi) further includes a second insulating layer (second insulating layer 10 [0021] Fig 1 Uozumi) in which the second metal pad (second metal pad 8 [0021] Fig 1 Uozumi) is formed, the second surface being formed with the second insulating layer (10 Fig 1 Uozumi) and the second metal pad (second metal pad 8 [0021] Fig 1 Uozumi).
Regarding Claim 15, the combination of Uozumi and Wakatsuki discloses the limitations of claim 14 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein a thermal expansion coefficient of a material of the first metal pad (first metal pad 5 [0022] may be copper [0024] Fig 1 Uozumi) is higher than a thermal expansion coefficient of a material of the first insulating layer and higher than a thermal expansion coefficient of a material of the second insulating layer, and
a thermal expansion coefficient (copper has a thermal expansion coefficient of 16.5 to 17 ppm/degree Celsius) of a material of the second metal pad (second metal pad 8 [0021] may be made of copper [0024] Fig 1 Uozumi) is higher than the thermal expansion coefficient (silicon oxide has a coefficient of thermal expansion of 0.55 to 0.75 ppm/degree Celsius) of the material of the first insulating layer (first insulating layer 7 [0021] may be made of silicon oxide [0024] Fig 1 Uozumi) and higher than the thermal expansion coefficient (silicon oxide has a coefficient of thermal expansion of 0.55 to 0.75 ppm/degree Celsius) of the material of the second insulating layer (second insulating layer 10 [0021] may be made of silicon oxide [0024] Fig 1 Uozumi).
Regarding Claim 16, the combination of Uozumi and Wakatsuki discloses the limitations of claim 14 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein the first metal pad (first metal pad 5 [0022] may be copper [0024] Fig 1 Uozumi) and the second metal pad (second metal pad 8 [0021] may be made of copper [0024] Fig 1 Uozumi) are each formed of copper or a copper alloy.
Regarding Claim 17, Uozumi discloses a method for manufacturing a semiconductor device (semiconductor device 1A [0020] Fig 1), comprising:
preparing a first chip component (component that includes first semiconductor substrate 2 [0021] Fig 1) having a first semiconductor substrate (first semiconductor substrate 2 [0021] Fig 1),
a first metal pad (first metal pad 5 [0022] Fig 1) exposed on a first surface of the first chip component (component that includes first semiconductor substrate 2 [0021] Fig 1), and
a first circuit (first circuit region 12 [0022] Fig 1) connected to the first metal pad (5 Fig 1);
preparing a second chip component (component that includes second semiconductor substrate 3 [0022] Fig 1) having a second semiconductor substrate (second semiconductor substrate 3 [0022] Fig 1),
a second metal pad (second metal pad 8 [0021] Fig 1) exposed on a second surface of the second chip component (component that includes second semiconductor substrate 3 Fig 1), and
a second circuit (second circuit region 14 [0022] Fig 1) connected to the second metal pad (8 Fig 1).
Uozumi does not disclose
forming a carbon or organic film on the first metal pad;
after said forming the carbon or organic film, placing the first chip component and the second chip component such that the first surface contacts the second surface and the first metal pad faces the second metal pad via the carbon or organic film; and
bonding the first metal pad and the second metal pad with heat.
Wakatsuki, in the related art of semiconductor devices that include memory devices, discloses
forming a carbon (carbon [0041]) or organic film on the first metal pad (second metal pad 62 [0041] Fig 3);
after said forming the carbon (carbon is introduced which may be determined depending on the degrees of recess [0041] Fig 3) or organic film,
placing the first chip component (component that includes circuit chip 2 [0025] Fig 1 and Fig 3) and the second chip component (component that includes such that the first surface contacts the second surface and the first metal pad (62 Fig 3) faces the second metal pad (first metal pad 72 [0041] Fig 3) via the carbon (carbon [0041]) or organic film (shown in Fig 3); and
bonding the first metal pad (62 Fig 3) and the second metal pad (72 Fig 3) with heat (heat is applied to bond array wafer W1 and array wafer W2 together [0060] Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Uozumi to include a first carbon film provided in the first recess as taught by Wakatsuki in order to increase the volume of the metal pads to correct for dishing [0038]. Further, a person of ordinary skill in the art would have recognized that correcting for dishing would be advantageous in providing a bonding surface with less defects which would improve the electrical functioning while improving the reliability of the device (see MPEP 2143.I(D)).
Regarding Claim 18, the combination of Uozumi and Wakatsuki discloses the limitations of claim 17 as explained above. The combination of Uozumi and Wakatsuki further discloses
wherein during said bonding (bonding [0042] Wakatsuki), a carbon film derived from the carbon (carbon [0040]-[0041] Wakatsuki) or organic film is formed in a recess (recess of the metal pads [0041] Wakatsuki) that is formed along an outer periphery of at least one of the first metal pad (second metal pad 62 [0041] Fig 3 Wakatsuki) and the second metal pad (first metal pad 72 [0041] Fig 3 Wakatsuki).
Regarding Claim 19, the combination of Uozumi and Wakatsuki discloses the limitations of claim 17 as explained above. The combination of Uozumi and Wakatsuki further discloses
further comprising: performing a chemical mechanical polishing (CMP) (chemical mechanical polishing CMP [0039] Fig 3 Wakatsuki) on the first surface of the prepared first chip component (component that includes circuit chip 2 [0025] Fig 1 and Fig 3 Wakatsuki), an exposed surface of the first metal pad (second metal pad 62 [0041] Fig 3 Wakatsuki) being recessed as a result of the CMP (CMP [0039]-[0040] Wakatsuki),
wherein the carbon (carbon [0040]-[0041] Wakatsuki) or organic film is formed on the recessed (recess of the metal pads [0041] Wakatsuki) exposed surface of the first metal pad (62 Fig 3 Wakatsuki).
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Uozumi (US 2021/0091024) in view of Wakatsuki (US 2021/0296253), and in further view of Makala et al (US 2021/0028149).
Regarding Claim 10, the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki does not directly disclose
wherein a surface area of the first metal pad on the first surface and a surface area of the second metal pad on the second surface are different, and
a region of one of the first metal pad on the first surface and the second metal pad on the second surface is entirely overlapped by a region of the other.
Makala et al, in the related art of semiconductor devices that include bonding pads, discloses
wherein a surface area of the first metal pad (second bonding pads 788 [0044] Fig 9 viewed from 180 degrees) on the first surface and a surface area of the second metal pad (first bonding pads 988 [0044] Fig 9 viewed from 180 degrees on the second surface are different (shown in Fig 9 viewed from 180 degrees, the examiner notes that in the surface areas of 788 and 988 would be different in a plan view), and
a region (middle region) of one of the first metal pad (788 Fig 9 viewed from 180 degrees) on the first surface and the second metal pad (988 Fig 9 viewed from 180 degrees) on the second surface is entirely overlapped (shown in Fig 9 viewed from 180 degrees) by a region of the other.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Uozumi and Wakatsuki to include wherein a surface area of the first metal pad on the first surface and a surface area of the second metal pad on the second surface are different, and a region of one of the first metal pad on the first surface and the second metal pad on the second surface is entirely overlapped by a region of the other as taught by Makala et al in order to optimize current flow between the first semiconductor die and the semiconductor die [0076]. Further, a person ordinary skill in the art would have recognized that optimizing the current flow between the first semiconductor die and the second semiconductor die would be advantageous in that having less current flow would optimize the durability and reliability of the device while having more current flow would optimize the electrical functioning capability of the device (see MPEP 2143.I(D)).
Regarding Claim 10 (the examiner notes that this claim is rejected with a different interpretation to reject dependent claim 12), the combination of Uozumi and Wakatsuki discloses the limitations of claim 1 as explained above. The combination of Uozumi and Wakatsuki does not directly disclose
wherein a surface area of the first metal pad on the first surface and a surface area of the second metal pad on the second surface are different, and
a region of one of the first metal pad on the first surface and the second metal pad on the second surface is entirely overlapped by a region of the other.
Makala et al, in the related art of semiconductor devices that include bonding pads, discloses
wherein a surface area of the first metal pad (first bonding pads 988 [0044] Fig 9) on the first surface and a surface area of the second metal pad (second bonding pads 788 [0044] Fig 9) on the second surface are different (shown in Fig 9, the examiner notes that in the surface areas of 788 and 988 would be different in a plan view), and
a region (middle region) of one of the first metal pad (988 Fig 9) on the first surface and the second metal pad (788 Fig 9) on the second surface is entirely overlapped (shown in Fig 9) by a region of the other.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Uozumi and Wakatsuki to include wherein a surface area of the first metal pad on the first surface and a surface area of the second metal pad on the second surface are different, and a region of one of the first metal pad on the first surface and the second metal pad on the second surface is entirely overlapped by a region of the other as taught by Makala et al in order to optimize current flow between the first semiconductor die and the semiconductor die [0076]. Further, a person ordinary skill in the art would have recognized that optimizing the current flow between the first semiconductor die and the second semiconductor die would be advantageous in that having less current flow would optimize the durability and reliability of the device while having more current flow would optimize the electrical functioning capability of the device (see MPEP 2143.I(D)).
Regarding Claim 11, the combination of Uozumi, Wakatsuki, and Makala et al discloses the limitations of claim 10 as explained above. The combination of Uozumi, Wakatsuki, and Makala et al further discloses
wherein the region of the second metal pad (988 Fig 9 viewed from 180 degrees Makala et al) on the second surface is entirely overlapped (shown in Fig 9 viewed from 180 degrees) by the region of the first metal pad (788 Fig 9 viewed from 180 degrees Makala et al) on the first surface, and
at least a part of the first carbon film (carbon [0041] Wakatsuki) on the first surface is not in contact (the examiner notes that although the top surface of the carbon filled recess would be in physical contact with the second metal pad, the remaining lower portion of the carbon filled recess would not be in physical contact with the second metal pad and would meet this claim limitation) with the second metal pad (988 Fig 9 viewed from 180 degrees Makala et al).
Regarding Claim 12, the combination of Uozumi, Wakatsuki, and Makala et al discloses the limitations of claim 10 as explained above. The combination of Uozumi, Wakatsuki, and Makala et al further discloses
wherein the region of the first metal pad (first bonding pads 988 [0044] Fig 9 Makala et al) on the first surface is entirely overlapped by the region of the second metal pad (second bonding pads 788 [0044] Fig 9 Makala et al) on the second surface, and
an entire part (the examiner notes that the top surface of the carbon filled recess would be in physical contact with the second metal pad and would meet this claim limitation) of the first carbon film (carbon [0041] Wakatsuki) on the first surface is in contact with the second metal pad (788 Fig 9 Makala et al).
Regarding Claim 13, the combination of Uozumi, Wakatsuki, and Makala et al discloses the limitations of claim 10 as explained above. The combination of Uozumi, Wakatsuki, and Makala et al further discloses
wherein the second metal pad (8 Fig 1 Uozumi/72 Fig 3 Wakatsuki) has a second recess [0041] formed in the second surface, and a second carbon film (carbon [0041]) is provided in the second recess [0041].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Uozumi (US 2021/0091024) in view of Wakatsuki (US 2021/0296253), and in further view of Uzoh et al (US 2021/0305202).
Regarding Claim 20, the combination of Uozumi and Wakatsuki discloses the limitations of claim 19 as explained above. The combination of Uozumi and Wakatsuki does not directly disclose
further comprising: after said performing the CMP, rinsing the first surface of the prepared first chip component, wherein a residual material after said rinsing is formed as the carbon or organic film.
Uzoh et al, in the related art of semiconductor devices that include bonding surfaces, discloses
further comprising: after said performing the CMP (dishing may occur from the polishing of a CMP process [0019]),
rinsing (rinsing the bonding surface [0044]) the first surface of the prepared first chip component (first chip bonder [0046] Fig 3), wherein a residual material after said rinsing is formed (activating the bonding surface [0044]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Uozumi and Wakatsuki to include wherein after said performing the CMP, rinsing the first surface of the prepared first chip component, wherein a residual material after said rinsing is formed as the carbon or organic film as taught by Uzoh et al in order to remove contaminating particles from the bonding surface [claim 3]. Further, a person of ordinary skill in the art would have recognized that removing particles disposed at the surface would help in preventing the enablement of undesirable current signal leakage [abstract] (see MPEP 2143.I(D)).
The combination of Uozumi, Wakatsuki, and Uzoh et al now discloses
wherein a residual material after said rinsing is formed as the carbon (carbon [0041] Wakatsuki) or organic film.
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mitsuhashi et al (US 2022/0028804) which discloses a semiconductor device with a power source pad and a connection pad [0107], and Wu et al (US 2021/0217716) which discloses a semiconductor device with bonding pads [0003].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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