Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Objections
Claims 2, 8, 17 are objected to because of the following informality: the phrase “configured to generate the accelerator command based on instruction set architecture (ISA)” should be changed to “…based on an instruction set architecture (ISA)…” for grammatical readability.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fryman et al., US Patent Application Publication 2019/0303159 (hereinafter Fryman) in view of Patsidis et al., “RISC-V2: A Scalable RISC-V Vector Processor” (hereinafter Patsidis).
Regarding claim 1, Fryman teaches:
A core directly coupled with one or more accelerators (see e.g. fig. 1, a core 108 directly coupled to accelerator engines 120 through wiring/buffers), the core comprising: an interface unit communicatively coupled and having circuitry configured to generate an accelerator command to an accelerator of the one or more accelerators based on output commands (see e.g. para. [0358], an issue circuit translates decoded instructions based on the decoded instructions and the specified accelerator core).
Fryman fails to explicitly teach the core as a reduced instruction set computer (RISC)-V vector extension (RVV) core comprising a command queue configured to output commands.
Patsidis teaches a RISC-V vector extension core comprising a command queue configured to output commands (see e.g. fig. 1, RISC-V vector extension core with command queue vIQ).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Fryman and Patsidis wherein the core is a reduced instruction set computer (RISC)-V vector extension (RVV) core comprising a command queue configured to output commands. This would have provided an advantage such as “significant latency improvements” for reduction operations such as discussed by Patsidis (see pg. 3, section C).
Regarding claim 2, Fryman in view of Patsidis teaches or suggests:
The RVV core according to claim 1, wherein the interface unit comprises: a command register configured to generate the accelerator command based on instruction set architecture (ISA) of a corresponding accelerator and the command queue; and an interface configured to communicate with the one or more accelerators (see e.g. Fryman para. [0134-6], [0358], the accelerator instruction/command is generated based on the ISA of the accelerator).
Regarding claim 3, Fryman in view of Patsidis teaches or suggests:
The RVV core according to claim 2, wherein the interface unit further comprises one or more channels, wherein a channel of the one or more channels is each configured to provide a communication channel with a corresponding accelerator (see e.g. Fryman para. [0366]).
Regarding claim 4, Fryman in view of Patsidis teaches or suggests:
The RVV core according to claim 1, further comprising an RVV register configured to be directly accessible to the one or more accelerators (see e.g. Fryman para. [0060]).
Regarding claim 5, Fryman in view of Patsidis teaches or suggests:
The RVV core according to claim 4, wherein the RVV register is configured to store data for the RVV core and data for the one or more accelerators (see e.g. Fryman para. [0060]).
Regarding claim 6, Fryman in view of Patsidis teaches or suggests:
The RVV core according to claim 1, wherein the interface unit is a queue-based first in first out unit (see e.g. Patsidis fig. 1).
Claims 7-11 are rejected for reasons corresponding to those given above for claims 1-6 (see also Patsidis fig. 1 scalar core).
Claims 12-20 are rejected for reasons corresponding to those given above for claims 1-6 (see also Patsidis fig. 1 scalar core; Fryman para. [0074], decoder for an accelerator).
Response to Arguments
Applicant's arguments filed 8/4/26 have been fully considered but they are not persuasive.
Applicant argues a lack of teaching of “A core directly coupled with one or more accelerators”.
Examiner respectfully disagrees. The core of Fryman is directly coupled and communicates with the engines through a direct local connection rather than indirectly through another processing core or through the intra-accelerator network. Applicant has not defined or claimed a more limiting requirement of “directly coupled” in order to differentiate from this teaching. Further, arguendo, even if a buffer/queue along the communication path created an indirect coupling, one of ordinary skill in the art would have certainly recognized that the buffer/queue could be contained within the “core” given the combination with Patsidis. Patsidis teaches a RISC-V vector extension core comprising a buffer/queue (see e.g. fig. 1, RISC-V vector extension core with command queue vIQ).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Fryman was not relied upon to teach the core comprising “a command queue configured to output commands”. As stated in the rejection, “Fryman fails to explicitly teach the core as a reduced instruction set computer (RISC)-V vector extension (RVV) core comprising a command queue configured to output commands” (emphasis added). The commands being translated in Fryman are previously output, but are simply not disclosed to be stored in a queue as they are being output/processed within the pipeline. Patsidis teaches such a queue within a processing pipeline in a core (see e.g. fig. 1 command queue vIQ).
Patsidis was not relied upon to teach a command queue having outputs that are used by an interface unit to generate commands to external accelerators. Patsidis was relied upon to teach a RISC-V vector extension core comprising a command queue configured to output commands (see e.g. fig. 1, RISC-V vector extension core with command queue vIQ).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, combining Fryman with Patsidis to incorporate aspects of an RVV core would have provided at least an advantage of the RVV core of “significant latency improvements” for reduction operations as discussed by Patsidis (see pg. 3, section C).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
Prosecution Insights