DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dean et al (US 7,068,192).
Regarding claim 1, Dean et al teach in figures (2-7) a computer-implemented method for decoding variable length integers (See column 1: lines 20-22), comprising: obtaining a series of bits encoding one or more variable length integers (input of figure 7); applying a mask (step 708, the mask including tag bits) to the series of bits to determine a number of bytes (i.e., storage length, see claims 1, 11) that correspond to each of the one or more variable length integers in the series of bits; and decoding (See decoder 210 of figure 2) each of the one or more variable length integers based on the number of bytes that correspond to each of the one or more variable length integers.
Regarding claim 9, Dean et al teach in figures (2-7) an apparatus for decoding variable length integers (See abstract), the apparatus comprising one or more processors (See claim 20) and one or more non-transitory memories with instructions thereon, wherein the instructions upon execution by the one or more processors, cause the one or more processors to: obtain a series of bits encoding one or more variable length integers (input of figure 7); apply a mask (step 708, the mask including tag bits) to the series of bits to determine a number of bytes (i.e., storage length, see claims 1, 11) that correspond to each of the one or more variable length integers in the series of bits; and decode (See decoder 210 of figure 2) each of the one or more variable length integers based on the number of bytes that correspond to each of the one or more variable length integers.
Regarding claim 17, Dean et al teach in figures (2-7) One or more non-transitory computer-readable storage media storing instructions that when executed by one or more processors cause the one or more processors to execute a method (See claim 20) for decoding variable length integers, wherein the method comprises: obtaining a series of bits encoding one or more variable length integers (input of figure 7); applying a mask (step 708, the mask including tag bits) to the series of bits to determine a number of bytes (i.e., storage length, see claims 1, 11) that correspond to each of the one or more variable length integers in the series of bits; and decoding (See decoder 210 of figure 2) each of the one or more variable length integers based on the number of bytes that correspond to each of the one or more variable length integers.
Allowable Subject Matter
Claims 2-8, 10-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH J LAUTURE whose telephone number is (571)272-1805. The examiner can normally be reached 9:30 AM-6:00 PM.
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/JOSEPH J LAUTURE/ Primary Examiner, Art Unit 2845