DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,989,144. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 21 of the instant application is anticipated by patent claim 1 in that claim 1 of the patent contains all the limitations of claim 1 of the instant application. Claim 1 of the instant application therefore is not patently distinct from the earlier patent claim and as such is unpatentable for anticipatable-type double patenting because claim 1 of the instant application is anticipated by patent claim 1. Please see comparison table as below. See In re Goodman (CA FC) 29 USPQ2d 2010(12/3/1993)
And the limitations of the remaining claims 22-40 are found, with minor variations in the recitation of Patent claims 2-20.
Patent (U.S. Patent No. 11,989,144)
Instant Application (18/667,752)
An apparatus comprising:
A first processor comprising:
a master interrupt controller, in a first semiconductor die of a plurality of semiconductor dies on a substrate, comprising circuitry configured to: receive, via a communication link, interrupts generated by at least: a first interrupt source in the first semiconductor die; and
a plurality of semiconductor dies within the first processor, wherein each of the plurality of semiconductor dies is configured to generate interrupts;
a second interrupt source in a second semiconductor die of the plurality of semiconductor dies;
in response to receiving a given interrupt, determine which of the first interrupt source and the second interrupt source generated the given interrupt; and
wherein a first semiconductor die of the plurality of semiconductor dies includes an interrupt handler comprising circuitry configured to: receive an interrupt to be serviced from a second semiconductor die of the plurality of semiconductor dies; and
convey the given interrupt, with an indication of which source generated the given interrupt, to a processor for handling by the processor.
forward the interrupt to a second processor different from the first processor for servicing the interrupt.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 21-32 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsien et al. (Pub. No. US2019/0196574)
As per claim 21, Tsien discloses a first processor (fig.1, cpu 112) comprising:
a plurality of semiconductor dies (fig.1, components on node 100 are individual dies), within the first processor (the processing node comprising CPU corresponding to the semiconductor die as show in figures 1 and 2) wherein each of the plurality of semiconductor dies is configured to generate interrupts (paragraph 34, line1 multiple interrupts asserted by cores on remote CPUs);
wherein a first semiconductor die (fig.2, master node 220A) processing of the plurality of semiconductor dies includes an interrupt handler (fig.1, interrupt controller 111) comprising circuitry configured to: receive an interrupt to be serviced from a second semiconductor die (fig.2, node 220B) of the plurality of semiconductor dies (fig.1, components on node 220B are individual dies); and
forward the interrupt to a second processor (fig.2, (fig.1, cpu 112b of node 220B) different from the first processor (fig.1, cpu 112) for servicing the interrupt. (paragraph 64, based on a reply from the master node, a second node is identified to service the arbitrated interrupt)
As per claim 22, Tsien discloses wherein the circuitry is configured to communicate to the second semiconductor die that the interrupt has been handled by the second processor without being serviced by the first processor, responsive to receipt of a completion response from the second processor. (paragraph 47, lines 9-10, responses are received, the command proceeds to completion.)
As per claims 23 and 30, Tsien discloses wherein the circuitry is configured to generate metadata comprising at least an identifier of the second semiconductor die to send to the second processor with the interrupt. (paragraph 51, interrupt controller 228 also stores fixed interrupt identifiers (IDs) for each of the processor cores in computing system 200.)
As per claim 24, Tsien discloses wherein the second semiconductor die is configured to convey the interrupt to the first semiconductor die while having an interrupt handler disabled for servicing interrupts (paragraph 17, lines 8-10, disabling clocks for the one or more clients and a communication fabric transferring traffic between the one or more clients.)
As per claim 26, Tsien discloses wherein one or more of the plurality of dies comprises a plurality of clients, each configured to generate interrupts that are received by the interrupt handler of the first semiconductor die. (paragraph 29, controller 170 detects when one or more of clients 110 become idle. If each of the clients 110 becomes idle, then in an embodiment, power controller 170 relays an indication to one or more nodes on one or more of its links via link interfaces 180 specifying a powered down state.)
As per claim 27, Tsien discloses wherein the circuitry is configured to generate metadata to send to the second processor with the interrupt, wherein the metadata comprises at least a first identifier of the second semiconductor die and a second identifier of a corresponding one of a plurality of clients that generated the interrupt. (paragraph 51, interrupt controller 228 also stores fixed interrupt identifiers (IDs) for each of the processor cores in computing system 200.)
As per claim 28, Tsien discloses a method, comprising:
receiving, by circuitry of a first semiconductor die (fig.2, master node 220A) of a plurality of semiconductor dies within a first processor, an interrupt to be serviced from a second semiconductor die (fig.2, node 220B) of the plurality of semiconductor dies, wherein each of the plurality of semiconductor dies is configured to generate interrupts (paragraph 33, based on a different interrupt mode or different interrupt type, an interrupt is sent from a processor detecting the interrupt to a processor in a particular node based on arbitration.); and
Forwarding, by the first semiconductor die (fig.2, master node 220A), the interrupt to a second processor (fig.1, cpu 112b) separate from the plurality of semiconductor dies for servicing the interrupt. (paragraph 64, based on a reply from the master node, a second node is identified to service the arbitrated interrupt)
As per claim 29, Tsien discloses wherein the circuitry is configured to communicate to the second semiconductor die, an indication that the interrupt has been service by a third processor (fig.2, cpu 112c within node 220c) and not by the second processor, responsive to receipt of a completion response from the third processor. (paragraph 47, lines 9-10, responses are received, the command proceeds to completion.)
As per claim 31, Tsien discloses wherein the second semiconductor die has an interrupt handler disabled for servicing interrupts and relies on the first semiconductor die for forwarding interrupts to the processor (paragraph 17, lines 8-10, disabling clocks for the one or more clients and a communication fabric transferring traffic between the one or more clients.)
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 25 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Tsien et al. (Pub. No. US2019/0196574) in view of Balakrishman et al. (Pub. No. US2014/0201406)
As per claims 25 and 32, Tsien discloses all the limitations as the above but does not explicitly disclose wherein two or more of the plurality of semiconductor dies are packaged together as a monolithic circuit forming a single processor package on a same substrate. However, Balakrishman discloses this. (paragraph 2, System-on-a-chip or system on chip (also named after the acronyms SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). An integrated circuit or monolithic integrated circuit (also referred to as IC, chip, and microchip))
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Balakrishman with the teaching of White so as to low latency used to enable such flexible partitioning of a SoC or a system into multiple physical dies while the software implemented in the system considers them as a single logical die to enhance the system performance.
7. Claims 33-40 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Tsien et al. (Pub. No. US2019/0196574) in view of Asaad et al. (Pub. No. US2011/0219208)
As per claim 35, Tsien discloses computing system comprising:
a first processor (fig.1, cpu 112); and
a second processor comprising a plurality of semiconductor dies (fig.1, components on node 100 are individual dies);
wherein a first semiconductor die (fig.2, master node 220A) of the plurality of semiconductor dies is configured to:
run a first guest operating system associated with a first mode of the plurality of modes (fig.2, processing node 102b) different from the first processor (fig.2, processing node 102a) for servicing the interrupt (paragraph 33, lines 5-6, Based on an interrupt mode or an interrupt type, an interrupt is sent from a processor detecting the interrupt to a particular processor); and
forward the interrupt to the first processor. (paragraph 64, based on a reply from the master node, a second node is identified to service the arbitrated interrupt)
Tsien discloses all the limitations as the above but does not explicitly disclose maintain a plurality of partitions based on a partition mode; run a first quest operating system associated with a first partition of the plurality of partitions; receive an interrupt from a second semiconductor die of the plurality of semiconductor dies associated with a second partition of the plurality of parttions different from the first partition. However, Asaad discloses this. (paragraph 16, lines 5-8, each computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources. Many processors on a single die enables adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Asaad with the teaching of Tsien so as to allows the use of different filesystems to be installed for different kinds of files so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 33, Asaad discloses the method further comprising:
maintaining, by the processor, the plurality of partitions, each associated with a corresponding guest operating system; and generating, by the first semiconductor die metadata to send to the processor with the interrupt, the metadata comprising a first identifier identifying the second semiconductor die and a second identifier identifying a partition of the plurality of partitions. (paragraph 16, lines 5-8, each computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources. Many processors on a single die enables adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases.)
As per claim 34, Asaad discloses wherein the first identifier is a logical identifier mapped to a physical identifier of the second semiconductor die, wherein each of an operating system of the processor and the guest operating system of the partition use the logical identifier to specify the second semiconductor die. (paragraph 16, lines 5-8, each computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources. Many processors on a single die enables adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases.)
As per claim 36, Tsien discloses wherein the circuitry is configured to communicate to the second semiconductor die that the interrupt has been handled, responsive to receipt of a completion response from the second processor. (paragraph 47, lines 9-10, responses are received, the command proceeds to completion.)
As per claim 37, Asaad discloses wherein the first semiconductor is configured to generate metadata to send to the processor with the interrupt, wherein the metadata comprises a first identifier identifying the second semiconductor die and a second identifier identifying the second partition. (paragraph 16, lines 5-8, each computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources. Many processors on a single die enables adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases.)
As per claim 38, Tsien discloses wherein the first identifier is a logical identifier mapped to a physical identifier of the second semiconductor die, wherein each of an operating system of the processor and the guest operating system of the second partition use the logical identifier to specify the second semiconductor die. (paragraph 51, interrupt controller stores fixed interrupt identifiers for each of the processors in computing system.)
As per claim 39, Asaad discloses wherein the second semiconductor die is associated with a physical identifier and a logical identifier, and wherein the physical identifier remains constant across changes to partitioning of the plurality of semiconductor dies while the logical identifier is updated in response to a change in partition assignment.(paragraph 16, lines 5-8, many processors on a single die enables adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases.)
As per claim 40, Tsien discloses wherein each of the plurality of semiconductor dies except the first semiconductor die has an interrupt handler that is not used to handle interrupts and relies on the first semiconductor die for forwarding interrupts to the processor. (paragraph 17, lines 8-10, disabling clocks for the one or more clients and a communication fabric transferring traffic between the one or more clients)
Response to Amendment
8. Applicant's amendment filed on 02/06/2026 have been fully considered but are moot in view of the new ground(s) of rejection.
9. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Meyer et al. [Pub. No. US2017/0315944] discloses an arbitrator or interrupt service provider operable via the on-chip bus systems 108 and 128 at respective dies with system address maps to control or manage requests for resources (e.g., memory 104, peripheral components 110, or the like)
White [Pub. No. US2014/0115198] discloses monitoring logic for measuring and storing latencies for servicing interrupt requests.
Conclusion
10. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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