DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because the empty boxes (e.g. 110, 120, 102, 103, 11, 101, 102 and 106) in figures 1, 7 and 8 should contain symbols or text indicating their functionality. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: the Specification should be revised carefully because it contains some typographical errors (Example: page 4; paragraph [0019]; recites “transformer T. the flyback converter 200”, which should be “transformer T. The flyback converter 200”).
Appropriate correction is required.
Claim Objections
Claim 6 is objected to because of the following informalities: Claim 6, line 4 recites “the primary control signal”, which should be --a primary control signal -- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim 14 is objected to because of the following informalities: Claim 6, second line recites “the flyback converter”, which should be --a flyback converter -- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim 19 is objected to because of the following informalities: Claim 19, second line recites “the flyback converter”, which should be --a flyback converter -- because this term was not previously presented in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-13, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0294355), hereinafter Lin, in view of Lenz et al. (US 7,884,583), hereinafter Lenz.
Regarding claim 1, Lin discloses (see figures 1-9) a flyback converter (figure 5, part 500), comprising: a primary power switch (figure 5, part S1), coupled to a primary winding of a transformer (figure 5, part Lp); a secondary power switch (figure 5, part S2), coupled to a secondary winding of the transformer (figure 5, part 564); and a driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820), configured to provide a drive signal (figures 5 and 8, part 548) to drive the primary power switch (figure 5, part S1); wherein: if a time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is longer (figure 6, part longer time interval between two adjacent turn-ons of S1 Vg after t1) (figure 8, part when the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold) (paragraphs [0053]-[0056]; if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode (e.g., the deep continuous conduction mode)… at rising edges of the drive signal 548 that is received by the gate terminal 582 of the transistor 570, the drive signal 548 increases more slowly in the continuous conduction mode (e.g., the deep continuous conduction mode) than in the discontinuous conduction mode as shown by the waveform 648), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide a weak drive (figures 6 and 8, part weak drive at 666; through 877), so that the primary power switch (figures 5 and 8, part S1[570]) is controlled to turn to a fully ON state from a fully OFF state with a first speed (figures 6 and 8, part fully ON state from a fully OFF state at slower speed at 666) (paragraphs [0065]-[0069]; if both the comparison signal 857 and the detection signal 863 are at the logic high level, the control signal 877 is the at the logic high level… if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode (e.g., the deep continuous conduction mode)… if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude. For example, if the control signal 877 changes from the logic low level to the logic high level, the current 817 decreases from the predetermined higher magnitude to the predetermined lower magnitude… if the current 817 generated by the current source 816 decreases, an output current 813 of the current mirror 810 also decreases. For example, if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases); and if the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is shorter (figure 6, part shorter time interval between two adjacent turn-ons of S1 Vg before t1) (paragraphs [0053]-[0056]), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide a strong drive (figures 6 and 8, part strong drive at 660; through 877), so that the primary power switch (figures 5 and 8, part S1[570]) is controlled to turn to the fully ON state from the fully OFF state with a second speed (figures 6 and 8, part fully ON state from a fully OFF state at faster speed at 660) (paragraphs [0065]-[0069]; if the comparison signal 857 and/or the detection signal 863 is at the logic low level, the control signal 877 is at the logic low level… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude).
Lin does not expressly disclose is longer than a reference time length; is shorter than the reference time length.
Lenz teaches (see figures 1-6) if a time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is longer than a reference time length (figures 3, part when the detected frequency at 25 is lower than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is longer than the reference time length); and if the time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is shorter than the reference time length (figures 3, part when the detected frequency at 25 is higher than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is shorter than the reference time length) (column 5; lines 7-39; the frequency measurement circuit 25 indicates that the input signal IN is switching at a frequency higher than a predetermined threshold).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller [specific the determination used to change the driver operation] of Lin with the control features as taught by Lenz and obtain a flyback converter, comprising: a primary power switch, coupled to a primary winding of a transformer; a secondary power switch, coupled to a secondary winding of the transformer; and a driver, configured to provide a drive signal to drive the primary power switch; wherein: if a time interval between two adjacent turn-ons of the primary power switch is longer than a reference time length, the driver is configured to provide a weak drive, so that the primary power switch is controlled to turn to a fully ON state from a fully OFF state with a first speed; and if the time interval between two adjacent turn-ons of the primary power switch is shorter than the reference time length, the driver is configured to provide a strong drive, so that the primary power switch is controlled to turn to the fully ON state from the fully OFF state with a second speed, because it efficiently providing gating signals to the drivers in order to obtain more efficient operation of the converter (Abstract).
Regarding claim 2, Lin and Lenz teach everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) the driver (figure 5, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide the weak drive (figures 6 and 8, part weak drive at 666 after t1; through 877) to the primary power switch (figures 5 and 8, part S1[570]) at a start-up stage (paragraph [0073]; the feedback signal 542 is larger than the predetermined feedback threshold 855 (e.g., Vfb_th) and the detected pulse width of the drive signal 548 is smaller than the predetermined time threshold (e.g., Ton_th) when the switching power supply 500 is in the start-up process).
Regarding claim 3, Lin and Lenz teach everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) the first speed (figures 6 and 8, part fully ON state from a fully OFF state at slower speed at 666) (paragraphs [0065]-[0069]; if both the comparison signal 857 and the detection signal 863 are at the logic high level, the control signal 877 is the at the logic high level… if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode (e.g., the deep continuous conduction mode)… if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude. For example, if the control signal 877 changes from the logic low level to the logic high level, the current 817 decreases from the predetermined higher magnitude to the predetermined lower magnitude… if the current 817 generated by the current source 816 decreases, an output current 813 of the current mirror 810 also decreases. For example, if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases) is lower than the second speed (figures 6 and 8, part fully ON state from a fully OFF state at faster speed at 660) (paragraphs [0065]-[0069]; if the comparison signal 857 and/or the detection signal 863 is at the logic low level, the control signal 877 is at the logic low level… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude).
Regarding claim 5, Lin and Lenz teach everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) a control circuit (figures 5 and 8, part 510), and the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1). However, Lin does not expressly disclose a timer configured to time the time interval between two adjacent turn-ons of the primary power switch.
Lenz teaches (see figures 1-6) a timer (figure 3, part timer inside frequency measurement 25) (figure 6, part timer generated by 31/33) configured to time the time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) (column 5; lines 7-39; the frequency measurement circuit 25 indicates that the input signal IN is switching at a frequency higher than a predetermined threshold).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller [specific the determination used to change the driver operation] of Lin with the control features as taught by Lenz and obtain a control circuit, having a timer configured to time the time interval between two adjacent turn-ons of the primary power switch, because it efficiently providing gating signals to the drivers in order to obtain more efficient operation of the converter (Abstract).
Regarding claim 6, Lin and Lenz teach everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) comprises: a first current source (figure 8, part first current source generated by 816 [at a predetermined lower magnitude], 810, 824, 842, 844, 830 and 822; when the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold), configured to provide a first drive current (figure 8, part first drive current at 822; when 816 [at a predetermined lower magnitude]); and a second current source (figure 8, part second current source generated by 816 [a predetermined higher magnitude], 810, 824, 842, 844, 830 and 822; when the control signal 877 is at the logic low level), configured to provide a second drive current (figure 8, part second drive current at 822; when 816 [a predetermined higher magnitude]); wherein when the primary control signal (figure 8, part primary control signal generated by 877 and output of 840) indicates that the primary power switch is turned on (figures 5 and 8, part S1[570]; turn-on): if the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is longer (figure 6, part longer time interval between two adjacent turn-ons of S1 Vg after t1) (figure 8, part when the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to drive the primary power switch (figures 5 and 8, part S1[570]) with the first drive current (figure 8, part first drive current at 822; when 816 [at a predetermined lower magnitude]) (paragraphs [0053]-[0056]; if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode (e.g., the deep continuous conduction mode)… at rising edges of the drive signal 548 that is received by the gate terminal 582 of the transistor 570, the drive signal 548 increases more slowly in the continuous conduction mode (e.g., the deep continuous conduction mode) than in the discontinuous conduction mode as shown by the waveform 648); and if the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is shorter (figure 6, part shorter time interval between two adjacent turn-ons of S1 Vg before t1), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to drive the primary power switch (figures 5 and 8, part S1[570]) with the second drive current (figure 8, part second drive current at 822; when 816 [a predetermined higher magnitude]) (paragraphs [0053]-[0056]); and wherein the second drive current (figure 8, part second drive current at 822; when 816 [a predetermined higher magnitude]) is higher than the first drive current (figure 8, part first drive current at 822; when 816 [at a predetermined lower magnitude]). However, Lin does not expressly disclose is longer than a reference time length; is shorter than the reference time length.
Lenz teaches (see figures 1-6) if the time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is longer than a reference time length (figures 3, part when the detected frequency at 25 is lower than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is longer than the reference time length); and if the time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is shorter than the reference time length (figures 3, part when the detected frequency at 25 is higher than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is shorter than the reference time length) (column 5; lines 7-39; the frequency measurement circuit 25 indicates that the input signal IN is switching at a frequency higher than a predetermined threshold).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller [specific the determination used to change the driver operation] of Lin with the control features as taught by Lenz and obtain the driver comprises: a first current source, configured to provide a first drive current; and a second current source, configured to provide a second drive current; wherein when the primary control signal indicates that the primary power switch is turned on: if the time interval between two adjacent turn-ons of the primary power switch is longer than the reference time length, the driver is configured to drive the primary power switch with the first drive current; and if the time interval between two adjacent turn-ons of the primary power switch is shorter than the reference time length, the driver is configured to drive the primary power switch with the second drive current; and wherein the second drive current is higher than the first drive current, because it efficiently providing gating signals to the drivers in order to obtain more efficient operation of the converter (Abstract).
Regarding claim 7, Lin and Lenz teach everything claimed as applied above (see claim 6). Further, Lin discloses (see figures 1-9) the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) further comprises: a third current source (figure 8, part third current source generated by 820), configured to provide a discharge current (figure 8, part discharge current through 820); wherein when the primary control signal (figure 8, part primary control signal generated by 877 and output of 840) indicates that the primary power switch is turned off (figures 5 and 8, part S1[570]; turn-off), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to drive the primary power switch (figures 5 and 8, part S1[570]) with the discharge current (figure 8, part discharge current through 820).
Regarding claim 8, Lin discloses (see figures 1-9) a control and drive circuit (figure PWM Controller), comprising: a primary controller (figure 5, part 510), configured to generate a primary control signal (figure 5, part 548) used to control a primary power switch (figure 5, part S1); and a time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1), wherein: if the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is longer (figure 6, part longer time interval between two adjacent turn-ons of S1 Vg after t1) (figure 8, part when the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold) (paragraphs [0053]-[0056]; if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode (e.g., the deep continuous conduction mode)… at rising edges of the drive signal 548 that is received by the gate terminal 582 of the transistor 570, the drive signal 548 increases more slowly in the continuous conduction mode (e.g., the deep continuous conduction mode) than in the discontinuous conduction mode as shown by the waveform 648), the primary controller (figure 5, part 510) is configured to control the primary power switch (figure 5, part S1) to turn to a fully ON state from a fully OFF state with a first speed (figures 6 and 8, part fully ON state from a fully OFF state at slower speed at 666) (paragraphs [0065]-[0069]; if both the comparison signal 857 and the detection signal 863 are at the logic high level, the control signal 877 is the at the logic high level… if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode (e.g., the deep continuous conduction mode)… if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude. For example, if the control signal 877 changes from the logic low level to the logic high level, the current 817 decreases from the predetermined higher magnitude to the predetermined lower magnitude… if the current 817 generated by the current source 816 decreases, an output current 813 of the current mirror 810 also decreases. For example, if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases); and if the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is shorter (figure 6, part shorter time interval between two adjacent turn-ons of S1 Vg before t1) (paragraphs [0053]-[0056]), the primary controller (figure 5, part 510) is configured to control the primary power switch (figure 5, part S1) to turn to the fully ON state from the fully OFF state with a second speed (figures 6 and 8, part fully ON state from a fully OFF state at faster speed at 660) (paragraphs [0065]-[0069]; if the comparison signal 857 and/or the detection signal 863 is at the logic low level, the control signal 877 is at the logic low level… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude).
Lin does not expressly disclose a timer, configured to time a time interval between two adjacent turn-ons of the primary power switch; is longer than a reference time length; is shorter than the reference time length.
Lenz teaches (see figures 1-6) a timer (figure 3, part timer inside frequency measurement 25) (figure 6, part timer generated by 31/33), configured to time a time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH); and if a time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is longer than a reference time length (figures 3, part when the detected frequency at 25 is lower than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is longer than the reference time length); and if the time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is shorter than the reference time length (figures 3, part when the detected frequency at 25 is higher than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is shorter than the reference time length) (column 5; lines 7-39; the frequency measurement circuit 25 indicates that the input signal IN is switching at a frequency higher than a predetermined threshold).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller [specific the determination used to change the driver operation] of Lin with the control features as taught by Lenz and obtain a control and drive circuit, comprising: a primary controller, configured to generate a primary control signal used to control a primary power switch; and a timer, configured to time a time interval between two adjacent turn-ons of the primary power switch, wherein: if the time interval between two adjacent turn-ons of the primary power switch is longer than a reference time length, the primary controller is configured to control the primary power switch to turn to a fully ON state from a fully OFF state with a first speed; and if the time interval between two adjacent turn-ons of the primary power switch is shorter than the reference time length, the primary controller is configured to control the primary power switch to turn to the fully ON state from the fully OFF state with a second speed. , because it efficiently providing gating signals to the drivers in order to obtain more efficient operation of the converter (Abstract).
Regarding claim 9, claim 1 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 10, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 11, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 12, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 13, claim 3 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, Lin discloses (see figures 1-9) a control and drive circuit (figure PWM Controller), comprising: a primary controller (figure 5, part 510), configured to generate a primary control signal (figure 5, part 548) used to control a primary power switch (figure 5, part S1); and a driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820), configured to provide a drive signal (figures 5 and 8, part 548) to drive the primary power switch (figure 5, part S1); wherein: if a time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is longer (figure 6, part longer time interval between two adjacent turn-ons of S1 Vg after t1) (figure 8, part when the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold) (paragraphs [0053]-[0056]; if the feedback signal 542 becomes larger than the predetermined feedback threshold 640 (e.g., Vfb_th) and the previous pulse width (e.g., a pulse width 670) of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 becomes smaller than a width threshold, the switching power supply 500 changes from operating in the discontinuous conduction mode to operating in the continuous conduction mode (e.g., the deep continuous conduction mode)… at rising edges of the drive signal 548 that is received by the gate terminal 582 of the transistor 570, the drive signal 548 increases more slowly in the continuous conduction mode (e.g., the deep continuous conduction mode) than in the discontinuous conduction mode as shown by the waveform 648), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide a weak drive (figures 6 and 8, part weak drive at 666; through 877), to have the primary power switch (figures 5 and 8, part S1[570]) turn to a fully ON state from a fully OFF state with a first speed (figures 6 and 8, part fully ON state from a fully OFF state at slower speed at 666) (paragraphs [0065]-[0069]; if both the comparison signal 857 and the detection signal 863 are at the logic high level, the control signal 877 is the at the logic high level… if the control signal 877 changes from the logic low level to the logic high level, the switching power supply 500 changes from the discontinuous conduction mode to the continuous conduction mode (e.g., the deep continuous conduction mode)… if the control signal 877 is at the logic high level, the current source 816 generates the current 817 at a predetermined lower magnitude. For example, if the control signal 877 changes from the logic low level to the logic high level, the current 817 decreases from the predetermined higher magnitude to the predetermined lower magnitude… if the current 817 generated by the current source 816 decreases, an output current 813 of the current mirror 810 also decreases. For example, if the output current 813 of the current mirror 810 decreases, a current 845 that charges the capacitor 844 also decreases. As an example, if the current 845 that charges the capacitor 844 decreases, the rate of increase of a drive signal 823 that is received by a gate terminal of the transistor 822 also decreases. For example, if the rate of increase of the drive signal 823 decreases, the rate of increase of a source voltage 825 at a source terminal of the transistor 822 also decreases. As an example, if the rate of increase of the source voltage 825 decreases, the rate of increase of the drive signal 548 that is received by the gate terminal 582 of the transistor 570 also decreases); and if the time interval between two adjacent turn-ons (figure 6, part a time interval between two adjacent turn-ons of S1 Vg) of the primary power switch (figure 5, part S1) is shorter (figure 6, part shorter time interval between two adjacent turn-ons of S1 Vg before t1) (paragraphs [0053]-[0056]), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide a strong drive (figures 6 and 8, part strong drive at 660; through 877), to have the primary power switch (figures 5 and 8, part S1[570]) turn to the fully ON state from the fully OFF state with a second speed (figures 6 and 8, part fully ON state from a fully OFF state at faster speed at 660) (paragraphs [0065]-[0069]; if the comparison signal 857 and/or the detection signal 863 is at the logic low level, the control signal 877 is at the logic low level… if the control signal 877 is at the logic low level, the current source 816 generates the current 817 at a predetermined higher magnitude).
Lin does not expressly disclose is longer than a reference time length; is shorter than the reference time length.
Lenz teaches (see figures 1-6) if a time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is longer than a reference time length (figures 3, part when the detected frequency at 25 is lower than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is longer than the reference time length); and if the time interval between two adjacent turn-ons (figures 3, part a time interval between two adjacent turn-ons determines by the frequency measurement 25; period of time is reciprocal of frequency [T = 1/f]) of the primary power switch (figures 3, part DMOS HIGH) is shorter than the reference time length (figures 3, part when the detected frequency at 25 is higher than the predetermined threshold; based on reciprocal function [T = 1/f] is equivalent when time interval is shorter than the reference time length) (column 5; lines 7-39; the frequency measurement circuit 25 indicates that the input signal IN is switching at a frequency higher than a predetermined threshold).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller [specific the determination used to change the driver operation] of Lin with the control features as taught by Lenz and obtain a control and drive circuit, comprising: a primary controller, configured to generate a primary control signal used to control a primary power switch; and a driver, configured to provide a drive signal to drive the primary power switch; wherein: if a time interval between two adjacent turn-ons of the primary power switch is longer than a reference time length, the driver is configured to provide a weak drive, to have the primary power switch turn to a fully ON state from a fully OFF state with a first speed; and if the time interval between two adjacent turn-ons of the primary power switch is shorter than the reference time length, the driver is configured to provide a strong drive, to have the primary power switch turn to the fully ON state from the fully OFF state with a second speed, because it efficiently providing gating signals to the drivers in order to obtain more efficient operation of the converter (Abstract).
Regarding claim 16, claim 5 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 17, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 18, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, claim 3 has the same limitations, based on this is rejected for the same reasons.
Claims 4, 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0294355), hereinafter Lin, in view of Lenz et al. (US 7,884,583), hereinafter Lenz, and further in view of Shi et al. (US 8,274,801), hereinafter Shi.
Regarding claim 4, Lin and Lenz teach everything claimed as applied above (see claim 1). Further, Lin discloses (see figures 1-9) when the flyback converter (figure 5, part 500) enters a burst mode (figure 6, part burst mode before t1) and then exit from the burst mode (figure 6, part exit of burst mode at t1), the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide the weak drive (figures 6 and 8, part weak drive at 666; through 877) to the primary power switch (figures 5 and 8, part S1[570]); and when the flyback converter (figure 5, part 500) is not under the burst mode (figure 6, part after t1); and the driver (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) is configured to provide the strong drive (figures 6 and 8, part strong drive at 660; through 877) to the primary power switch (figure 8, part driver generated by 816, 810, 824, 842, 844, 830, 832, 822 and 820) (paragraphs [0065]-[0069]). However, Lin does not expressly disclose when the flyback converter is not under the burst mode, the driver is configured to provide the strong drive to the primary power switch.
Shi teaches (see figures 1-7) when the flyback converter (figure 1, part flyback converter) is not under the burst mode (figure 2, part not under the burst mode at Normal control mode), the driver (figure 3, part driver generated by 309) is configured to provide the strong drive (figure 5A, part strong drive of Vn at normal load condition) to the primary power switch (figure 3, part S1) (columns 4 and 5; lines 64-67 and 1-57; FIG. 5A shows voltage waveforms of a power supply under a normal load condition).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Lin with the control features as taught by Shi and obtain when the flyback converter enters a burst mode and then exit from the burst mode, the driver is configured to provide the weak drive to the primary power switch; and when the flyback converter is not under the burst mode, the driver is configured to provide the strong drive to the primary power switch, because it provides more efficient switching control based on the load condition.
Regarding claim 14, claim 4 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 19, claim 4 has the same limitations, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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