Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This Office Action is responsive to the communication filed 3/16/2026.
Claim Status
2. Claims 1-2, 4-9, 11-12, 16-17, and 19-20 have currently been amended.
Response to Arguments
3. The applicant’s arguments have been taken into consideration, but are moot in view of new grounds of rejection.
In light of the applicant’s claim amendments, see newly cited prior art reference Marinissen et al (US 2010/0264932), which discloses (in par [0054-0054] of Marinissen et al) comparing bits from the first and second shift registers during the same clock period (e.g., wherein a first value provided by the first LFSR is compared to a second value provided by the second LFSR during each clock cycle to detect a mismatch) and deviating from normal operation upon determining that the bits from the first and second shift register don’t match (e.g., responsive to detecting the mismatch, an error is reported and threat mitigation initiated).
Claim Objections
4. Claim 1 is objected to because of the following informalities:
Line 2 of claim 1 should be amended to --a first Linear Feedback Shift Register[[--. Appropriate correction is required.
Allowable Subject Matter
5. Claims 11-20 are allowable.
Claim Rejections – 35 USC 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 7-8, and 10 are rejected under 35 USC 103 as being unpatentable over Arora et al (US 8,689,357) in view of Marinissen et al (US 2010/0264932).
Regarding claim 1, Arora et al teaches a system comprising:
a first Linear Feedback Shift Register (LFSR) and a second LFSR having an equal size comprising a number of bits (Abstract, lines 1-5 & col. 5, lines 45-46, which disclose a set of 16-bit LFSRs corresponding to a tamper detection circuit),
the first LFSR and the second LFSR initialized at one or more power up (col. 3, lines 40-45, “The tamper detector also has a set of LFSRs”) or reset to an initial condition.
Arora et al does not explicitly teach wherein a first value provided by the first LFSR is compared to a second value provided by the second LFSR during each clock cycle to detect a mismatch, responsive to detecting the mismatch, an error is reported and threat mitigation initiated.
However, Marinissen et al teaches wherein a first value provided by the first LFSR is compared to a second value provided by the second LFSR during each clock cycle to detect a mismatch (par [0053-0054], which disclose comparing bits from the first and second shift registers during the same clock period),
responsive to detecting the mismatch, an error is reported and threat mitigation initiated (par [0053], lines 9-12, which discloses deviating from normal operation upon determining that the bits from the first and second shift register don’t match).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Marinissen et al within the disclosure of Arora et al in order to provide the predictive result of improving detection of tampering in an environment including a plurality of shift register circuits during a plurality of clock cycles (as disclosed in the Abstract of Marinissen et al) because altering normal shift operations, upon determining anomalous shift register bits, further prevents any malicious actors from tampering with shift register circuits when the malicious party attempts to perform an attack using altered shift register bits.
Regarding claim 7, Arora et al and Marinissen et al teach the limitations of claim 1.
Arora et al further teaches a lookup table that stores information indicative of anchor values (fig. 5-6 & col. 4, lines 20-30) and the number of bits (fig. 5-6 & col. 4, lines 20-30).
Regarding claim 8, Arora et al and Marinissen et al teach the limitations of claim 1.
Arora et al further teaches wherein the anchor values are coordinated to occur at defined clock counts (col. 2, lines 45-50, “clock cycles”).
Regarding claim 10, Arora et al and Marinissen et al teach the limitations of claim 1
Arora et al further teaches wherein the defined value is a LogicOneBit (col. 6, lines 56-57, “logic level one”) or a LogicZeroBit (col. 6, lines 56-57, “logic level zero”).
8. Claims 2-3, 6, and 9 are rejected under 35 USC 103 as being unpatentable over Arora et al (US 8,689,357) in view of Marinissen et al (US 2010/0264932), further in view of Montoya et al (US 2020/0021427).
Regarding claim 2, Arora et al and Marinissen et al do not explicitly teach wherein the first LFSR and the second LFSR emit respective measure and reference indicators that change continually according to a LFSR polynomial.
However, Montoya et al teaches wherein the first LFSR and the second LFSR emit respective measure and reference indicators that change continually according to a LFSR polynomial (fig. 2 & par [0014], “LFSR register where m≤N is the number of feedback measurements corresponding to the non-zero coefficients of an N-degree primitive polynomial”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Montoya et al within the teachings of Arora et al and Marinissen et al in order to provide the predictive result of improving prevention of tampering and circuit attack prevention by using algorithms to determine differences in successive bits (as disclosed in par [0007] of Montoya et al) because using the differences in bits between a value provided by a shift register with another input value discloses potential tampering based upon detecting differences between both values.
Regarding claim 3, Arora et al and Marinissen et al do not explicitly teach wherein the respective measure and reference indicators are emitted as a series of pseudo-random values separated by a large Hamming distance between consecutive values.
However, Montoya et al teaches wherein the respective measure and reference indicators are emitted as a series of pseudo-random values separated by a large Hamming distance between consecutive values (par [0014], lines 1-5, “Hamming distance”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Montoya et al within the teachings of Arora et al and Marinissen et al according to the motivation disclosed regarding claim 2.
Regarding claim 6, Arora et al and Marinissen et al do not explicitly teach a binary counter comprising the number of bits.
However, Montoya et al teaches a binary counter comprising the number of bits (par [0023], par [0041], and par [0062], lines 5-9, “binary counter”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Montoya et al within the teachings of Arora et al and Marinissen et al according to the motivation disclosed regarding claim 2.
Regarding claim 9, Arora et al does not explicitly teach wherein the first LFSR and the second LSFR comprise respective groups of register bits, and wherein register bits of the respective groups of register bits is assigned to a defined value according to a selected pattern.
However, Montoya et al teaches wherein the first LFSR and the second LSFR comprise respective groups of register bits (par [0038], lines 8-10, “bits at the output of the basic shift registers”), and wherein register bits of the respective groups of register bits is assigned to a defined value according to a selected pattern (fig. 2 & par [0047], “K bits being supplied to the K respective inputs of the basic shift registers”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Montoya et al within the disclosure of Arora et al in order to provide the predictive result of improving prevention of tampering and circuit attack prevention by using algorithms to determine differences in successive bits (as disclosed in par [0007] of Montoya et al) because using the differences in bits between a value provided by a shift register with another input value discloses potential tampering based upon detecting differences between both values.
8. Claims 4-5 are rejected under 35 USC 103 as being unpatentable over Arora et al (US 8,689,357) in view of Marinissen et al (US 2010/0264932), further in view of Cooke (US 2016/0154746).
Regarding claim 4, Arora et al and Marinissen et al do not explicitly teach wherein the first LFSR is a tracking LFSR, and wherein the second LFSR is a reference LFSR.
However, Cooke teaches wherein the first LFSR is a tracking LFSR (par [0030], “Galois LFSR”), and wherein the second LFSR is a reference LFSR (par [0063], lines 15-20, “N flip-flop LFSR”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Cooke within the teachings of Arora et al and Marinissen et al in order to provide the predictive result of improving shift register-related tamper prevention by implementing encrypted masking of register bits (as disclosed in par [0074], lines 1-3 of Cooke) because scrambling of the LFSR register-bits further prevents unauthorized altering of the LFSR.
Regarding claim 5, Arora et al and Marinissen et al do not explicitly teach wherein the number of bits is 20 bits.
However, Cooke teaches wherein the number of bits is 20 bits (par [0094], lines 1-2, “20-bit offset”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Cooke within the teachings of Arora et al and Marinissen et al according to the motivation disclosed regarding clam 4.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Randy A. Scott whose telephone number is (571) 272-3797. The examiner can normally be reached on Monday-Thursday 7:30 am-5:00 pm, second Fridays 7:30 am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Luu Pham can be reached on (571) 270-5002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RANDY A SCOTT/Primary Examiner, Art Unit 2439
20260407