Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1 – 20 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1 – 20 of prior U.S. Patent No. 10,608,662. This is a statutory double patenting rejection.
US Application Number 18/668,069
US Patent Number 10,608,662
1. A hybrid digital-to-analog converter (DAC) driver circuit, the circuit comprising: a current-mode DAC driver configured to receive a first set of bits of a digital input signal and to generate a first analog signal; a voltage-mode DAC driver configured to receive a second set of bits of the digital input signal and to generate a second analog signal; and a combination circuit configured to combine the first analog signal and the second analog signal and to generate an analog output signal, wherein: resistor values of the voltage-mode DAC driver are adjustable to provide termination of the DAC driver circuit, the current-mode DAC driver and the voltage-mode DAC driver comprise differential drivers, and the current-mode DAC driver and the voltage-mode DAC driver are configured to operate with a single clock signal.
1. A hybrid digital-to-analog converter (DAC) driver circuit, the circuit comprising: a current-mode DAC driver configured to receive a first set of bits of a digital input signal and to generate a first analog signal; a voltage-mode DAC driver configured to receive a second set of bits of the digital input signal and to generate a second analog signal; and a combination circuit configured to combine the first analog signal and the second analog signal and to generate an analog output signal, wherein: resistor values of the voltage-mode DAC driver are adjustable to provide termination of the DAC driver circuit, the current-mode DAC driver and the voltage-mode DAC driver comprise differential drivers, and the current-mode DAC driver and the voltage-mode DAC driver are configured to operate with a single clock signal.
2. The circuit of claim 1, wherein the current- mode DAC driver and the voltage- mode DAC driver are configured to operate using one of binary coded or thermometer coded digital signals, and wherein the first set of bits comprises least significant bits (LSBs) of the digital input signal and the second set of bits comprises most significant bits (MSBs) of the digital input signal.
2. The circuit of claim 1, wherein the current-mode DAC driver and the voltage-mode DAC driver are configured to operate using one of binary coded or thermometer coded digital signals, and wherein the first set of bits comprises least significant bits (LSBs) of the digital input signal and the second set of bits comprises most significant bits (MSBs) of the digital input signal.
3. The circuit of claim 1, wherein the current-mode DAC driver is implemented using PMOS transistors and the voltage-mode DAC driver is implemented using series self-terminated (SST) configurations.
3. The circuit of claim 1, wherein the current-mode DAC driver is implemented using PMOS transistors and the voltage-mode DAC driver is implemented using series self-terminated (SST) configurations.
4. The circuit of claim 1, wherein the voltage-mode DAC driver is implemented using a small chip area of less than approximately 20x50 pm2.
4. The circuit of claim 1, wherein the voltage-mode DAC driver is implemented using a small chip area of less than approximately 20×50 μm.sup.2.
5. The circuit of claim 1, wherein the current- mode DAC driver comprises a straight current-steering DAC driver implemented in current-mode logic (CML), and wherein the straight current-steering DAC driver comprises a tail current array formed of a plurality of current sources with different current values.
5. The circuit of claim 1, wherein the current-mode DAC driver comprises a straight current-steering DAC driver implemented in current-mode logic (CML), and wherein the straight current-steering DAC driver comprises a tail current array formed of a plurality of current sources with different current values.
6. The circuit of claim 5, wherein the straight current-steering DAC driver further comprises an array of differential data switches, wherein each differential data switch of the array of differential data switches is coupled to a respective current source of the current sources and is configured to receive a differential bit pair of the first set of bits of the digital input signal.
6. The circuit of claim 5, wherein the straight current-steering DAC driver further comprises an array of differential data switches, wherein each differential data switch of the array of differential data switches is coupled to a respective current source of the current sources and is configured to receive a differential bit pair of the first set of bits of the digital input signal.
7. The circuit of claim 6, wherein the straight current-steering DAC driver further comprises an array of cascode pairs, wherein each cascode pair of the array of cascode pairs is coupled to a respective differential data switch of the array of differential data switches, and wherein drain nodes of the cascode pairs of the array of cascode pairs are coupled to one another to create a differential output node of the straight current-steering DAC driver, and wherein the differential output node of the straight current- steering DAC driver is coupled to a differential output node of the voltage-mode DAC driver.
7. The circuit of claim 6, wherein the straight current-steering DAC driver further comprises an array of cascode pairs, wherein each cascode pair of the array of cascode pairs is coupled to a respective differential data switch of the array of differential data switches, and wherein drain nodes of the cascode pairs of the array of cascode pairs are coupled to one another to create a differential output node of the straight current-steering DAC driver, and wherein the differential output node of the straight current-steering DAC driver is coupled to a differential output node of the voltage-mode DAC driver.
8. The circuit of claim 1, wherein the current-mode DAC driver comprises a folded current- steering DAC driver comprising a folded array of differential data switches, wherein the folded array of differential data switches is coupled in parallel with an array of cascode transistor pairs to a pair of current sources, wherein drain nodes of the array of cascode transistor pairs are coupled to one another to create a differential output node of the folded current-steering DAC driver, and wherein digital input signals of the folded current- steering DAC driver are within a range of about 0-0.9 V.
8. The circuit of claim 1, wherein the current-mode DAC driver comprises a folded current-steering DAC driver comprising a folded array of differential data switches, wherein the folded array of differential data switches is coupled in parallel with an array of cascode transistor pairs to a pair of current sources, wherein drain nodes of the array of cascode transistor pairs are coupled to one another to create a differential output node of the folded current-steering DAC driver, and wherein digital input signals of the folded current-steering DAC driver are within a range of about 0-0.9 V.
9. The circuit of claim 8, wherein the DAC driver circuit comprises an interleaved folded DAC driver comprising a first and a second folded current-steering DAC drivers, wherein the first folded current-steering DAC driver comprises a first folded array of differential data switches, a first set of dump switches, and a first set of output switches, wherein the second folded current-steering DAC driver comprises a second folded array of differential data switches, a second set of dump switches, and a second set of output switches, wherein differential output nodes of the first set of output switches and the second set of output switches are coupled to differential output nodes of the voltage-mode DAC driver.
9. The circuit of claim 8, wherein the DAC driver circuit comprises an interleaved folded DAC driver comprising a first and a second folded current-steering DAC drivers, wherein the first folded current-steering DAC driver comprises a first folded array of differential data switches, a first set of dump switches, and a first set of output switches, wherein the second folded current-steering DAC driver comprises a second folded array of differential data switches, a second set of dump switches, and a second set of output switches, wherein differential output nodes of the first set of output switches and the second set of output switches are coupled to differential output nodes of the voltage-mode DAC driver.
10. The circuit of claim 9, wherein the voltage-mode DAC driver includes a pair of input multiplexers, each multiplexer of the pair of input multiplexers is configured to couple a first or a second digital input signal to respective input nodes of the voltage-mode DAC driver.
10. The circuit of claim 9, wherein the voltage-mode DAC driver includes a pair of input multiplexers, each multiplexer of the pair of input multiplexers is configured to couple a first or a second digital input signal to respective input nodes of the voltage-mode DAC driver.
11. The circuit of claim 1, wherein the combination circuit comprises an input impedance of an external circuit receiving the analog output signal, wherein the input impedance comprises a differential impedance including 50 S2 resistors.
11. The circuit of claim 1, wherein the combination circuit comprises an input impedance of an external circuit receiving the analog output signal, wherein the input impedance comprises a differential impedance including 50 Ω resistors.
12. A method for providing a hybrid digital-to-analog converter (DAC) driver circuit, the method comprising: providing a current- mode DAC driver to receive a first set of bits of a digital input signal and to generate a first analog signal; providing a voltage-mode DAC driver to receive a second set of bits of the digital input signal and to generate a second analog signal; coupling output nodes of the current-mode DAC driver and the voltage-mode DAC driver to a combination circuit; configuring the combination circuit to combine the first analog signal and the second analog signal and to generate an analog output signal; adjusting resistor values of the voltage-mode DAC driver to provide termination of the DAC driver circuit; and configuring the current-mode DAC driver and the voltage-mode DAC driver to operate with a single clock signal, wherein the current-mode DAC driver and the voltage-mode DAC driver comprise differential drivers.
12. A method for providing a hybrid digital-to-analog converter (DAC) driver circuit, the method comprising: providing a current-mode DAC driver to receive a first set of bits of a digital input signal and to generate a first analog signal; providing a voltage-mode DAC driver to receive a second set of bits of the digital input signal and to generate a second analog signal; coupling output nodes of the current-mode DAC driver and the voltage-mode DAC driver to a combination circuit; configuring the combination circuit to combine the first analog signal and the second analog signal and to generate an analog output signal; adjusting resistor values of the voltage-mode DAC driver to provide termination of the DAC driver circuit; and configuring the current-mode DAC driver and the voltage-mode DAC driver to operate with a single clock signal, wherein the current-mode DAC driver and the voltage-mode DAC driver comprise differential drivers.
13. The method of claim 12, further comprising implementing the current- mode DAC driver using PMOS transistors and the voltage-mode DAC driver using series self-terminated (SST) configurations, and wherein the voltage-mode DAC driver is implemented using a small chip area of less than approximately 20x50 pm2.
13. The method of claim 12, further comprising implementing the current-mode DAC driver using PMOS transistors and the voltage-mode DAC driver using series self-terminated (SST) configurations, and wherein the voltage-mode DAC driver is implemented using a small chip area of less than approximately 20×50 μm.sup.2.
14. The method of claim 12, wherein providing the current-mode DAC driver comprises providing a straight current-steering DAC driver implemented in current-mode logic (CML), and wherein providing the straight current-steering DAC driver comprises providing a tail current array formed of a plurality of current sources with different current values.
14. The method of claim 12, wherein providing the current-mode DAC driver comprises providing a straight current-steering DAC driver implemented in current-mode logic (CML), and wherein providing the straight current-steering DAC driver comprises providing a tail current array formed of a plurality of current sources with different current values.
15. The method of claim 14, wherein providing the straight current-steering DAC driver further comprises providing an array of differential data switches, coupling each differential data switch of the array of differential data switches to a respective current source of the current sources, and configuring each differential data switch of the array of differential data switches to receive a differential bit pair of the first set of bits of the digital input signal.
15. The method of claim 14, wherein providing the straight current-steering DAC driver further comprises providing an array of differential data switches, coupling each differential data switch of the array of differential data switches to a respective current source of the current sources, and configuring each differential data switch of the array of differential data switches to receive a differential bit pair of the first set of bits of the digital input signal.
16. The method of claim 15, wherein providing the straight current-steering DAC driver further comprises providing an array of cascode pairs, and coupling each cascode pair of the array of cascode pairs to a respective differential data switch of the array of differential data switches, and wherein the method further comprises coupling drain nodes of the cascode pairs of the array of cascode pairs to one another to create a differential output node of the straight current- steering DAC driver, and coupling the differential output node of the straight current-steering DAC driver to a differential output node of the voltage-mode DAC driver.
16. The method of claim 15, wherein providing the straight current-steering DAC driver further comprises providing an array of cascode pairs, and coupling each cascode pair of the array of cascode pairs to a respective differential data switch of the array of differential data switches, and wherein the method further comprises coupling drain nodes of the cascode pairs of the array of cascode pairs to one another to create a differential output node of the straight current-steering DAC driver, and coupling the differential output node of the straight current-steering DAC driver to a differential output node of the voltage-mode DAC driver.
17. The method of claim 12, wherein providing the current-mode DAC driver comprises providing a folded current-steering DAC driver including a folded array of differential data switches, and coupling the folded array of differential data switches in parallel with an array of cascode transistor pairs to a pair of current sources, and wherein the method further comprises coupling drain nodes of the array of cascode transistor pairs to one another to create a differential output node of the folded current-steering DAC driver, and wherein digital input signals of the folded current- steering DAC driver are within a range of about 0-0.9 V.
17. The method of claim 12, wherein providing the current-mode DAC driver comprises providing a folded current-steering DAC driver including a folded array of differential data switches, and coupling the folded array of differential data switches in parallel with an array of cascode transistor pairs to a pair of current sources, and wherein the method further comprises coupling drain nodes of the array of cascode transistor pairs to one another to create a differential output node of the folded current-steering DAC driver, and wherein digital input signals of the folded current-steering DAC driver are within a range of about 0-0.9 V.
18. The method of claim 17, wherein providing the DAC driver circuit comprises providing an interleaved folded DAC driver by providing a first folded current- steering DAC driver and a second folded current-steering DAC driver, wherein providing the first folded current- steering DAC driver comprises providing a first folded array of differential data switches, a first set of dump switches, and a first set of output switches, wherein providing the second folded current-steering DAC driver comprises providing a second folded array of differential data switches, a second set of dump switches, and a second set of output switches, and wherein the method further comprises coupling differential output nodes of the first set of output switches and the second set of output switches to differential output nodes of the voltage-mode DAC driver.
18. The method of claim 17, wherein providing the DAC driver circuit comprises providing an interleaved folded DAC driver by providing a first folded current-steering DAC driver and a second folded current-steering DAC driver, wherein providing the first folded current-steering DAC driver comprises providing a first folded array of differential data switches, a first set of dump switches, and a first set of output switches, wherein providing the second folded current-steering DAC driver comprises providing a second folded array of differential data switches, a second set of dump switches, and a second set of output switches, and wherein the method further comprises coupling differential output nodes of the first set of output switches and the second set of output switches to differential output nodes of the voltage-mode DAC driver.
19. The method of claim 18, wherein the voltage-mode DAC driver includes a pair of input multiplexers, and wherein the method further comprises configuring each multiplexer of the pair of input multiplexers to couple a first or a second digital input signal to respective input nodes of the voltage-mode DAC driver.
19. The method of claim 18, wherein the voltage-mode DAC driver includes a pair of input multiplexers, and wherein the method further comprises configuring each multiplexer of the pair of input multiplexers to couple a first or a second digital input signal to respective input nodes of the voltage-mode DAC driver.
20. An analog-to-digital converter DAC circuit comprising: a clock generator configured to generate a clock signal; a digital signal processor configured to generate a first digital signal at a first bit rate; a multiplexer circuit configured to receive the first digital signal and to generate a second digital signal at a second bit rate; and a DAC driver circuit configured to receive the second digital signal and the clock signal, wherein the DAC driver circuit comprises: a differential current-mode DAC driver configured to receive least significant bits (LSBs) of the second digital signal and to generate a first analog signal; a differential voltage-mode DAC driver configured to receive most significant bits (MSBs) of the second digital signal and to generate a second analog signal; and a combination circuit configured to combine the first analog signal and the second analog signal and to generate an analog output signal, wherein resistor values of the differential voltage-mode DAC driver are adjustable.
20. An analog-to-digital converter DAC circuit comprising: a clock generator configured to generate a clock signal; a digital signal processor configured to generate a first digital signal at a first bit rate; a multiplexer circuit configured to receive the first digital signal and to generate a second digital signal at a second bit rate; and a DAC driver circuit configured to receive the second digital signal and the clock signal, wherein the DAC driver circuit comprises: a differential current-mode DAC driver configured to receive least significant bits (LSBs) of the second digital signal and to generate a first analog signal; a differential voltage-mode DAC driver configured to receive most significant bits (MSBs) of the second digital signal and to generate a second analog signal; and a combination circuit configured to combine the first analog signal and the second analog signal and to generate an analog output signal, wherein resistor values of the differential voltage-mode DAC driver are adjustable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845