DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-7, in the reply filed on 6/02/2026 is acknowledged.
Claims 8-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/02/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gorbachov et al. (US 2021/0384102).
Regarding claim 1, Gorbachov discloses a thermoelectric cooling chip in Figures 22-25 (See Peltier device, abstract and [70]), comprising:
a substrate (2230, [68]);
a buffer layer (BOX SiO2 layer 2220) disposed on a surface of the substrate ([68]);
a first etching stop layer (2272) disposed on the buffer layer (2220) ([68], The layer 2272 can be interpreted as a first and second layer having the same composition, specifically silicon nitride);
a dielectric layer (STI SiO2 2250, 2270) disposed on the first etching stop layer ([68]);
a first conductivity type semiconductor layer (2268n or 2268p) buried in the dielectric layer (Figures 22-25 and [69]);
a first wiring layer (interconnect 2282) disposed in the dielectric layer (STI layer) and directly contacting a sidewall (front surface in Figures 22-25, it is noted that the term “sidewall” can be interpreted as any surface of the first conductivity type semiconductor layer) the first conductivity type semiconductor layer (The interconnects directly contact layer 2268);
a second etching stop layer disposed on the first conductivity type semiconductor layer (The layer 2272 can be interpreted as a first and second layer having the same composition, specifically silicon nitride);
a second wiring layer (second interconnect) disposed in the dielectric layer (STI layer) and the second etching stop layer, and directly contacting the sidewall of the first conductivity type semiconductor layer (multiple interconnects protrude through the STI layer and the etch stop layer and directly contact the front surface of layer 2268 as shown in Figure 25);
a second conductivity type semiconductor layer (p-poly strip or n-poly strip 2290/2590, [70]-[71]) disposed on the first conductivity type semiconductor layer (2268n or 2268p) (Figures 22-25); and
a third wiring layer (interconnects 2280 or 2592) disposed on the second wiring layer and directly contacting a sidewall of the second conductive type semiconductor layer (front surface of 2290/2590, [69]-[71]).
It is noted that the term “disposed on” does not require direct contact or a particular order of the layers. All of the layers of the device of Grobachov are connected either directly or indirectly and are “disposed on” each other.
Regarding claim 2, Gorbachov discloses all of the claim limitations as set forth above. Gorbachov additionally discloses that the substrate (2230) comprises a silicon substrate (Figure 25, Bulk-Si).
Regarding claim 3, Gorbachov discloses all of the claim limitations as set forth above. Gorbachov additionally discloses that the first conductivity type semiconductor layer is a P-type doped polysilicon layer and the second conductivity type semiconductor layer is an N-type doped polysilicon layer (Figures 22-25 and [6]-[8] and [70]-[71], the first and second conductivity type can be interpreted as either the n-type or the p-type polysilicon).
Regarding claim 4, Gorbachov discloses all of the claim limitations as set forth above. Gorbachov additionally discloses that the first conductivity type semiconductor layer is an N-type doped polysilicon layer and the second conductivity type semiconductor layer is a P-type doped polysilicon layer (Figures 22-25, [6]-[8] and [70]-[71], the first and second conductivity type can be interpreted as either the n-type or the p-type polysilicon).
Regarding claim 5, Gorbachov discloses all of the claim limitations as set forth above. Gorbachov additionally discloses that the buffer layer (2220) comprises a silicon oxide layer (SiO2 BOX layer, [68] and [40] and Figure 25), the first etching stop layer comprises a silicon nitride layer (Figure 25 and [44]), and the second etching stop layer comprises a silicon nitride layer (Figure 25 and [44]).
Regarding claim 6, Gorbachov discloses all of the claim limitations as set forth above. Gorbachov additionally discloses that the dielectric layer comprises a silicon oxide layer (SiO2 STI layer, Figure 25 and [41]).
Regarding claim 7, Gorbachov discloses all of the claim limitations as set forth above. Gorbachov additionally discloses that the second conductivity type semiconductor layer and the first conductivity type semiconductor layer are electrically isolated by the second etching stop layer (Figures 22-25 and [49] and [70]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDSEY A BUCK whose telephone number is (571)270-1234. The examiner can normally be reached Monday-Friday 9am-5:30pm.
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/LINDSEY A BUCK/Primary Examiner, Art Unit 1728
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