Prosecution Insights
Last updated: April 19, 2026
Application No. 18/668,228

LOAD DRIVE CIRCUIT, LIGHT EMITTING DIODE DRIVER, AND DISPLAY DEVICE

Non-Final OA §102§103§112
Filed
May 19, 2024
Examiner
LAM, NELSON C
Art Unit
2627
Tech Center
2600 — Communications
Assignee
Lapis Technology Co., Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
3y 4m
To Grant
69%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
404 granted / 674 resolved
-2.1% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
36 currently pending
Career history
710
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
14.8%
-25.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 674 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/19/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: LIGHT EMITTING DIODE (LED) LOAD DRIVE CIRCUIT CAPABLE OF SUPPRESSING LEAKAGE CURRENT WHEN LED LOAD IS NOT DRIVEN Claim Objections Claims 1 and 5-8 are objected to because of the following informalities: As per claim 1, the limitation “a first transistor which has its drain connected to the external terminal, receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source; a second transistor which leads the output current generated by the first transistor in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing driving or non-driving of the load and is configured to control the second transistor to be in an on state when the instruction signal indicates the driving of the load or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the non-driving of the load” should be “a first transistor [[which has its]] comprising a drain connected to the external terminal, receives a drive voltage at [[its]] a gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between [[its]] the drain and a source of the first transistor; a second transistor which leads the output current generated by the first transistor when the second transistor is in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing a driving or a non-driving of the load and is configured to control the second transistor to be in [[an]] the on state when the instruction signal indicates the driving of the load or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the non-driving of the load”. As per claim 5, the limitation “wherein a drain of the second transistor is connected to a source of the first transistor, and one end of the resistor is connected to a source of the second transistor and the other end of the resistor is connected to the reference voltage line” should be “wherein a drain of the second transistor is connected to [[a]] the source of the first transistor, and one end of the resistor is connected to a source of the second transistor and [[the other]] another end of the resistor is connected to the reference voltage line”. As per claim 6, the limitation “wherein a source of the second transistor is connected to the reference voltage line, and one end of the resistor is connected to a source of the first transistor and the other end of the resistor is connected to a drain of the second transistor” should be “wherein a source of the second transistor is connected to the reference voltage line, and one end of the resistor is connected to [[a]] the source of the first transistor and [[the other]] another end of the resistor is connected to a drain of the second transistor”. As per claim 7, the limitation “a first transistor which has its drain connected to the external terminal, receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source; a second transistor which leads the output current generated by the first transistor in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing the light emitting diode to be turned on or off and is configured to control the second transistor to be in an on state when the instruction signal indicates the light on state or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state” should be “a first transistor [[which has its]] comprising a drain connected to the external terminal, receives a drive voltage at [[its]] a gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between [[its]] the drain and a source of the first transistor; a second transistor which leads the output current generated by the first transistor when the second transistor is in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing the light emitting diode to be turned on or turned off and is configured to control the second transistor to be in [[an]] the on state when the instruction signal indicates the light on state or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state”. As per claim 8, the limitation “a liquid crystal display panel which includes a plurality of scan lines extending in a horizontal direction of a two-dimensional screen and a plurality of data lines extending in a vertical direction of a two-dimensional screen; a scan driver which sequentially applies horizontal scan pulses to each of the plurality of scan lines; a data driver which supplies a plurality of drive signals each having a voltage value corresponding to a luminance level of each pixel based on a video signal to the plurality of data lines; a backlight panel which is installed on a back surface of the liquid crystal display panel and includes first to r-th light emitting diodes connected in series, where r is an integer of 2 or more; and a light emitting diode driver which drives the first to r-th light emitting diodes, wherein the light emitting diode driver includes: an external terminal which is connectable to a cathode of the last light emitting diode among the first to r-th light emitting diodes connected in series; a first transistor which has its drain connected to the external terminal, receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source; a second transistor which leads the output current generated by the first transistor in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing the first to r-th light emitting diodes to be turned on or off and is configured to control the second transistor to be in an on state when the instruction signal indicates the light on state or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state” should be “a liquid crystal display panel which includes a plurality of scan lines extending in a horizontal direction of a two-dimensional screen and a plurality of data lines extending in a vertical direction of [[a]] the two-dimensional screen; a scan driver which sequentially applies horizontal scan pulses to each of the plurality of scan lines; a data driver which supplies a plurality of drive signals each having a voltage value corresponding to a luminance level of [[each]] a pixel based on a video signal to the plurality of data lines; a backlight panel which is installed on a back surface of the liquid crystal display panel and includes a first to an r-th light emitting diodes connected in series, wherein r is an integer of 2 or more; and a light emitting diode driver which drives the first to the r-th light emitting diodes, wherein the light emitting diode driver includes: an external terminal which is connectable to a cathode of the last light emitting diode among the first to the r-th light emitting diodes connected in series; a first transistor [[which has its]] comprising a drain connected to the external terminal, receives a drive voltage at [[its]] a gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between [[its]] the drain and a source of the first transistor; a second transistor which leads the output current generated by the first transistor when the second transistor is in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing the first to the r-th light emitting diodes to be turned on or turned off and is configured to control the second transistor to be in [[an]] the on state when the instruction signal indicates the light on state or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 7-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitation “the light on state”, “the light off state“. There is insufficient antecedent basis for these limitations in the claim. Claim 8 recites the limitation “the last light emitting diode”, “the light on state”, “the light off state“. There is insufficient antecedent basis for these limitations in the claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith (US 20220353970). As per claim 1, Smith discloses a load drive circuit (Fig. 2, #200; [0081]) comprising: an external terminal (#272) which is connectable to a load (#270; [0081]); a first transistor (#230) which has its drain connected to the external terminal (#272), receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source ([0081]-[0086]); a second transistor (#220) which leads the output current generated by the first transistor (#230) in an on state to a reference voltage line to which a reference voltage is applied (#Vref; [0082]-[0085]); and a control circuit (#210) which receives an instruction signal instructing driving or non-driving of the load (#270) and is configured to control the second transistor (#220) to be in an on state when the instruction signal indicates the driving of the load (#270; [0081]-[0085]) or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the non-driving of the load. As per claim 7, Smith discloses a light emitting diode driver (Fig. 2, #200; [0079]) comprising: an external terminal (#272) which is connectable to a light emitting diode (#270; [0081]); a first transistor (#230) which has its drain connected to the external terminal (#272), receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source ([0081]-[0086]); a second transistor (#220) which leads the output current generated by the first transistor (#230) in an on state to a reference voltage line to which a reference voltage is applied (#Vref; [0082]-[0085]); and a control circuit (#210) which receives an instruction signal instructing the light emitting diode (#270) to be turned on or off and is configured to control the second transistor (#220) to be in an on state when the instruction signal indicates the light on state ([0081]-[0085]) or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Ishizawa (US 20160065201). As per claim 2, Smith discloses the load drive circuit according to claim 1. However, Smith does not explicitly teach a back gate of each of the first transistor and the second transistor is connected to the reference voltage line. Ishizawa teaches a back gate of each of the first transistor (Fig. 1, #MN11) and the second transistor (#MN12) is connected to the reference voltage line ([0021]; where the ground potential is functionally equivalent to a reference voltage). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the back gate of the first and second transistor of Smith connected according to Ishizawa so that the back gate that is connected to the ground potential. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20090109165) in view of Smith. As per claim 8, Park discloses a display device (Fig. 1; [0048]) comprising: a liquid crystal display panel (#10) which includes a plurality of scan lines extending in a horizontal direction of a two-dimensional screen and a plurality of data lines extending in a vertical direction of a two-dimensional screen ([0049]-[0051]); a scan driver (#20) which sequentially applies horizontal scan pulses to each of the plurality of scan lines ([0052]); a data driver (#30) which supplies a plurality of drive signals each having a voltage value corresponding to a luminance level of each pixel based on a video signal to the plurality of data lines ([0063]; [0055]); a backlight panel (#80) which is installed on a back surface of the liquid crystal display panel (#10) and includes first to r-th light emitting diodes connected in series, where r is an integer of 2 or more ([0051]; [0059]-[0061]); and a light emitting diode driver (#70) which drives the first to r-th light emitting diodes ([0057]; [0067]-[0070]); wherein the light emitting diode driver (#70) includes: an external terminal which is connectable to a cathode of the last light emitting diode among the first to r-th light emitting diodes connected in series ([0060]-[0068]; where an external terminal which is connectable to a cathode of the last light emitting diode is inherently present). However, Park does not explicitly teach a first transistor which has its drain connected to the external terminal, receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source; a second transistor which leads the output current generated by the first transistor in an on state to a reference voltage line to which a reference voltage is applied; and a control circuit which receives an instruction signal instructing the first to r-th light emitting diodes to be turned on or off and is configured to control the second transistor to be in an on state when the instruction signal indicates the light on state or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state. Smith teaches a first transistor (#230) which has its drain connected to the external terminal (#272), receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source ([0081]-[0086]); a second transistor (#220) which leads the output current generated by the first transistor (#230) in an on state to a reference voltage line to which a reference voltage is applied (#Vref; [0082]-[0085]); and a control circuit (#210) which receives an instruction signal instructing the first to r-th light emitting diodes (#270) to be turned on or off and is configured to control the second transistor (#220) to be in an on state when the instruction signal indicates the light on state ([0081]-[0085]; [0142]) or to control the second transistor to be in an off state and apply a control voltage having a predetermined voltage value higher than the reference voltage to the source of the first transistor when the instruction signal indicates the light off state. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the light emitting diode driver of Park configured according to Smith so as to provide current control circuitry for controlling a current through a load (Smith: [0004]). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Smith in view of Ishizawa. As per claim 9, Park in view of Smith discloses the display device according to claim 8. However, the prior art of Park and Smith do not explicitly teach a back gate of each of the first transistor and the second transistor is connected to the reference voltage line. Ishizawa teaches a back gate of each of the first transistor (Fig. 1, #MN11) and the second transistor (#MN12) is connected to the reference voltage line ([0021]; where the ground potential is functionally equivalent to a reference voltage). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the back gate of the first and second transistor of Park in view of Smith connected according to Ishizawa so that the back gate that is connected to the ground potential. Allowable Subject Matter Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of a load drive circuit comprising an external terminal which is connectable to a load; a first transistor which has its drain connected to the external terminal, receives a drive voltage at its gate, generates an output current corresponding to the drive voltage, and allows the output current to flow between its drain and source; and a second transistor which leads the output current generated by the first transistor in an on state to a reference voltage line to which a reference voltage is applied does not teach or fairly suggest a resistor which is included in a current path of the output current including the first transistor and the second transistor and converts the output current into a voltage; a differential amplifier which receives a voltage signal specifying a current value of the output current by a voltage value and outputs a difference between the voltage signal and the voltage converted by the resistor to the gate of the first transistor as the drive voltage via a first node; and a third transistor which receives the instruction signal at a gate and is turned on to apply the reference voltage to the first node when the instruction signal indicates the non-driving of the load. Claims 10 and 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of a display device comprising a liquid crystal display panel; a light emitting diode driver which drives the first to r-th light emitting diodes; wherein the light emitting diode driver includes: an external terminal which is connectable to a cathode of the last light emitting diode among the first to r-th light emitting diodes connected in series does not teach or fairly suggest a resistor which is included in a current path of the output current including the first transistor and the second transistor and converts the output current into a voltage; a differential amplifier which receives a voltage signal specifying a current value of the output current by a voltage value and outputs a difference between the voltage signal and the voltage converted by the resistor to the gate of the first transistor as the drive voltage via a first node; and a third transistor which receives the instruction signal at a gate and is turned on to apply the reference voltage to the first node when the instruction signal indicates the light off state. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nelson Lam/Examiner, Art Unit 2627 /KE XIAO/Supervisory Patent Examiner, Art Unit 2627
Read full office action

Prosecution Timeline

May 19, 2024
Application Filed
Oct 06, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
69%
With Interview (+9.5%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 674 resolved cases by this examiner. Grant probability derived from career allow rate.

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