Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 6-11 are objected to because of the following informalities: Claim 6 sets forth “mode resister set” in line 15. For purposes of compact prosecution, this is being interpreted as “mode register set”. Appropriate correction is required.
Claims 7-11 are objected to as dependent upon claim 6.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-5, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 sets forth “wherein the training operation includes a training operation between the external chip selection signal and the external clock”. It is unclear how the training operation would include a training operation. This language suggests that “the training operation” may include any number of things, including one or more “training operations”, which is unclear language and is not supported by the disclosure. Therefore, one of ordinary skill in the art would find this language indefinite and as failing to particularly point out and distinctly claim the subject matter which is regarded as the invention.
Claims 3-5 and 19 are rejected as dependent upon claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20090019323 A1 (Porterfield).
Regarding claim 12, Porterfield teaches an operating method of a semiconductor device, (Porterfield, FIG. 1, FIG. 5; [0006]: “memory devices used in the computer system of FIG. 1”) the operating method comprising: determining whether to perform a training operation (Porterfield, “training sequences…”) based on side-band signals (Porterfield, “Side band Configuration Bits”; Porterfield, [0030]: “TABLE 1”; [0030]: “Cfg.Calibrate…”) that are received through a side-band interface; (Porterfield, FIG. 1; “Side Band access bus 34”; [0039]: “As with the memory device 50, the host controller 240 includes a Register 293 that receives configuration data through the Side Band access bus 34 (FIG. 1) and a buffer 294. The Register 293 can also apply Configuration data to the Side Band access bus 34 through a second buffer 295.”; see FIG. 7) generating a sampling pattern based on in-band signals that are received through an in-band interface when it is determined to perform the training operation; (Porterfield, [0015]: “The DIMMs 22-28 receive commands, addresses and write data from the host controller 16 through a uni-directional command/address (“CA”) bus 30, and they transmit read data to the host controller 16 through a uni-directional data bus 32. Additionally, the DIMMs 22-28 are coupled to the host controller 16 through a Side Band access bus 34.”; “DQ Secondary Receive”) comparing the sampling pattern with a preset pattern; (Porterfield, FIG. 9; Porterfield, [0040]: “More specifically, the correct timing of the forwarded clock signals can be determined by sweeping the forwarded clock signals relative to the frame packet bits in small incremental delays over a period of time during training as shown in FIG. 9. While sweeping the relative timing between the frame packet bits and a forwarded clock signal, the captured frame packet bits are compared to expected data to determine when the frame packet bits in each lane are captured incorrectly at each end of the clock signal sweep.”); storing the comparing result; (Porterfield, FIG. 5, FIG. 9; [0029]: “As mentioned above, configuration data is coupled through the Side Band access bus 34 (FIG. 1) and applied to a Register 210 through a buffer 214. Configuration data from the Register 210 are applied to the Side Band access bus 34 through a second buffer 216.”) and outputting the result through the side-band interface. (The instant specification provides no specific detail regarding the limitation “outputting the stored comparing result through the side-band interface based on the side-band signals”; Porterfield teaches that a result is to be outputted through the side band interface based on signals (Porterfield, FIG. 1; “Side Band access bus 34”, “Side Band interface”), also [0017], [0029], [0039], etc.)
Regarding claim 13, Porterfield teaches the operating method of claim 12, wherein: the in-band signals comprise a chip selection signal and a clock, (Porterfield, FIG. 5; [0020]: “A memory device 50 according to one embodiment of the invention is shown in greater detail in FIG. 5. Most of the components of the memory device 50 are also used in the host controller 16 to transmit and receive the same signals that are transmitted and received by the memory device 50”) and the generating of the sampling pattern comprises generating the sampling pattern by latching the chip selection signal at a specific edge of the clock. (Porterfield, FIG. 5; [0040]: “More specifically, the correct timing of the forwarded clock signals can be determined by sweeping the forwarded clock signals relative to the frame packet bits in small incremental delays over a period of time during training as shown in FIG. 9. While sweeping the relative timing between the frame packet bits and a forwarded clock signal, the captured frame packet bits are compared to expected data to determine when the frame packet bits in each lane are captured incorrectly at each end of the clock signal sweep. The clock signal is then repositioned to capture the data at the midpoint between the two failing ends of the sweep. This will establish the clock in roughly the center of the data eye and is referred to as bit-lock.”
Regarding claim 14, Porterfield teaches the operating method of claim 12, wherein the comparing of the sampling pattern with the preset pattern comprises comparing the sampling pattern with the preset pattern to determine whether the sampling pattern and the preset pattern are identical with each other. (Porterfield, FIG. 9; Porterfield, [0040]: “More specifically, the correct timing of the forwarded clock signals can be determined by sweeping the forwarded clock signals relative to the frame packet bits in small incremental delays over a period of time during training as shown in FIG. 9. While sweeping the relative timing between the frame packet bits and a forwarded clock signal, the captured frame packet bits are compared to expected data to determine when the frame packet bits in each lane are captured incorrectly at each end of the clock signal sweep.”)
Regarding claim 15, Porterfield teaches the operating method of claim 12, and teaches further comprising initializing the stored comparing result, based on the side-band signals. (The instant specification provides no specific detail regarding the limitation “initializing the stored comparing result, based on the side-band signals”; Porterfield teaches that a result is to be created “initialized” and stored based on the side-band signals, including Porterfield [0015], [0040], etc.)
Regarding claim 16, Porterfield teaches the operating method of claim 12 and further teaches comprising outputting the stored comparing result through the side-band interface based on the side-band signals. (The instant specification provides no specific detail regarding the limitation “outputting the stored comparing result through the side-band interface based on the side-band signals”; Porterfield teaches that a result is to be outputted through the side band interface based on signals (Porterfield, FIG. 1; “Side Band access bus 34”, “Side Band interface”), also [0017], [0029], [0039], etc.)
Regarding claim 17, Porterfield teaches the operating method of claim 12, and teaches wherein: the side-band interface couples between the semiconductor device and a baseboard management controller. (The instant specification provides no specific detail on the relationship set forth by “coupled to”; Porterfield teaches that these limitations are to interface together; Porterfield, see FIG. 1, 2, and 5)
Regarding claim 18, Porterfield teaches the operating method of claim 17, and teaches wherein: the in-band interface couples between the semiconductor device and a controller. (The instant specification provides no specific detail on the relationship set forth by “coupled to”; Porterfield teaches that these limitations are to interface together; Porterfield, see FIG. 1, 2, and 5)
Response to Arguments
Applicant's arguments filed 2 December 2025 regarding claims 12-18 have been fully considered but they are not persuasive. In particular, Applicant response asserts that Porterfield merely describes a register that stores only operation parameters, and that Porterfield does not disclose storing a training result in a mode register, nor outputting the training result.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the operation parameters are training results…storing a training result in a mode register set…outputting the training result stored in the mode register through a sideband interface”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Allowable Subject Matter
Amended claim 1 appears to incorporate allowable subject matter as indicated in the Office action dated 2 October 2025. However, further search and consideration is required upon resolution of indefiniteness issues.
Amended claim 6 does not appear to be taught by the prior art of record. In particular, the prior art does not teach: a semiconductor device comprising: a reception circuit configured to receive in-band signals from a controller through an in-band interface; a transmission and reception circuit configured to transmit and receive side-band signals to and from a baseboard management controller through a side-band interface; a command decoding circuit configured to generate a training activation signal based on an output of the transmission and reception circuit; a sampling circuit configured to generate a sampling pattern by sampling an output of the reception circuit based on the training activation signal; a comparison circuit configured to generate at least one pattern comparison signal by comparing the sampling pattern with at least one preset pattern based on the training activation signal; and a mode register set configured to store the pattern comparison signal based on the training activation signal wherein the at least one pattern comparison signal stored in the mode register set is output to the baseboard management controller through the side-band interface.
However, further search and consideration is required upon claim objections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL JOHN KING/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827