DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 12/02/2025 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that Lakshmanamurthy in view of Bi does not teach “a serial bus interface circuit, to: receive a sequence of serial-bus-interface read instructions from a processor; forward the serial-bus-interface read instructions over the serial bus to the at least one device” of claim 1, the Examiner respectfully disagrees.
Lakshmanamurthy discloses a computer system (See Lakshmanamurthy: Fig. 1, Computer system 100) that comprises a memory controller (Fig. 1, Memory controller 120; i.e. the bus interface circuit of claim 1) that is coupled to a memory (Fig. 1, Memory 130) via a bus connection (Fig. 1, Memory controller 120 is coupled to memory 130 via a bus; i.e. the bus of claim 1). Lakshmanamurthy further discloses that memory controller receives read instructions from a processor (Fig. 1, Processor 110 sends plurality of read commands in order to memory controller 120 which is a sequence of reads; Paragraph 0016, memory controller 200 may service commands (requests to read or write data) from one or more masters (e.g., processor 110… Paragraph 0019, up to eight like transactions may be collected before switching to the other type (e.g., from read to write). Lakshmanamurthy does not disclose that the bus nor the bus interface circuit utilize serial bus protocol, thus the secondary reference Bi was incorporated to disclose a serial bus connector (See Bi: Fig. 4, Connector 210 is I2C serial protocol coupled to memory 100; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
While Applicant argues that the memory 130 of Lakshmanamurthy is a high-speed DRAM, as opposed to the the I2C bus of Bi which is a low-speed I2C bus, and thus Lakshmanamurthy teaches away from using the I2C protocol which would not provide sufficient data communication rates, the Lakshmanamurthy reference does not require that the system memory 130 be only DRAM (See Lakshmanamurthy: Paragraph 0013, system memory 130 may include dynamic random access memory (DRAM) or may be implemented using other memory technologies). Since the secondary reference Bi discloses NAND flash memory being used with the serial I2C protocol, the memory controller of Lakshmanamurthy could use the I2C protocol when communicating with a flash memory as taught by Bi. Lakshmanamurthy makes no requirement that the system memory 130 be only a high-speed DRAM, thus it would have been obvious to incorporate Bi’s serial bus and flash memory in order to enable the use of the well-known and commonly used I2C protocol that is a widely used data communication bus standard.
The Citations of Pertinent Prior Art section below includes the reference Vergis (US PGPUB 2023/0103368) disclosing that I2C/I3C can be used for communicating with high-speed DRAM system memory (See Vergis: Figure 2, I2C/I3C interface 216 with ports 218 to DRAM 220 and Paragraph 0042), the reference Stoler (US Patent 10,185,678) disclosing that I2C and/or any other serial protocol can be used with DDR DRAM system memory, references Gouw (US PGPUB 2015/0347348) and Kawanishi (US PGPUB 2023/0259485) disclosing that I2C/I3C are considered high speed protocols and can utilize high speed communication rates, and the references Sethi (US PGPUB 2018/0137074) and Kim (US PGPUB 2002/0194416) disclosing that it is well-known and conventional to utilize serial communication bus protocol when communicating with system memory (See Citation of Pertinent Prior Art section below for aforementioned citations). As can be seen, I2C/I3C can be used with system memory, and serial protocols are well-known and commonly used with system memory and are considered as high-speed.
Furthermore, Applicant argues that Lakshmanamurthy’s architecture is incompatible with serial bus architecture because there is a parallel multi-bank scheduling system (Lakshmanamurthy: Fig. 2A, Multiple FIFO banks 230 are parallel to each other). However, the multiple FIFO banks are only used to store multiple transactions from the command FIFO 210, but the bank scheduler 240 only selects one of the bank FIFOs 230 at a time based on whether or not the banks contain coherent/non-coherent read/write requests and schedules the output in a first-in-first-out (FIFO) manner where like transactions are scheduled sequentially (See Fig. 2A, Bank scheduler 240 only has a single output), not in a parallel output manner (See Lakshmanamurthy: Figure 3, Read requests are scheduled in step 340 or step 350 in a current FIFO bank, and the next bank is selected to be scheduled in step 310; Paragraph 0021, For each round the bank scheduler 240 may select a specific transaction type (e.g., read, write) from each bank FIFO in the bank FIFO set 230… Paragraph 0041, After scheduling a transaction, the process advances to the next bank (310)).
See Detailed Rejection Below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 10, 12-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438).
Regarding claim 1, Lakshmanamurthy teaches an apparatus (Fig. 1, Apparatus 100), comprising: a bus, to connect to at least one device (Fig. 1, Memory 130 (i.e. at least one device) in apparatus 100 is connected to rest of apparatus components via bus connection between 130 and 120 (i.e. a bus)); and a bus interface circuit (Figs. 1 and 2A, Memory controller 120 in Figure 1 and memory controller 200 in Figure 2A are the same embodiment and interfaces between the memory and the rest of the apparatus 100 (i.e. bus interface circuit); Paragraph 0015, FIG. 2A… memory controller 200 (e.g., 120 of FIG. 1)), to: receive a sequence of bus-interface read instructions from a processor (Fig. 1, Processor 110 sends plurality of read commands in order to memory controller 120 which is a sequence of reads; Paragraph 0016, memory controller 200 may service commands (requests to read or write data) from one or more masters (e.g., processor 110… Paragraph 0019, up to eight like transactions may be collected before switching to the other type (e.g., from read to write); forward the bus-interface read instructions over the bus to the at least one device (Fig. 2A, Memory controller 200 (i.e. 120 in Fig. 1) forwards read commands via arbiter 220 and bank scheduler 240 to memory device banks (i.e. at least one device 130 in Fig. 1); Paragraph 0019, The bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling); buffer data elements, which are received over the bus (Paragraph 0025, Data being read from the memory devices is received from the data bus) from the at least one device in response to the bus-interface read instructions (Fig. 2A, Read FIFO 280 enqueues (i.e. buffers) the return read data received over the bus connection from memory 130 in Figure 1 (i.e. over the bus) in response to the read command; Paragraph 0026, enqueues the read data and performs the reordering, based on sequence tags associated with both the original read requests); and make the buffered data elements available to the processor (Fig. 2A, Read FIFO 280 sends data elements to processor thus making it available to processor; Paragraph 0026, coherent processor (e.g., traditional processor) must receive the reads in the same order the read commands were presented… routes the reordered data to coherent processor that initiated the read transaction via the read FIFO 280).
Lakshmanamurthy does not teach the apparatus comprising a serial bus; and a serial bus interface circuit, to: receive a sequence of serial-bus-interface read instructions.
Bi teaches the apparatus comprising a serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface); and a serial bus interface circuit, to: receive a sequence of serial-bus-interface read instructions (Fig. 4, Memory controller 300 interfaces with CPU 230 and sends serial I2C instructions to memory; Paragraph 0027, central processing unit 230 of the motherboard 200 may transmit a command to the memory controller 300 for accessing the four memory modules 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 2, Lakshmanamurthy in view of Bi teaches the apparatus of claim 1.
Bi teaches wherein the apparatus further comprises wherein the serial bus comprises an Inter-Integrated Circuit (I2C) bus or an Improved Inter Integrated Circuit (I3C) bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 4, Lakshmanamurthy in view of Bi teaches the apparatus of claim 1. Lakshmanamurthy teaches the apparatus comprising wherein the bus interface circuit comprises a First-In-First-Out (FIFO) memory to buffer the serial-bus-interface read instructions that are pending to be forwarded to the at least one device (Fig. 2A, Command FIFO 210 enqueues read commands to be forwarded via arbiter 220; Paragraph 0016, commands and addresses associated therewith enter the memory controller 200 and are buffered in the command/address FIFO 210. Read requests may be tagged to allow proper association of read requests).
Bi teaches the apparatus comprising the serial bus interface circuit (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 10, Lakshmanamurthy in view of Bi teaches the apparatus of claim 1. Lakshmanamurthy teaches the apparatus comprising wherein the bus interface circuit is also to: receive, from the processor, a sequence of bus-interface write instructions and respective outbound data elements (Fig. 2A, Sequence of write commands are sent to FIFO 210 and write data elements are sent to write buffer 270; Paragraph 0019, bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling… Paragraph 0025, Write data enters the memory controller 200 through the write buffer 270); buffer the bus-interface write instructions and the outbound data elements (Fig. 2A, Command FIFO 210 buffers write commands and write buffer 270 buffers outbound data); and forward the buffered bus-interface write instructions and the buffered outbound data elements over the bus to the at least one device (Fig. 2A, Write commands forwarded by bank scheduler 240 and write data forwarded to memory device; Paragraph 0025, write data may be merged into the data path and steering logic 260, processed by the ECC logic 265, and forwarded via a data bus to data pins of the memory devices).
Bi teaches the apparatus comprising the serial bus interface circuit, serial instructions, and the serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 12, Lakshmanamurthy teaches a method, comprising: receiving a sequence of bus-interface read instructions from a processor (Fig. 1, Processor 110 sends plurality of read commands in order to memory controller 120 which is a sequence of reads; Paragraph 0016, memory controller 200 may service commands (requests to read or write data) from one or more masters (e.g., processor 110… Paragraph 0019, up to eight like transactions may be collected before switching to the other type (e.g., from read to write); forwarding the bus-interface read instructions over a bus to the at least one device (Fig. 2A, Memory controller 200 (i.e. 120 in Fig. 1) forwards read commands via arbiter 220 and bank scheduler 240 to memory device banks (i.e. at least one device 130 in Fig. 1); Paragraph 0019, The bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling); buffering data elements, which are received over the bus from the at least one device in response to the bus-interface read instructions (Fig. 2A, Read FIFO 280 buffers the return read data; Paragraph 0026, enqueues the read data and performs the reordering, based on sequence tags associated with both the original read requests); and making the buffered data elements available to the processor (Fig. 2A, Read FIFO 280 sends data elements to processor thus making it available to processor; Paragraph 0026, coherent processor (e.g., traditional processor) must receive the reads in the same order the read commands were presented… routes the reordered data to coherent processor that initiated the read transaction via the read FIFO 280).
Lakshmanamurthy does not teach the method comprising a serial bus; and receiving a sequence of serial-bus-interface read instructions.
Bi teaches the method comprising a serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface); and receiving a sequence of serial-bus-interface read instructions (Fig. 4, Memory controller 300 interfaces with CPU 230 and sends serial I2C instructions to memory; Paragraph 0027, central processing unit 230 of the motherboard 200 may transmit a command to the memory controller 300 for accessing the four memory modules 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s method to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 13, Lakshmanamurthy in view of Bi teaches the method of claim 12. Lakshmanamurthy teaches the method comprising further buffering the bus-interface read instructions, which are pending to be forwarded to the at least one device, in a First-In-First-Out (FIFO) memory (Fig. 2A, Command FIFO 210 enqueues read commands to be forwarded via arbiter 220; Paragraph 0016, commands and addresses associated therewith enter the memory controller 200 and are buffered in the command/address FIFO 210. Read requests may be tagged to allow proper association of read requests).
Bi teaches the apparatus comprising the serial bus interface circuit (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s method to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 19, Lakshmanamurthy in view of Bi teaches the method of claim 12. Lakshmanamurthy teaches the method further comprising receiving, from the processor, a sequence of bus-interface write instructions and respective outbound data elements (Fig. 2A, Sequence of write commands are sent to FIFO 210 and write data elements are sent to write buffer 270; Paragraph 0019, bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling… Paragraph 0025, Write data enters the memory controller 200 through the write buffer 270); buffering the bus-interface write instructions and the outbound data elements (Fig. 2A, Command FIFO 210 buffers write commands and write buffer 270 buffers outbound data); and forwarding the buffered bus-interface write instructions and the buffered outbound data elements over the bus to the at least one device (Fig. 2A, Write commands forwarded by bank scheduler 240 and write data forwarded to memory device; Paragraph 0025, write data may be merged into the data path and steering logic 260, processed by the ECC logic 265, and forwarded via a data bus to data pins of the memory devices).
Bi teaches the method comprising the serial bus interface circuit, serial instructions, and the serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s method to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) and further in view of Lee (US 2007/0198856).
Regarding claim 3, Lakshmanamurthy in view of Bi teaches the apparatus of claim 1. Neither Lakshmanamurthy nor Bi teaches the apparatus comprising wherein the serial bus interface circuit comprises a Dual-Port (DP) memory to buffer the data elements received in response to the serial-bus-interface read instructions.
Lee teaches the apparatus comprising wherein the serial bus interface circuit comprises a Dual-Port (DP) memory to buffer the data elements received in response to the serial-bus-interface read instructions (Fig. 5, Ram buffer 34 in a serial interface circuit 200; Paragraph 0096, flash-memory controller or flash-card controllers when only the serial engine is the bus master and a large buffer exists in serial engine or in one of the flash controllers. RAM buffer 34 could have one internal port and two external slave ports, or could have external logic to combine the two slave ports to access one port on RAM chips. A full dual-port RAM could also be used).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s apparatus to incorporate the teachings of Lee and include dual-port buffering in the apparatus.
One of ordinary skill in the art would be motivated to make the modifications in order to perform concurrent data transfers, thus increasing memory access speeds and reducing delays (See Lee: Paragraph 0098).
Claims 5, 7-8, 11, 14, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) and further in view of Nguyen (US 2006/0015660).
Regarding claim 5, Lakshmanamurthy in view of Bi teaches the apparatus of claim 1. Neither Lakshmanamurthy nor Bi teaches the apparatus comprising wherein the serial bus interface circuit is to detect a defined condition by analyzing at least some of the buffered data elements, and to initiate an action in response to the condition.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit (Fig. 1A, Serial storage controller, see SAS module 103; Paragraph 0031, system includes controller 101, which is coupled to buffer memory 111) is to detect a defined condition by analyzing at least some of the buffered data elements, and to initiate an action in response to the condition (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 7, the combination of Lakshmanamurthy/Bi/Nguyen teaches the apparatus of claim 5.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit is to detect the condition by assessing a count of the buffered data elements (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 8, the combination of Lakshmanamurthy/Bi/Nguyen teaches the apparatus of claim 5.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit is to detect the condition responsively to an extremum value among at least some of the buffered data elements (Fig. 2, Counter 201 reaches maximum (i.e. extremum) value due to buffered data elements; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111. Firmware of controller 101 may be used to pre-set the maximum value).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 11, the combination of Lakshmanamurthy/Bi/Nguyen teaches the apparatus of claim 5.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit is to decide whether to buffer a given data element, which is received over the serial bus, in accordance with a defined buffering condition (Fig. 1A, Channel 0 106A is decided to be paused when buffer is full; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 14, Lakshmanamurthy in view of Bi teaches the method of claim 12. Neither Lakshmanamurthy nor Bi teaches the method further comprising detecting a defined condition by analyzing at least some of the buffered data elements, and initiating an action in response to the condition.
Nguyen teaches the method further comprising detecting a defined condition by analyzing at least some of the buffered data elements, and initiating an action in response to the condition (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s method to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 16, the combination of Lakshmanamurthy/Bi/Nguyen teaches the method of claim 14.
Nguyen teaches the method comprising wherein detecting the condition comprises assessing a count of the buffered data elements (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s method to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 17, the combination of Lakshmanamurthy/Bi/Nguyen teaches the method of claim 14.
Nguyen teaches the method comprising wherein detecting the condition is performed responsively to an extremum value among at least some of the buffered data elements (Fig. 2, Counter 201 reaches maximum (i.e. extremum) value due to buffered data elements; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111. Firmware of controller 101 may be used to pre-set the maximum value).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s method to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 20, the combination of Lakshmanamurthy/Bi/Nguyen teaches the method of claim 12.
Nguyen teaches the method comprising wherein buffering the data elements comprises deciding whether to buffer a given data element, which is received over the serial bus, in accordance with a defined buffering condition (Fig. 1A, Channel 0 106A is decided to be paused when buffer is full; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s method to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) in view of Nguyen (US 2006/0015660) and further in view of Ho (US 2016/0378545).
Regarding claim 6, the combination of Lakshmanamurthy/Bi/Nguyen teaches the apparatus of claim 5. The combination of Lakshmanamurthy/Bi/Nguyen does not teach the apparatus comprising wherein the serial bus interface circuit is to detect the condition by calculating a statistical function over at least some of the buffered data elements.
Ho teaches the apparatus comprising wherein the serial bus interface circuit (Fig. 7, Serial processor 12; Paragraph 0127, serial resource allocation may be required to make sure that contentions from concurrent attempts to access main memory are managed and conflicts resolved and prevented) is to detect the condition by calculating a statistical function over at least some of the buffered data elements (Paragraph 0333, Queue threshold 148 can be computed as a function of the resulting measured/tested average and the resulting measured/tested statistical moment (e.g., standard deviation)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Nguyen’s apparatus to incorporate the teachings of Ho and use statistical analysis to determine queue thresholds.
One of ordinary skill in the art would be motivated to make the modifications in order to satisfy quality of service requirements, thus improving performance metrics (See Ho: Paragraphs 0332 and 0333).
Regarding claim 15, the combination of Lakshmanamurthy/Bi/Nguyen teaches the method of claim 14. The combination of Lakshmanamurthy/Bi/Nguyen does not teach the method comprising wherein detecting the condition comprises calculating a statistical function over at least some of the buffered data elements.
Ho teaches the method comprising wherein detecting the condition comprises calculating a statistical function over at least some of the buffered data elements (Paragraph 0333, Queue threshold 148 can be computed as a function of the resulting measured/tested average and the resulting measured/tested statistical moment (e.g., standard deviation)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Nguyen’s method to incorporate the teachings of Ho and use statistical analysis to determine queue thresholds.
One of ordinary skill in the art would be motivated to make the modifications in order to satisfy quality of service requirements, thus improving performance metrics (See Ho: Paragraphs 0332 and 0333).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) in view of Nguyen (US 2006/0015660) and further in view of Birke (US 2014/0219287).
Regarding claim 9, the combination of Lakshmanamurthy/Bi/Nguyen teaches the apparatus of claim 5. The combination of Lakshmanamurthy/Bi/Nguyen does not teach the apparatus comprising wherein the serial bus interface circuit is to send an indication to the processor upon detecting the condition.
Birke teaches the apparatus comprising wherein the serial bus interface circuit (Fig. 2, PCIe flow control performed by interface circuit 130; Paragraph 0014, external source may be used to interface with hardware using a PCI express (PCIe) or an Infiniband interface) is to send an indication to the processor upon detecting the condition (Fig. 2, Producer (i.e. processor) is sent a command to stop it from sending packets once threshold is reached; Paragraph 0042, processor may determine 225 whether the storage in the input buffer queue is more than the threshold for a maximum number of data packets in the input buffer queue. If the threshold has been exceeded, then the processor may issue 230 a stop command to the producer to stop sending further data packets).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Nguyen’s apparatus to incorporate the teachings of Birke and send stop commands to the processor when a queue threshold is reached.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent data loss from the host (See Birke: Paragraph 0002).
Regarding claim 18, the combination of Lakshmanamurthy/Bi/Nguyen teaches the method of claim 14. The combination of Lakshmanamurthy/Bi/Nguyen does not teach the method comprising wherein initiating the action comprises sending an indication to the processor upon detecting the condition.
Birke teaches the method comprising wherein initiating the action comprises sending an indication to the processor upon detecting the condition (Fig. 2, Producer (i.e. processor) is sent a command to stop it from sending packets once threshold is reached; Paragraph 0042, processor may determine 225 whether the storage in the input buffer queue is more than the threshold for a maximum number of data packets in the input buffer queue. If the threshold has been exceeded, then the processor may issue 230 a stop command to the producer to stop sending further data packets).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Nguyen’s method to incorporate the teachings of Birke and send stop commands to the processor when a queue threshold is reached.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent data loss from the host (See Birke: Paragraph 0002).
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2023/0103368 to Vergis discloses that I2C and/or I3C can be used to communicate with DRAM high-speed memory (See Vergis: Figure 2, I2C/I3C interface 216 with ports 218 to DRAM 220; Paragraph 0042, Memory module management device 148 further includes proxy controller and router 216 with an integrated I2C or I3C interface coupled to n I/O ports 218, also labeled P1, P2, P3, . . . , Pn. I/O port P1 is connected to multiple DRAMs 220).
US Patent 10,185,678 to Stoler discloses that system memory can be used with I2C or any other serial protocol (See Stoler: Col. 2, Lines 66-67 to Col. 3, Lines 1-13, memory device 110 can be primary system memory comprising Random Access Memory (RAM) or a storage device. The external memory device 110 can comprise DDR (Double Data Rate) RAM, DRAM (Dynamic RAM), SRAM, or other memory designs/types. External memory device 110 can comprise a mechanical/magnetic hard drive, a Solid State Drive (SSD), or other form of storage medium. External memory interface 112 can include a SATA (Serial Advanced Technology Attachment), PATA (Parallel Advanced Technology Attachment), Universal Serial Bus (USB), a SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), CAN (Controller area network), PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), or other memory interface protocols/technologies).
US PGPUB 2015/0347348 to Gouw discloses that I2C includes a high speed communication mode (See Gouw: Paragraph 0028, The current revisions of the I2C protocol can run bus speeds of 3.4 Mb/s in a high speed mode; 400 kb/s in a fast mode; and 10 kb/s in a low-speed mode).
US PGPUB 2023/0259485 to Kawanishi discloses that I2C/I3C are considered high speed communication protocols (See Kawanishi: Paragraph 0002, In recent years, it has been required to implement high-speed and multi-functionalized I2C, and a definition of an improved inter integrated circuit (I3C) has been formulated by a mobile industry processor interface (MIPI) alliance as a next-generation standard, and revision of I3C is in progress).
US PGPUB 2018/0137074 to Sethi discloses that system memory can be coupled to any serial bus interconnect (See Sethi: System memory 1075 is coupled to processor 1000 via serial bus 1005; Paragraph 0079, system memory 1075… bus 1005 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect).
US PGPUB 2002/0194416 to Kim discloses that serial bus protocols are well-known and conventionally used with DRAM system memory (See Kim Paragraph 0009, Presently, a serial bus architecture is adapted in the RIMM as a Rambus dynamic random access memory (DRAM) module system).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184