DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/16/2026 has been entered.
Response to Amendment
Claims 1 and 12 have been amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 10, 12-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) and further in view of Lee (US 2019/0073126).
Regarding claim 1, Lakshmanamurthy teaches an apparatus (Fig. 1, Apparatus 100), comprising: a bus, to connect to at least one device (Fig. 1, Memory 130 (i.e. at least one device) in apparatus 100 is connected to rest of apparatus components via bus connection between 130 and 120 (i.e. a bus)); and a bus interface circuit (Figs. 1 and 2A, Memory controller 120 in Figure 1 and memory controller 200 in Figure 2A are the same embodiment and interfaces between the memory and the rest of the apparatus 100 (i.e. bus interface circuit); Paragraph 0015, FIG. 2A… memory controller 200 (e.g., 120 of FIG. 1)), to: receive a sequence of bus-interface read instructions from a processor (Fig. 1, Processor 110 sends plurality of read commands in order to memory controller 120 which is a sequence of reads; Paragraph 0016, memory controller 200 may service commands (requests to read or write data) from one or more masters (e.g., processor 110… Paragraph 0019, up to eight like transactions may be collected before switching to the other type (e.g., from read to write); forward the bus-interface read instructions over the bus to the at least one device (Fig. 2A, Memory controller 200 (i.e. 120 in Fig. 1) forwards read commands via arbiter 220 and bank scheduler 240 to memory device banks (i.e. at least one device 130 in Fig. 1); Paragraph 0019, The bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling); buffer data elements, which are received over the bus (Paragraph 0025, Data being read from the memory devices is received from the data bus) from the at least one device in response to the bus-interface read instructions (Fig. 2A, Read FIFO 280 enqueues (i.e. buffers) the return read data received over the bus connection from memory 130 in Figure 1 (i.e. over the bus) in response to the read command; Paragraph 0026, enqueues the read data and performs the reordering, based on sequence tags associated with both the original read requests); and make the buffered data elements available to the processor (Fig. 2A, Read FIFO 280 sends data elements to processor thus making it available to processor; Paragraph 0026, coherent processor (e.g., traditional processor) must receive the reads in the same order the read commands were presented… routes the reordered data to coherent processor that initiated the read transaction via the read FIFO 280).
Lakshmanamurthy does not teach the apparatus comprising a serial bus; and a serial bus interface circuit, to: receive a sequence of serial-bus-interface read instructions.
Bi teaches the apparatus comprising a serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface); and a serial bus interface circuit, to: receive a sequence of serial-bus-interface read instructions (Fig. 4, Memory controller 300 interfaces with CPU 230 and sends serial I2C instructions to memory; Paragraph 0027, central processing unit 230 of the motherboard 200 may transmit a command to the memory controller 300 for accessing the four memory modules 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Neither Lakshmanamurthy nor Bi teaches the apparatus comprising: repeatedly execute the serial-bus-interface read instructions over the bus to the at least one device; and update the buffered data elements with data elements most recently received from the at least one device in response to the serial-bus-interface read instructions.
Lee teaches the apparatus comprising: repeatedly execute the serial-bus-interface read instructions over the bus to the at least one device (Fig. 1, Host 102 transmits plurality of read commands over serial protocol to controller 130, and controller 130 repeatedly executes the read commands; Paragraph 0109, controller 130 repeatedly performs read operations corresponding to a plurality of read commands received from the host 102 on the memory blocks included in the memory device 150... Paragraph 0057, host interface unit 132 may process… through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-E), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA)); and update the buffered data elements with data elements most recently received from the at least one device in response to the serial-bus-interface read instructions (Fig. 12, Buffer memory 6325 within controller (see Figure 1, 130) receives new data from each read command (i.e. update the buffered data elements) and outputs the data to the host 6310; Paragraph 0086, when a plurality of read commands are received from the host 102 for the data stored in the memory device 150, data corresponding to the read commands may be read from the memory device 150 by checking map data of the data corresponding to the read commands, and after storing the read data in the buffers/caches included in the memory 144 of the controller 130, the data stored in the buffers/caches may be provided to the host 102).
Lakshmanamurthy, Bi, and Lee are analogous arts because they are in the same field of endeavor of controlling read/write command processing from a memory controller to a memory device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s apparatus to incorporate the teachings of Lee and enable repeated processing of the group of read commands from Lakshmanamurthy with continuous updating of the buffer with new read data when each read command is processed over the serial bus of Bi.
One of ordinary skill in the art would be motivated to make the modifications in order to quickly, stably, and efficiently perform storage operations while minimizing complexity and power consumption (See Lee: Paragraphs 0004 and 0005).
Regarding claim 2, the combination of Lakshmanamurthy/Bi/Lee teaches the apparatus of claim 1.
Bi teaches wherein the apparatus further comprises wherein the serial bus comprises an Inter-Integrated Circuit (I2C) bus or an Improved Inter Integrated Circuit (I3C) bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 4, the combination of Lakshmanamurthy/Bi/Lee teaches the apparatus of claim 1. Lakshmanamurthy teaches the apparatus comprising wherein the bus interface circuit comprises a First-In-First-Out (FIFO) memory to buffer the serial-bus-interface read instructions that are pending to be forwarded to the at least one device (Fig. 2A, Command FIFO 210 enqueues read commands to be forwarded via arbiter 220; Paragraph 0016, commands and addresses associated therewith enter the memory controller 200 and are buffered in the command/address FIFO 210. Read requests may be tagged to allow proper association of read requests).
Bi teaches the apparatus comprising the serial bus interface circuit (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 10, the combination of Lakshmanamurthy/Bi/Lee teaches the apparatus of claim 1. Lakshmanamurthy teaches the apparatus comprising wherein the bus interface circuit is also to: receive, from the processor, a sequence of bus-interface write instructions and respective outbound data elements (Fig. 2A, Sequence of write commands are sent to FIFO 210 and write data elements are sent to write buffer 270; Paragraph 0019, bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling… Paragraph 0025, Write data enters the memory controller 200 through the write buffer 270); buffer the bus-interface write instructions and the outbound data elements (Fig. 2A, Command FIFO 210 buffers write commands and write buffer 270 buffers outbound data); and forward the buffered bus-interface write instructions and the buffered outbound data elements over the bus to the at least one device (Fig. 2A, Write commands forwarded by bank scheduler 240 and write data forwarded to memory device; Paragraph 0025, write data may be merged into the data path and steering logic 260, processed by the ECC logic 265, and forwarded via a data bus to data pins of the memory devices).
Bi teaches the apparatus comprising the serial bus interface circuit, serial instructions, and the serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s apparatus to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 12, Lakshmanamurthy teaches a method, comprising: receiving a sequence of bus-interface read instructions from a processor (Fig. 1, Processor 110 sends plurality of read commands in order to memory controller 120 which is a sequence of reads; Paragraph 0016, memory controller 200 may service commands (requests to read or write data) from one or more masters (e.g., processor 110… Paragraph 0019, up to eight like transactions may be collected before switching to the other type (e.g., from read to write); forwarding the bus-interface read instructions over a bus to the at least one device (Fig. 2A, Memory controller 200 (i.e. 120 in Fig. 1) forwards read commands via arbiter 220 and bank scheduler 240 to memory device banks (i.e. at least one device 130 in Fig. 1); Paragraph 0019, The bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling); buffering data elements, which are received over the bus from the at least one device in response to the bus-interface read instructions (Fig. 2A, Read FIFO 280 buffers the return read data; Paragraph 0026, enqueues the read data and performs the reordering, based on sequence tags associated with both the original read requests); and making the buffered data elements available to the processor (Fig. 2A, Read FIFO 280 sends data elements to processor thus making it available to processor; Paragraph 0026, coherent processor (e.g., traditional processor) must receive the reads in the same order the read commands were presented… routes the reordered data to coherent processor that initiated the read transaction via the read FIFO 280).
Lakshmanamurthy does not teach the method comprising a serial bus; and receiving a sequence of serial-bus-interface read instructions.
Bi teaches the method comprising a serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface); and receiving a sequence of serial-bus-interface read instructions (Fig. 4, Memory controller 300 interfaces with CPU 230 and sends serial I2C instructions to memory; Paragraph 0027, central processing unit 230 of the motherboard 200 may transmit a command to the memory controller 300 for accessing the four memory modules 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s method to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Neither Lakshmanamurthy nor Bi teaches the method comprising: repeatedly executing the serial-bus-interface read instructions over the bus to the at least one device; and updating the buffered data elements with data elements most recently received from the at least one device in response to the serial-bus-interface read instructions.
Lee teaches the method comprising: repeatedly executing the serial-bus-interface read instructions over the bus to the at least one device (Fig. 1, Host 102 transmits plurality of read commands over serial protocol to controller 130, and controller 130 repeatedly executes the read commands; Paragraph 0109, controller 130 repeatedly performs read operations corresponding to a plurality of read commands received from the host 102 on the memory blocks included in the memory device 150... Paragraph 0057, host interface unit 132 may process… through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-E), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA)); and updating the buffered data elements with data elements most recently received from the at least one device in response to the serial-bus-interface read instructions (Fig. 12, Buffer memory 6325 within controller (see Figure 1, 130) receives new data from each read command (i.e. update the buffered data elements) and outputs the data to the host 6310; Paragraph 0086, when a plurality of read commands are received from the host 102 for the data stored in the memory device 150, data corresponding to the read commands may be read from the memory device 150 by checking map data of the data corresponding to the read commands, and after storing the read data in the buffers/caches included in the memory 144 of the controller 130, the data stored in the buffers/caches may be provided to the host 102).
Lakshmanamurthy, Bi, and Lee are analogous arts because they are in the same field of endeavor of controlling read/write command processing from a memory controller to a memory device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi’s method to incorporate the teachings of Lee and enable repeated processing of the group of read commands from Lakshmanamurthy with continuous updating of the buffer with new read data when each read command is processed over the serial bus of Bi.
One of ordinary skill in the art would be motivated to make the modifications in order to quickly, stably, and efficiently perform storage operations while minimizing complexity and power consumption (See Lee: Paragraphs 0004 and 0005).
Regarding claim 13, the combination of Lakshmanamurthy/Bi/Lee teaches the method of claim 12. Lakshmanamurthy teaches the method comprising further buffering the bus-interface read instructions, which are pending to be forwarded to the at least one device, in a First-In-First-Out (FIFO) memory (Fig. 2A, Command FIFO 210 enqueues read commands to be forwarded via arbiter 220; Paragraph 0016, commands and addresses associated therewith enter the memory controller 200 and are buffered in the command/address FIFO 210. Read requests may be tagged to allow proper association of read requests).
Bi teaches the apparatus comprising the serial bus interface circuit (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s method to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Regarding claim 19, the combination of Lakshmanamurthy/Bi/Lee teaches the method of claim 12. Lakshmanamurthy teaches the method further comprising receiving, from the processor, a sequence of bus-interface write instructions and respective outbound data elements (Fig. 2A, Sequence of write commands are sent to FIFO 210 and write data elements are sent to write buffer 270; Paragraph 0019, bank scheduler 240 may select either all reads or all writes targeted to different banks and schedule these transactions for a particular round of scheduling… Paragraph 0025, Write data enters the memory controller 200 through the write buffer 270); buffering the bus-interface write instructions and the outbound data elements (Fig. 2A, Command FIFO 210 buffers write commands and write buffer 270 buffers outbound data); and forwarding the buffered bus-interface write instructions and the buffered outbound data elements over the bus to the at least one device (Fig. 2A, Write commands forwarded by bank scheduler 240 and write data forwarded to memory device; Paragraph 0025, write data may be merged into the data path and steering logic 260, processed by the ECC logic 265, and forwarded via a data bus to data pins of the memory devices).
Bi teaches the method comprising the serial bus interface circuit, serial instructions, and the serial bus (Fig. 1, Serial bus 110 is coupled to memory chip 102 of memory module 100 (i.e. at least one device) via I2C which is serial; Paragraph 0022, second non-volatile memory chip 102 may be coupled to the motherboard via the connection portion 110 adopting an inter-integrated circuit (I.sup.2C) interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy’s method to incorporate the teachings of Bi and include I2C serial protocol and I2C access commands for the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to use a high-speed serial communication standard that is well-known and commonly used in data communications.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) in view of Lee (US 2019/0073126) and further in view of Lee (US 2007/0198856), hereinafter Lee ‘8856.
Regarding claim 3, the combination of Lakshmanamurthy/Bi/Lee teaches the apparatus of claim 1. The combination of Lakshmanamurthy/Bi/Lee does not teach the apparatus comprising wherein the serial bus interface circuit comprises a Dual-Port (DP) memory to buffer the data elements received in response to the serial-bus-interface read instructions.
Lee ‘8856 teaches the apparatus comprising wherein the serial bus interface circuit comprises a Dual-Port (DP) memory to buffer the data elements received in response to the serial-bus-interface read instructions (Fig. 5, Ram buffer 34 in a serial interface circuit 200; Paragraph 0096, flash-memory controller or flash-card controllers when only the serial engine is the bus master and a large buffer exists in serial engine or in one of the flash controllers. RAM buffer 34 could have one internal port and two external slave ports, or could have external logic to combine the two slave ports to access one port on RAM chips. A full dual-port RAM could also be used).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s apparatus to incorporate the teachings of Lee ‘8856 and include dual-port buffering in the apparatus.
One of ordinary skill in the art would be motivated to make the modifications in order to perform concurrent data transfers, thus increasing memory access speeds and reducing delays (See Lee ‘8856: Paragraph 0098).
Claims 5, 7-8, 11, 14, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) in view of Lee (US 2019/0073126) and further in view of Nguyen (US 2006/0015660).
Regarding claim 5, the combination of Lakshmanamurthy/Bi/Lee teaches the apparatus of claim 1. The combination of Lakshmanamurthy/Bi/Lee does not teach the apparatus comprising wherein the serial bus interface circuit is to detect a defined condition by analyzing at least some of the buffered data elements, and to initiate an action in response to the condition.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit (Fig. 1A, Serial storage controller, see SAS module 103; Paragraph 0031, system includes controller 101, which is coupled to buffer memory 111) is to detect a defined condition by analyzing at least some of the buffered data elements, and to initiate an action in response to the condition (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 7, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the apparatus of claim 5.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit is to detect the condition by assessing a count of the buffered data elements (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 8, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the apparatus of claim 5.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit is to detect the condition responsively to an extremum value among at least some of the buffered data elements (Fig. 2, Counter 201 reaches maximum (i.e. extremum) value due to buffered data elements; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111. Firmware of controller 101 may be used to pre-set the maximum value).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 11, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the apparatus of claim 5.
Nguyen teaches the apparatus comprising wherein the serial bus interface circuit is to decide whether to buffer a given data element, which is received over the serial bus, in accordance with a defined buffering condition (Fig. 1A, Channel 0 106A is decided to be paused when buffer is full; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s apparatus to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 14, the combination of Lakshmanamurthy/Bi/Lee teaches the method of claim 12. The combination of Lakshmanamurthy/Bi/Lee does not teach the method further comprising detecting a defined condition by analyzing at least some of the buffered data elements, and initiating an action in response to the condition.
Nguyen teaches the method further comprising detecting a defined condition by analyzing at least some of the buffered data elements, and initiating an action in response to the condition (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s method to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 16, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the method of claim 14.
Nguyen teaches the method comprising wherein detecting the condition comprises assessing a count of the buffered data elements (Fig. 2, Storage controller contains overflow/underflow counters for buffers used to track buffered elements and determine overflow/underflow condition; Paragraph 0051, system 200 using two counters for tracking buffer memory 111 data or space availability, overflow and underflow conditions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s method to incorporate the teachings of Nguyen and enable buffer level tracking by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 17, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the method of claim 14.
Nguyen teaches the method comprising wherein detecting the condition is performed responsively to an extremum value among at least some of the buffered data elements (Fig. 2, Counter 201 reaches maximum (i.e. extremum) value due to buffered data elements; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111. Firmware of controller 101 may be used to pre-set the maximum value).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s method to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Regarding claim 20, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the method of claim 12.
Nguyen teaches the method comprising wherein buffering the data elements comprises deciding whether to buffer a given data element, which is received over the serial bus, in accordance with a defined buffering condition (Fig. 1A, Channel 0 106A is decided to be paused when buffer is full; Paragraph 0054, CH0 logic 106A is paused or stopped when counter 201 reaches a certain preset value indicating that there is no space available in buffer memory 111).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee’s method to incorporate the teachings of Nguyen and enable buffer level tracking and pausing by the memory controller.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent overflow/underflow conditions thus reducing memory loss errors (See Nguyen: Paragraphs 0003 and 0015).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) in view of Lee (US 2019/0073126) in view of Nguyen (US 2006/0015660) and further in view of Ho (US 2016/0378545).
Regarding claim 6, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the apparatus of claim 5. The combination of Lakshmanamurthy/Bi/Lee/Nguyen does not teach the apparatus comprising wherein the serial bus interface circuit is to detect the condition by calculating a statistical function over at least some of the buffered data elements.
Ho teaches the apparatus comprising wherein the serial bus interface circuit (Fig. 7, Serial processor 12; Paragraph 0127, serial resource allocation may be required to make sure that contentions from concurrent attempts to access main memory are managed and conflicts resolved and prevented) is to detect the condition by calculating a statistical function over at least some of the buffered data elements (Paragraph 0333, Queue threshold 148 can be computed as a function of the resulting measured/tested average and the resulting measured/tested statistical moment (e.g., standard deviation)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee/Nguyen’s apparatus to incorporate the teachings of Ho and use statistical analysis to determine queue thresholds.
One of ordinary skill in the art would be motivated to make the modifications in order to satisfy quality of service requirements, thus improving performance metrics (See Ho: Paragraphs 0332 and 0333).
Regarding claim 15, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the method of claim 14. The combination of Lakshmanamurthy/Bi/Lee/Nguyen does not teach the method comprising wherein detecting the condition comprises calculating a statistical function over at least some of the buffered data elements.
Ho teaches the method comprising wherein detecting the condition comprises calculating a statistical function over at least some of the buffered data elements (Paragraph 0333, Queue threshold 148 can be computed as a function of the resulting measured/tested average and the resulting measured/tested statistical moment (e.g., standard deviation)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee/Nguyen’s method to incorporate the teachings of Ho and use statistical analysis to determine queue thresholds.
One of ordinary skill in the art would be motivated to make the modifications in order to satisfy quality of service requirements, thus improving performance metrics (See Ho: Paragraphs 0332 and 0333).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmanamurthy (US 2007/0156946) in view of Bi (US 2022/0139438) in view of Lee (US 2019/0073126) in view of Nguyen (US 2006/0015660) and further in view of Birke (US 2014/0219287).
Regarding claim 9, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the apparatus of claim 5. The combination of Lakshmanamurthy/Bi/Lee/Nguyen does not teach the apparatus comprising wherein the serial bus interface circuit is to send an indication to the processor upon detecting the condition.
Birke teaches the apparatus comprising wherein the serial bus interface circuit (Fig. 2, PCIe flow control performed by interface circuit 130; Paragraph 0014, external source may be used to interface with hardware using a PCI express (PCIe) or an Infiniband interface) is to send an indication to the processor upon detecting the condition (Fig. 2, Producer (i.e. processor) is sent a command to stop it from sending packets once threshold is reached; Paragraph 0042, processor may determine 225 whether the storage in the input buffer queue is more than the threshold for a maximum number of data packets in the input buffer queue. If the threshold has been exceeded, then the processor may issue 230 a stop command to the producer to stop sending further data packets).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee/Nguyen’s apparatus to incorporate the teachings of Birke and send stop commands to the processor when a queue threshold is reached.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent data loss from the host (See Birke: Paragraph 0002).
Regarding claim 18, the combination of Lakshmanamurthy/Bi/Lee/Nguyen teaches the method of claim 14. The combination of Lakshmanamurthy/Bi/Lee/Nguyen does not teach the method comprising wherein initiating the action comprises sending an indication to the processor upon detecting the condition.
Birke teaches the method comprising wherein initiating the action comprises sending an indication to the processor upon detecting the condition (Fig. 2, Producer (i.e. processor) is sent a command to stop it from sending packets once threshold is reached; Paragraph 0042, processor may determine 225 whether the storage in the input buffer queue is more than the threshold for a maximum number of data packets in the input buffer queue. If the threshold has been exceeded, then the processor may issue 230 a stop command to the producer to stop sending further data packets).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lakshmanamurthy/Bi/Lee/Nguyen’s method to incorporate the teachings of Birke and send stop commands to the processor when a queue threshold is reached.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent data loss from the host (See Birke: Paragraph 0002).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2021/0280222 to Chang discloses that receiving a group of read commands and continuously processing reads in a loop (See Figure 11, Loop 1102 -> 1103 -> 1110 -> back to 1102; Paragraph 0065, If chip select remains low at block 1117, then the I/O bus turns around, and after waiting the I/O switching delay (1118), the procedure loops to block 1102 to receive a next command).
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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