Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This application is in response to application filed on May 20, 2024.
2. Claims 1-20 are pending and has been examined.
Drawings
3. Drawings submitted on 05/20/2024 are acceptable.
Specification
4. Abstract exceeds 150 words. Appropriate action is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 and 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3 and 13 recite “a magnitude” of the output current in line 4 should be “the magnitude” of the output current.
Claim 12 recites “the first switch circuitry” and “the second switch circuitry”. There are insufficient antecedent basis for these claim limitation.
Claim 13 dependent on claim 12, thus is also rejected because of its dependency.
Claim Rejections - 35 USC § 102
6.The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2,4,7-12,14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Saggini “20220263410”.
In re to claim 1, saggini discloses a power converter (Figs. 8,14,14-15 and 18-20 a power converter ) comprising:
a first circuit path (a path of current ICRES1 flow through Cres 1 and winding N1) including a first transformer winding (N1) connected in series with a first capacitor (Cres1) between a first node (213) of the first circuit path and a second node (VN21) of the first circuit path (path of current ICRES1 flow through Cres 1 and winding N1), the second node (VN21) of the first circuit path (path of current ICRES1 flow through Cres 1 and winding N1) connected to an output node of the power converter ( Iout node);
a second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) including a second transformer winding (N2) connected in series with a second capacitor (CC1) between a first node (VN1 node) of the second circuit path and a second node (VN11 node) of the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ), the second node (VN11 node) of the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) connected to the output node of the power converter ( Iout node);;
first switch circuitry (Q2) operative to control connectivity of the first node (213) of the first circuit path (path of current ICRES1 flow through Cres 1 and winding N1) to the second node of the first circuit path (VN21) ; and
second switch circuitry (Q3) operative to control connectivity of the first node (VN11 node) of the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) to the second node of the second circuit path (VN11) .
In re to claim 2, saggini discloses (Figs. 8,14,14-15 and 18-20): a controller (140) operative to control the first switch circuitry (Q2) and the second switch circuitry (Q3)in accordance with a first mode and a second mode (when control signal S1 and S2 are turn on and off) , the first mode including activation of the second switch circuitry to an ON-state and deactivation of the first switch circuitry to an OFF-state (Fig. 12 shows Q3 is on and Q2 is off), the second mode including activation of the first switch circuitry to an ON-state and deactivation of the second switch circuitry to an OFF-state (Fig.15 shows Q2 is on and Q3 is off) .
In re to claim 4, saggini discloses (Figs. 8,14,14-15 and 18-20): third switch circuitry (Q1) disposed in series with the first switch circuitry (Q2) between an input voltage source (Vin) and the output node (Iout node), the third switch circuitry directly coupled between the input voltage source and the first node of the first circuit path (Q1 is coupled to vin and node 213); and fourth switch circuitry (Q7) disposed in series with the second switch circuitry (Q3) between the output node (Iout thru inductor N2) and a reference voltage (ground), the fourth switch circuitry (Q7) directly coupled between the first node (VN1) of the second circuit path and a reference voltage node (ground thru Q9) .
In re to claim 7, saggini discloses (Figs. 8,14,14-15 and 18-20): a series connection of multiple switches (Fig. 8,14,14-15 and 18- 20) between an input voltage source (Vin) and a reference voltage node (ground), the series connection including the first switch circuitry and the second switch circuitry (Q2 and Q3 are in series).
In re to claim 8, saggini discloses (Figs. 8,14,14-15 and 18-20): wherein the first switch circuitry and the second switch circuitry are activated in accordance with zero voltage switching (see prag. 00143, 00160,00172, 00174,00181-00182) .
In re to claim 9, saggini discloses (Figs. 8,14,14-15 and 18-20): an autotransformer (multi-tapped autotransformer 850) including the first transformer winding (N1) and the second transformer winding (N2) disposed in series (N1 and N2 are in series).
In re to claim 10, saggini discloses (Figs. 8,14,14-15 and 18-20): wherein switching operation of the first switch circuitry (Q2) and the second switch circuitry (Q3) is configured to provide full bridge rectification of first current through the first capacitor and second current through the second capacitor to produce a corresponding output current outputted from the output node (Fig. 8,14,14-15 and 18- 20 shows a full bridge rectification and current ICrest and ICC1 flowing through capacitor CRES1 and CC1 respectively ) .
In re to claim 11, saggini discloses method (Figs. 8,14,14-15 and 18-20 showing a method of a power converter operation) comprising: controlling (140) connectivity of a first node (213) of a first circuit path (path of a current ICRES1 flow through Cres 1 and winding N1) to a second node (VN21) of the first circuit path (a current ICRES1 flow through Cres 1 and winding N1), the first circuit path including a first transformer winding (N1) connected in series with a first capacitor (Cres 1) between the first node (213) of the first circuit path (path of a current ICRES1 flow through Cres 1 and winding N1)and the second node (VN21) of the first circuit path ;
controlling connectivity of a first node (VN1 node) of a second circuit path (path of a current iCC1 flowing winding N2 ) to a second node (VN11 node) of the second circuit path (path of current iCC1 flowing through CC1 and winding N2), the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) including a second transformer winding (N2) connected in series with a second capacitor (CC1) between the first node (VN1 node) of the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) and the second node (VN11 node) of the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) ; and
outputting first current (ICRES1) received from the first circuit path of a current ICRES1 flow through Cres 1 and winding N1) and second current received (ICC1) from the second circuit path (path of current iCC1 flowing through CC1 and winding N2 ) from an output node of a power converter (Iout node).
In re to claim 12, saggini discloses (Figs. 8,14,14-15 and 18-20):: controlling (140) the first switch circuitry (Q2) and the second switch circuitry (Q3)in accordance with a first mode and a second mode (when control signal S1 and S2 are turn on and off) , the first mode including activation of the second switch circuitry to an ON-state and deactivation of the first switch circuitry to an OFF-state (Fig. 12 shows Q3 is on and Q2 is off), the second mode including activation of the first switch circuitry to an ON-state and deactivation of the second switch circuitry to an OFF-state (Fig.15 shows Q2 is on and Q3 is off) .
In re to claim 14, saggini discloses (Figs. 8,14,14-15 and 18-20): controlling operation of (140) third switch circuitry (Q1) disposed in series with the first switch circuitry (Q2) between an input voltage source (Vin) and the output node (Iout node), the third switch circuitry directly coupled between the input voltage source and the first node of the first circuit path (Q1 is coupled to vin and node 213); and fourth switch circuitry (Q7) disposed in series with the second switch circuitry (Q3) between the output node (Iout thru inductor N2) and a reference voltage (ground), the fourth switch circuitry (Q7) directly coupled between the first node (VN1) of the second circuit path and a reference voltage node (ground thru Q9) .
In re to claim 17, saggini discloses (Figs. 8,14,14-15 and 18-20): a series connection of multiple switches (see switches in Fig. 8,14,14-15 and 18- 20) between an input voltage source (Vin) and a reference voltage node (ground), the series connection including the first switch circuitry and the second switch circuitry (Q2 and Q3 are in series).
In re to claim 18, saggini discloses (Figs. 8,14,14-15 and 18-20): wherein the first switch circuitry and the second switch circuitry are activated in accordance with zero voltage switching (see prag. 00143, 00160,00172, 00174,00181-00182) .
In re to claim 19, saggini discloses (Figs. 8,14,14-15 and 18-20): an autotransformer (multi-tapped autotransformer 850) including the first transformer winding (N1) and the second transformer winding (N2) disposed in series (N1 and N2 are in series).
In re to claim 20, saggini discloses (Figs. 8,14,14-15 and 18-20): wherein switching operation of the first switch circuitry (Q2) and the second switch circuitry (Q3) is configured to provide full bridge rectification of first current through the first capacitor and second current through the second capacitor to produce a corresponding output current outputted from the output node (Fig. 8,14,14-15 and 18- 20 shows a full bridge rectification and current ICrest and ICC1 flowing through capacitor CRES1 and CC1 respectively ) .
Allowable Subject Matter
7. Claims 3, 5-6, 13 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 is objected because the prior art in the records fails to discloses or suggest the power converter including the limitation of “a magnitude of an output current outputted from the output node of the power converter is substantially equal to a magnitude of first current through the first circuit path during the first mode; and wherein a magnitude of the output current outputted from the output node of the power converter is substantially equal to a magnitude of second current through the second circuit path during the second mode. ”
Claim 5 is objected because the prior art in the records fails to discloses or suggest the power converter including the limitation of “wherein the first mode includes activation of the third switch circuitry and the first switch circuitry to ON-states and deactivation of the fourth switch circuitry and the second switch circuitry to OFF-states; and wherein the second mode includes deactivation of the third switch circuitry and the first switch circuitry to OFF-states and activation of the fourth switch circuitry and the second switch circuitry to ON-states.”
Claim 13 is objected because the prior art in the records fails to discloses or suggest the power converter including the limitation of “a magnitude of an output current outputted from the output node of the power converter is substantially equal to a magnitude of first current through the first circuit path during the first mode; and wherein a magnitude of the output current outputted from the output node of the power converter is substantially equal to a magnitude of second current through the second circuit path during the second mode. ”
Claim 15 is objected because the prior art in the records fails to discloses or suggest the power converter including the limitation of “activating the third switch circuitry and the first switch circuitry to ON-states and deactivating the fourth switch circuitry and the second switch circuitry to OFF-states; and in the second mode, deactivating the third switch circuitry and the first switch circuitry to OFF-states and activating the fourth switch circuitry and the second switch circuitry to ON-states.”
Claim 6 dependent on claim 5 , thus is also objected because of its dependency.
Claim 16 dependent on claim 15 , thus is also objected because of its dependency.
Note: claims 3 and 13 contains allowable subject matter. However applicant has to comply 112(b) issues.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ursino “20240223089” the present invention disclose a power converter to provide The first series circuit path includes a first circuit component disposed in series with a first winding of the multiple windings; the second series circuit path including a second circuit component disposed in series with a second winding of the multiple windings. The first series circuit path is connected in parallel with the second series circuit path
Rizzonlatti “20230353058” The first power converter produces an intermediate voltage and a first output current derived from an input voltage. The first power converter supplies the intermediate voltage to the second power converter. The second power converter produces a second output current based on the intermediate voltage received from the first power converter. An output node of the voltage converter outputs a sum of the first output current and the second output current to produce an output voltage. A power supply can be configured to include any number of multiple voltage converters in parallel to power a load.
Rizzolatti “11362576” the apparatus provides improved performance of power conversion through implementation of multiple types of novel switched-capacitor converters. The apparatus reduces a carbon footprint and provides better use of energy through more efficient energy conversion, thus improving power conversion efficiency of power supplies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/SISAY G TIKU/
Primary Examiner, Art Unit 2838