DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the Preliminary Amendment filed on 05/20/2024.
Status of the Claims:
Claim(s) 18-22, and 26-29 has/have been canceled.
Claim(s) 1-17 and 23-25 is/are pending in this Office Action.
Of the above claim(s) 11-17 is/are withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of Species 1 of Figures 1-7 in the reply filed on 05/07/2026 is acknowledged.
Claims 11-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/07/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0075259 to GEURTS et al. (hereinafter GEURTS).
Regarding independent claim 1, GEURTS teaches an image pixel (pixel 22, see Fig. 6) comprising:
a photoelectric conversion element (photodiode 72, see Fig. 6);
a common circuit including a floating diffusion node configured to receive charges from the photoelectric conversion element, and configured to transfer an output voltage to a first node based on a voltage of the floating diffusion node (transfer transistor 74 (TX) that transfer the charges from PD to the floating diffusion region 78 (FD), see Fig. 6);
a sampling circuit including a first capacitor and a second capacitor configured to store the output voltage of the first node (charge storage region 91 comprising capacitor 94 and capacitor 96, see par. [0035] and Fig. 6); and
a first transistor configured to electrically connect at least one of the first or second capacitors to the floating diffusion node (transistor 98 (READ) electrically connects FD to capacitor 96, see par. [0035] and Fig. 6).
Regarding claim 2, GEURTS teaches the image pixel of claim 1, further comprising:
a second transistor connected between the first node and a column line, wherein, in a first operating mode, the second transistor is configured to transfer the output voltage of the first node to the column line (SEL transistor 86 connects the first node to the column line 88, see Fig. 6).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,924,570 to Jung et al. discloses an image sensor includes a pixel array including a plurality of pixels; and processing circuitry, wherein each of the plurality of pixels includes: a photodiode; a floating diffusion node configured to integrate photocharge generated by the photodiode; a first capacitor configured to store charge corresponding to a voltage of the floating diffusion node which is reset; a first sampling transistor one terminal of which is connected to the second node, and another terminal of which is connected to the first capacitor, being configured to sample charge to the first capacitor; a second capacitor configured to store charge corresponding to the voltage of the floating diffusion node at which the photocharge has been integrated; and a second sampling transistor, one terminal of which is connected to the second node, and another terminal of which is connected to the second capacitor, being configured to sample charge to the second capacitor.
US 2018/0115730 to VELICHKO discloses an image sensor pixel may include multiple split photodiodes that are covered by a single microlens. The image sensor may include a charge overflow capacitor coupled to a pixel charge storage within the image sensor via a gain control transistor. The image sensor pixel may have phase detection capabilities in a first mode of operation enabled by comparing phase signals generated from the split photodiodes. The image sensor pixel also may generate and readout image signals simultaneously in both rolling shutter operations and global shutter operations in a second mode of operation. The image sensor pixel may also generate an image using a linear combination of at least two signals read out using the charge overflow capacitor and light flickering mitigation operations. The image may be a high dynamic range image that is generated from at least a low exposure signal and a high exposure signal.
US 2016/0142653 to CHO et al. discloses an image sensor capable of implementing a global shutter mode and a rolling shutter mode. The image sensor includes a row driver, a pixel array, an analog-to-digital converter, and an output compensating circuit. The row driver performs decoding for a reset operation, a transfer operation and a read operation, and generates control signals. The pixel array, in a rolling shutter mode, performs the transfer operation on a second row group while the read operation for a first row group is performed, and receives an optical signal, converts the optical signal to electrical signal, and outputs the electrical signal as an image signal in response to the control signals.
US 8,471,315 to Hynecek et al. discloses a solid-state CMOS image sensor array and in particular describes in detail image sensor array pixels having global and rolling shutter capabilities that are using a dual channel transfer-storage gate for charge transfer from a PD to a TX gate well and from the TX gate well onto a FD. The dual channels are stacked above each other where a shallow charge channel is used to drain surface generated dark current away from the pixel structure, while a buried bulk channel provides for standard charge transfer and storage functions. This feature thus improves the sensor noise performance and prevents signal contamination and various shading effects caused by the dark current buildup during a prolonged charge storage sequence in pixels of image sensor arrays using the global shutter mode of operation. Several embodiment of this concept are described including pixels which utilize shared circuitry, a complete PD reset capability, and an efficient anti-blooming control.
Allowable Subject Matter
Claim(s) 3-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 23-25 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasize that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, the image pixel of claim 2, further comprising:
a precharge circuit connected to the first node, wherein the sampling circuit further includes:
a third transistor electrically connected between the first node and a second node;
a fourth transistor electrically connected between the second node and the first capacitor; and
a fifth transistor electrically connected between the second node and the second capacitor.
Regarding claim(s) 4-10, claim(s) further depend from claim 3 and is/are allowable for the same reasons stated above.
Regarding independent claim 23, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasize that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, an image sensor comprising:
a sampling circuit including a second transistor electrically connected between the first node and a second node, a first capacitor, and a second capacitor, wherein the first and second capacitors are electrically connected to the second node;
a third transistor electrically connected between the second node and the column line; and
a fourth transistor configured to electrically connect the floating diffusion node and the first capacitor, and
wherein, when the operating mode is a rolling shutter mode, the fourth transistor is configured to transfer charges that overflow from the photodiode to the first capacitor for storage therein.
Regarding claim(s) 24-25, claim(s) depend from independent claim 23 and is/are allowable for the same reasons stated above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGEL L GARCES-RIVERA whose telephone number is (571)270-7268. The examiner can normally be reached Mon-Fri 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-727-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANGEL L GARCES-RIVERA/ Examiner, Art Unit 2637
/SINH TRAN/ Supervisory Patent Examiner, Art Unit 2637
Prosecution Insights