DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (US 2021/0384874).
Figure 1 of Sun has been annotated and reproduced below for discussion purposes in the office action.
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In regard to Claim 1:
Sun discloses, in Figure 1, an amplifier circuit having a first input terminal (VI+), a second input terminal (VI-), a first output terminal (Vx+), a second output terminal (Vx-), a first node (1), a second node (2), a third node (3), and a fourth node (4), and receiving a first input voltage and a second input voltage respectively through the first input terminal (VI+ voltage) and the second input terminal (VI- voltage), the amplifier circuit comprising:
a first transistor (M1) having a first terminal (M1 source), a second terminal (M1 drain), and a first control terminal (M1 gate), wherein the first terminal (M1 source) is coupled to the first node (1), the second terminal (M1 drain) is coupled to the second output terminal (Vx-), and the first control terminal (M1 gate) is coupled to the first input terminal (VI+);
a second transistor (M3) having a third terminal (M3 source), a fourth terminal (M3 drain), and a second control terminal (M3 gate), wherein the third terminal (M3 source) is coupled to the second node (2), the fourth terminal (M3 drain) is coupled to the second output terminal (Vx-), and the second control terminal (M3 gate) is coupled to the first input terminal (VI+);
a third transistor (M2) having a fifth terminal (M2 source), a sixth terminal (M2 drain), and a third control terminal (M2 gate), wherein the fifth terminal (M2 source) is coupled to the first node (1), the sixth terminal (M2 drain) is coupled to the first output terminal (Vx+), and the third control terminal (M2 gate) is coupled to the second input terminal (VI-);
a fourth transistor (M4) having a seventh terminal (M4 source), an eighth terminal (M4 drain), and a fourth control terminal (M4 gate), wherein the seventh terminal (M4 source) is coupled to the second node (2), the eighth terminal (M4 drain) is coupled to the first output terminal (Vx+), and the fourth control terminal (M4 gate) is coupled to the second input terminal (VI-);
a first capacitor (Cres) having a ninth terminal (9) and a tenth terminal (10), wherein the ninth terminal (9) is coupled to the third node (3), and the tenth terminal (10) is coupled to the fourth node (4);
a first switch (S1) coupled between the third node (3) and a first reference voltage (ground);
a second switch (S2) coupled between the fourth node (4) and a second reference voltage (Vdd);
a third switch (S3) coupled between the first node (1) and the third node (3);
a fourth switch (S4) coupled between the second node (2) and the fourth node (4); and
a reference voltage generation circuit (Vdd, ground generator (not shown)) coupled to the first input terminal (VI+) and the second input terminal (VI-) and configured to generate at least one of the first reference voltage (ground) and the second reference voltage (Vdd) according to the first input voltage (VI+ voltage) and the second input voltage (VI- voltage). (¶ 0086)
In regard to Claim 4:
Sun discloses, in Figure 1, an amplifier circuit having a first input terminal (VI+), a second input terminal (VI-), a first output terminal (Vx+), a second output terminal (Vx-), a first node (1), a second node (2), a third node (3), and a fourth node (4), and receiving a first input voltage and a second input voltage respectively through the first input terminal (VI+ voltage) and the second input terminal (VI- voltage), the amplifier circuit comprising:
a first transistor (M1) having a first terminal (M1 source), a second terminal (M1 drain), and a first control terminal (M1 gate), wherein the first terminal (M1 source) is coupled to the first node (1), the second terminal (M1 drain) is coupled to the second output terminal (Vx-), and the first control terminal (M1 gate) is coupled to the first input terminal (VI+);
a second transistor (M3) having a third terminal (M3 source), a fourth terminal (M3 drain), and a second control terminal (M3 gate), wherein the third terminal (M3 source) is coupled to the second node (2), the fourth terminal (M3 drain) is coupled to the second output terminal (Vx-), and the second control terminal (M3 gate) is coupled to the first input terminal (VI+);
a third transistor (M2) having a fifth terminal (M2 source), a sixth terminal (M2 drain), and a third control terminal (M2 gate), wherein the fifth terminal (M2 source) is coupled to the first node (1), the sixth terminal (M2 drain) is coupled to the first output terminal (Vx+), and the third control terminal (M2 gate) is coupled to the second input terminal (VI-);
a fourth transistor (M4) having a seventh terminal (M4 source), an eighth terminal (M4 drain), and a fourth control terminal (M4 gate), wherein the seventh terminal (M4 source) is coupled to the second node (2), the eighth terminal (M4 drain) is coupled to the first output terminal (Vx+), and the fourth control terminal (M4 gate) is coupled to the second input terminal (VI-);
a first capacitor (Cres) having a ninth terminal (9) and a tenth terminal (10), wherein the ninth terminal (9) is coupled to the third node (3), and the tenth terminal (10) is coupled to the fourth node (4);
a first switch (S1) coupled between the third node (3) and a first reference voltage (ground);
a second switch (S2) coupled between the fourth node (4) and a second reference voltage (Vdd);
a third switch (S3) coupled between the first node (1) and the third node (3);
a fourth switch (S4) coupled between the second node (2) and the fourth node (4); and
a reference voltage generation circuit (Vdd, ground generator (not shown)) coupled to the first input terminal (VI+) and the second input terminal (VI-) and configured to generate at least one of the first reference voltage (ground) and the second reference voltage (Vdd) according to the first output voltage (Vx+) and the second output voltage (Vx-). (¶ 0095)
Allowable Subject Matter
Claims 2-3 and 5-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang et al. (US 2023/0246613) discloses an amplifier and a method for controlling a common mode voltage thereof. The method includes: generating a control signal according to a positive-terminal input signal, a negative-terminal input signal and a target common mode voltage; and coupling the controlling signal to a first terminal of a positive-terminal capacitor and a first terminal of a negative-terminal capacitor, to adjust degree of conduction of a positive-terminal p-type transistor and degree of conduction of a negative-terminal p-type transistor, or to adjust degree of conduction of a positive-terminal n-type transistor and degree of conduction of a negative-terminal n-type transistor, thereby changing a common mode voltage.
Huang et al. (US 2023/0040066) discloses an amplifier circuit, which has a first output terminal and a second output terminal, includes a first charge-steering amplifier, a second charge-steering amplifier, a first switch, and a second switch. The first charge-steering amplifier includes a first input terminal, a second input terminal, a first capacitor, and a second capacitor, and is used for amplifying a first input signal in a first operation period. The second charge-steering amplifier includes a third input terminal, a fourth input terminal, the first capacitor, and the second capacitor, and is used for amplifying a second input signal in a second operation period.
Hsieh et al. (US 2020/0007085) discloses an amplifier (100) has a first switch coupled between a first terminal of a first output capacitor and a voltage detection node. A second switch is coupled to the current source and the voltage detection node. A voltage detector (106) is coupled to the voltage detection node and the first switch. A third switch is coupled between the voltage detection node and a power source. A level shifter is coupled to a second terminal of the first output capacitor. The voltage detector detects output voltage of the first terminal of the first output capacitor via the voltage detection node.
Zabroda (US 2020/0005882) discloses coupling a differential input signal to NMOS transistors (M3, M4) and PMOS transistors (M1, M2) through a first switch (405) coupled to a first capacitor (C1) coupled to a gate terminal of the first PMOS transistor and a second capacitor (C2) coupled to the gate terminal of the first NMOS transistor, and a third capacitor (C3) coupled to the gate terminal of the second PMOS via a second switch (407) and a fourth capacitor (C4) coupled to the gate terminal of the second NMOS transistor. The gate terminal of the first PMOS transistor is coupled to the gate terminal of the second PMOS transistor through a third switch (419).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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