DETAILED ACTION
This action is in response to the application filed on 5/20/2024.
Claims 1-20 are pending in this application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5 and 13 are objected to because of the following informalities:
Claim 5 at line 1 “the plurality of passes” lacks proper antecedent basis. Claim 13 has a similar issue.
Appropriate correction is required.
Claim Interpretation
As to claim 1, “a deep learning compiler” is software and therefore not presumed to invoke 112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 7-10, 13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Baskaran et al. (US Patent Application Publication 2021/0232379 A1) in view of Brady et al. (US Patent Application Publication 2019/0392296 A1).
As to claim 1, Baskaran teaches an electronic device (See Figs 1 and 2A and associated text, e.g. [0016]- a system is provided for facilitating optimized execution of a program by a processing system) comprising a compiler (See e.g. [0023]- a sequential compilation flow using a polyhedral compiler targeting a multi-level processing system for executing a compiled program) configured to extract a plurality of hierarchies from the target system based on a hardware representation (See e.g. [0047]- we decompose the general compilation flow for a hierarchical hardware target into a sequence of optimizations. At each step, a different level of the hardware hierarchy is considered and Figs: 3A, 3B and associated text, e.g. [0075]- In step 304, a particular memory level from a target architecture is selected. The target architecture may have any number of processor and/or memory levels, such as 1, 2, 3, 5, 8, etc., levels, and [0079]- In various embodiments, after focalization iteration(s) are performed for a selected memory level, another memory level is selected from the target architecture at step 304, and the steps 306-314, each of the steps 306, 310, 312 being optional, may be repeated for the other memory level. These process steps may be iterated for one, some, or all memory levels of the target architecture), and perform iterative compilation on the plurality of extracted hierarchies (see e.g. [0044]- We describe various embodiments that feature an iterative/sequential approach where every architecture level is successively targeted, as illustrated in FIG. 1. In our approach, a different optimization problem is solved specifically for every considered level, according to one or more hardware characteristics of the considered level, see Fig.2A and associated text, e.g. [0047]- In particular, various optimizations applied and the parameters used are specialized for that specific level, [0076]- In the optional step 306, compiler optimizations such as loop fission, loop fusion, loop interchange, loop unroll, loop jam and unroll, and/or loop reversal, may be performed. Alternatively, or in addition, optimizations such as strip mining and/or loop tiling may be performed. Strip mining and loop tiling can increase the number of dimensions (also called dimensionality or depth) of a loop nest. These optimizations can be based on one or more characteristics of the memory at the selected level, such as memory size, memory speed, the number of read and/or write ports of the memory, memory power consumption, etc. As such, these optimizations may optimize the memory access (in terms of speed, number of memory accesses, power consumed, etc.), at the selected memory level).
Baskaran does not specifically teach a deep learning compiler or receiving a hardware representation corresponding to a target system comprising a hierarchical structure.
In an analogous art of compiling code however, Brady discloses a deep learning compiler (e.g. compiler 105, see Fig.1, and associated text, e.g. [0028]- an example compiler (e.g., 105), such as an example neural network compiler and [0046]- an improved compiler may be configured to consume a machine learning framework's (e.g., TensorFlow, Caffe™, etc.) representation (e.g., 110) of a Deep Neural Network (DNN), receiving a hardware representation corresponding to a target system comprising a hierarchical structure (e.g. target descriptor, see e.g. [0024]- target descriptor data 120 to describe attributes of a target hardware processing device 125, which is targeted for executing the code to be generated by the compiler 105) and [0047]- the compiler 105 may identify, from a target descriptor file 120, the memory and compute resources (and other resources (e.g., communication resources)) available on the target hardware device (e.g., and store this information in the IR (e.g., in structural model 1020), and extract a plurality of hierarchies from the target system based on a hardware representation (See e.g. [0047]- A set of sub-models (e.g., 1005, 1010, 1015) may be generated and encapsulated within the intermediate representation 140 to provide a configurable representation of a mathematical structure (e.g., the computation model of the intermediate representation) of the neural network described in graph 110, for instance, in the form of one or more computation graphs from which a binary may be constructed and [0071]- Compilation passes may determine similar information for each of the tensors in the data model, and memory allocator objects (e.g., 1405, 1410) may extract this information and define buffers to identify the amount of memory to “reserve” or allocate for storage of each of the tensors during execution of the neural network).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Baskaran to incorporate/implement the limitations as taught by Brady in order to provide a specialized compilation system that uses machine learning models more efficiently and effectively for the purpose of optimization.
As to claim 2, Baskaran also teaches wherein, for the performing of the iterative compilation, the compiler is configured to sequentially apply a pass pipeline indicating a sequence of passes to each of the plurality of extracted hierarchies from an upper hierarchy to a lower hierarchy (See [0044]- We describe various embodiments that feature an iterative/sequential approach where every architecture level is successively targeted, as illustrated in FIG. 1and [0047]- FIG. 2A illustrates a compilation flow in which polyhedra as modified by the optimization(s) performed at a particular level of hardware hierarchy are passed on to the next level and [0075]- In step 304, a particular memory level from a target architecture is selected. The target architecture may have any number of processor and/or memory levels, such as 1, 2, 3, 5, 8, etc., levels, and [0079]- In various embodiments, after focalization iteration(s) are performed for a selected memory level, another memory level is selected from the target architecture at step 304, and the steps 306-314, each of the steps 306, 310, 312 being optional, may be repeated for the other memory level. These process steps may be iterated for one, some, or all memory levels of the target architecture).
As to claim 5, Baskaran also teaches wherein each of the plurality of passes constituting the pass pipeline is configured to be applicable to hierarchies of a plurality of systems, including the target system, without being dependent on an individual system of the plurality of systems (see e.g. [0044]- We describe various embodiments that feature an iterative/sequential approach where every architecture level is successively targeted, as illustrated in FIG. 1. In our approach, a different optimization problem is solved specifically for every considered level, according to one or more hardware characteristics of the considered level, see Fig.2A and associated text, e.g. [0047]- In particular, various optimizations applied and the parameters used are specialized for that specific level, [0076]- In the optional step 306, compiler optimizations such as loop fission, loop fusion, loop interchange, loop unroll, loop jam and unroll, and/or loop reversal, may be performed. Alternatively, or in addition, optimizations such as strip mining and/or loop tiling may be performed. Strip mining and loop tiling can increase the number of dimensions (also called dimensionality or depth) of a loop nest. These optimizations can be based on one or more characteristics of the memory at the selected level, such as memory size, memory speed, the number of read and/or write ports of the memory, memory power consumption, etc. As such, these optimizations may optimize the memory access (in terms of speed, number of memory accesses, power consumed, etc.), at the selected memory level).
As to claim 7, Baskaran also teaches wherein, for the performing of the iterative compilation, the deep learning compiler is configured to compute a count of hierarchies constituting the target system from the received hardware representation and iteratively apply a pass pipeline to the plurality of extracted hierarchies by the computed count of hierarchies (See e.g. [0076]- These optimizations can be based on one or more characteristics of the memory at the selected level, such as memory size, memory speed, the number of read and/or write ports of the memory, memory power consumption, etc. As such, these optimizations may optimize the memory access (in terms of speed, number of memory accesses, power consumed, etc.), at the selected memory level. The optimizations may also focus on one or more loop dimensions while ignoring the other dimensions).
As to claim 8, Baskaran teaches the electronic device of claim 1, further comprising one or more processors comprising the compiler (see e.g. [0141]- the processor(s) and/or processing elements can thus be embedded in one or more devices that can be operated independently or together in a networked environment, where the network can include, for example, a Local Area Network (LAN), wide area network (WAN), and/or can include an intranet and/or the Internet and/or another network. The network(s) can be wired or wireless or a combination thereof and can use one or more communication protocols to facilitate communication between the different processors/processing elements).
Baskaran does not specifically teach a deep learning compiler.
In an analogous art of compiling code however, Brady discloses a deep learning compiler (e.g. compiler 105, see Fig.1, and associated text, e.g. [0028]- an example compiler (e.g., 105), such as an example neural network compiler and [0046]- an improved compiler may be configured to consume a machine learning framework's (e.g., TensorFlow, Caffe™, etc.) representation (e.g., 110) of a Deep Neural Network (DNN).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Baskaran to incorporate/implement the limitations as taught by Brady in order to provide a specialized compilation system that uses machine learning models more efficiently and effectively for the purpose of optimization.
As to claim 9, the limitations of the claims are substantially similar to the limitations of claim 1, and therefore, it is rejected for the reasons stated above.
As to claim 10, the limitations of the claims are substantially similar to the limitations of claim 2, and therefore, it is rejected for the reasons stated above.
As to claim 13, the limitations of the claims are substantially similar to the limitations of claim 5, and therefore, it is rejected for the reasons stated above.
As to claim 15, the limitations of the claims are substantially similar to the limitations of claim 7, and therefore, it is rejected for the reasons stated above.
As to claim 16, the limitations of the claims are substantially similar to the limitations of claim 1, and therefore, it is rejected for the reasons stated above.
As to claim 17, the limitations of the claims are substantially similar to the limitations of claim 1, and therefore, it is rejected for the reasons stated above.
Allowable Subject Matter
Claims 3, 4, 6, 11, 12, 14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bharadwaj et al (US Patent Application Publication 2022/0100257 A1) discloses Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. Prabhakar et al (US Patent 11,126,574 B1) discloses instrumentation profiling of runtime execution of dataflow pipelines on reconfigurable processors.
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/CHENECA SMITH/Examiner, Art Unit 2192
/S. Sough/SPE, Art Unit 2192
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