DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (US 20180366423 A1 – hereinafter Ong) in view of Kang et al. (US 20220352061 A1 – hereinafter Kang).
Regarding independent claim 1, Ong teaches:
A device (100 – Fig. 1 – [0017] – “semiconductor package 100” – this is a
device), comprising:
a substrate (102 – Fig. 1 – [0017] – “substrate 102”);
a plurality of pads (408, 410 – Fig. 10 – [0029] – “The interconnect structure
(similar to 120 of FIG. 1) may comprise metal routing 404 and a plated through hole (PTH) 406. The ACI structures 408, 410 (similar to 126, 128) may be formed using similar techniques” – these are interpreted as pads and there is a plurality) including at least two deep trench capacitor (DTC) pads (804 and 808 – Fig. 8 – [0033 – “contact pad 804 … contact pad 808” – these are pads for capacitors 116 and 118 – [0018] – “components 116, 118 may comprise integrated circuits (IC), or discrete components of different types, such as capacitors, inductors, resistors, or other types of electric components” which can be DTC) disposed on the substrate (102);
a plurality of first metal layer contacts disposed on the DTC pads;
a first solder resist (SR) layer (Fig. 1 annotated, see below – [0030] – “dielectric layer 124 (e.g., solder resist), which may be disposed on the second side 106 of the package substrate 102, as shown. The reference voltage, e.g., Vss (ground reference voltage) or Vcc (power reference voltage) may be generated by the die 108 and provided to the reference plane 112 via one or more conductive paths 120, 122. As shown, the conductive paths 120, 122 may extend between the sides 104 and 106 of the substrate 102 into the dielectric layer 124” – hereinafter ‘124-1’, this corresponds to the first solder resist layer) disposed on the substrate (102), the pads (804 and 808 – Fig. 5 shows this) and the first metal layer contacts;
a plurality of second metal layer contacts disposed on the first metal layer contacts;
a second SR layer (Fig. 1 annotated, see below – [0030] – “dielectric layer 124 (e.g., solder resist), which may be disposed on the second side 106 of the package substrate 102, as shown. The reference voltage, e.g., Vss (ground reference voltage) or Vcc (power reference voltage) may be generated by the die 108 and provided to the reference plane 112 via one or more conductive paths 120, 122. As shown, the conductive paths 120, 122 may extend between the sides 104 and 106 of the substrate 102 into the dielectric layer 124” – hereinafter ‘124-2’, this corresponds to the first solder resist layer) disposed on the first SR layer (502-1) and the second metal layer contacts; and
a DTC coupled to the second metal layer contacts.
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Ong does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kang teaches
a plurality of first metal layer contacts (211W – Fig. 3 – [0025] – ““conductive pattern 216 may be in contact with a bottom surface of the first wire part 211W of the lowermost first redistribution pattern 211”) disposed on the DTC pads (211V – Fig. 3 – [0024] – “first via part 211V may be located on the first wire part 211W”);
a plurality of second metal layer contacts (352 – Fig. – 3 – [0030] – “the conductive connectors 350 may include a solder bump 351, a first bump pattern 352, a second bump pattern 353, and a third bump pattern 354”) disposed on the first metal layer contacts (211W);
a DTC (340 – Fig. 3 – [0027] – “capacitor chip 340”) coupled to the second metal layer contacts (352).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer contact and DTC structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results of [0002] – “a semiconductor package and a method of fabricating the same, and more particularly, to a semiconductor package including a redistribution substrate and a method of fabricating the same.”
Regarding claim 2, Ong as modified by Kang, teaches claim 1 from which claim 2 depends. Ong further teaches
wherein the DTC (116 and 118) comprises a land-side capacitor
(LSC) (118 – Fig. 1 – [0022] – “land side capacitor 118”).
Regarding claim 3, Ong as modified by Kang, teaches claim 1 from which claim 3 depends. Ong does not expressly disclose the limitations of claim 3.
However, in an analogous art, Kang teaches
wherein the first metal layer contacts (211W) comprise copper ([0024] – “first
redistribution patterns 211 may include or be formed of a first wire part 211W and a first via part 211V … first redistribution pattern 211 may include or be formed of a conductive material, for example, at least one selected from copper (Cu)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first metal layer structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 4, Ong as modified by Kang, teaches claim 1 from which claim 4 depends. Ong does not expressly disclose the limitations of claim 4.
However, in an analogous art, Kang teaches
wherein the second metal layer contacts (352) comprise copper ([0030] –
“The first bump pattern 352 may include or be formed of a conductive material, for example, copper (Cu)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second metal layer structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 5, Ong as modified by Kang, teaches claim 1 from which claim 5 depends. Ong further teaches
wherein the DTC (118) is spaced apart from the second SR layer (124
– Fig. 1 shows this).
Regarding claim 6, Ong as modified by Kang, teaches claim 1 from which claim 6 depends. Ong does not expressly disclose the limitations of claim 6.
However, in an analogous art, Kang teaches
further comprising a plurality of third metal layer contacts (354 – Fig. 3 –
[0030] – “The second bump pattern 353 may be interposed between the first bump pattern 352 and the third bump pattern 354”) disposed between the second metal layer contacts (352) and the DTC (340).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third metal layer structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 7, Ong as modified by Kang, teaches claim 6 from which claim 7 depends. Ong does not expressly disclose the limitations of claim 7.
However, in an analogous art, Kang teaches
further comprising a plurality of solder contacts (353 – Fig. 3 – [0030] – “The
second bump pattern 353 may be interposed between the first bump pattern 352 and the third bump pattern 354”) disposed between the third metal layer contacts (354) and the second metal layer contacts (352).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the solder contact structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 8, Ong as modified by Kang, teaches claim 1 from which claim 8 depends. Ong further teaches
further comprising at least one ball grid array (BGA) ball (154 – Fig. 1
– [0022] – “BGAs through direct contact between a connector (e.g., solder ball) 154”) disposed on at least one of the pads (408).
Regarding claim 9, Ong as modified by Kang, teaches claim 1 from which claim 9 depends. Ong further teaches
wherein the pads (408, 410) comprise solder mask defined
(SMD) pads ([0034] – “FIG. 9 illustrates the example system after the solder resist development and surface finish on the semiconductor package 300. As shown, bump pads 902 and land side capacitor (LSC) Vss pads 904 may be exposed via a photolithography and etching process. In an embodiment, one or more surface finish metal layers e.g., gold (Au), nickel-palladium-gold (NiPdAu) may be deposited on bump pads 902 and LSC Vss pads 904 to prevent metal oxidation through example electroplating process” – “In an embodiment, one or more surface finish metal layers e.g., gold (Au), nickel-palladium-gold (NiPdAu) may be deposited on bump pads 902 and LSC Vss pads 904 to prevent metal oxidation through example electroplating process” this describes a mask process).
Regarding independent claim 10, Ong teaches:
A method of making a device (100 – Fig. 1 – [0017] – “semiconductor
package 100” – this is a device), comprising:
forming a plurality of pads (408, 410 – Fig. 10 – [0029] – “The interconnect
structure (similar to 120 of FIG. 1) may comprise metal routing 404 and a plated through hole (PTH) 406. The ACI structures 408, 410 (similar to 126, 128) may be formed using similar techniques” – these are interpreted as pads and there is a plurality) including at least two deep trench capacitor (DTC) pads (804 and 808 – Fig. 8 – [0033 – “contact pad 804 … contact pad 808” – these are pads for capacitors 116 and 118 – [0018] – “components 116, 118 may comprise integrated circuits (IC), or discrete components of different types, such as capacitors, inductors, resistors, or other types of electric components” which can be DTC) on a substrate (102 – Fig. 1 – [0017] – “substrate 102”);
forming a plurality of first metal layer contacts on the DTC pads;
forming a first solder resist (SR) (Fig. 1 annotated, see below – [0030] – “dielectric layer 124 (e.g., solder resist), which may be disposed on the second side 106 of the package substrate 102, as shown. The reference voltage, e.g., Vss (ground reference voltage) or Vcc (power reference voltage) may be generated by the die 108 and provided to the reference plane 112 via one or more conductive paths 120, 122. As shown, the conductive paths 120, 122 may extend between the sides 104 and 106 of the substrate 102 into the dielectric layer 124” – hereinafter ‘124-1’, this corresponds to the first solder resist layer) on the substrate (102), the pads (804 and 808) and the first metal layer contacts;
forming a plurality of second metal layer contacts on the first metal layer contacts;
forming a second SR layer (Fig. 1 annotated, see below – [0030] – “dielectric layer 124 (e.g., solder resist), which may be disposed on the second side 106 of the package substrate 102, as shown. The reference voltage, e.g., Vss (ground reference voltage) or Vcc (power reference voltage) may be generated by the die 108 and provided to the reference plane 112 via one or more conductive paths 120, 122. As shown, the conductive paths 120, 122 may extend between the sides 104 and 106 of the substrate 102 into the dielectric layer 124” – hereinafter ‘124-2’, this corresponds to the first solder resist layer) on the first SR layer (502-1) and the second metal layer contacts; and
forming a DTC on the second metal layer contacts.
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Ong does not expressly disclose the other limitations of claim 10.
However, in an analogous art, Kang teaches
forming a plurality of first metal layer contacts (211W – Fig. 3 – [0025] – ““conductive pattern 216 may be in contact with a bottom surface of the first wire part 211W of the lowermost first redistribution pattern 211”) on the DTC pads (211V – Fig. 3 – [0024] – “first via part 211V may be located on the first wire part 211W”);
forming a plurality of second metal layer contacts (352 – Fig. – 3 – [0030] – “the conductive connectors 350 may include a solder bump 351, a first bump pattern 352, a second bump pattern 353, and a third bump pattern 354”) on the first metal layer contacts (211W);
forming a DTC (340 – Fig. 3 – [0027] – “capacitor chip 340”) on the second metal layer contacts (352).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer contact and DTC structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 11, Ong as modified by Kang, teaches claim 10 from which claim 11 depends. Ong further teaches
wherein the DTC (116 and 118) comprises a land-side capacitor
(LSC) (118 – Fig. 1 – [0022] – “land side capacitor 118”).
Regarding claim 12, Ong as modified by Kang, teaches claim 10 from which claim 12 depends. Ong further teaches
wherein the DTC (118) is spaced apart from the second SR layer (124
– Fig. 1 shows this).
Regarding claim 13, Ong as modified by Kang, teaches claim 10 from which claim 13 depends. Ong does not expressly disclose the limitations of claim 13.
However, in an analogous art, Kang teaches
further comprising forming a plurality of third metal layer contacts
(354 – Fig. 3 – [0030] – “The second bump pattern 353 may be interposed between the first bump pattern 352 and the third bump pattern 354”) between the second metal layer contacts (352) and the DTC (340).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third metal layer structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 14, Ong as modified by Kang, teaches claim 13 from which claim 14 depends. Ong does not expressly disclose the limitations of claim 14.
However, in an analogous art, Kang teaches
further comprising forming a plurality of solder contacts (353 – Fig. 3 –
[0030] – “The second bump pattern 353 may be interposed between the first bump pattern 352 and the third bump pattern 354”) between the third metal layer contacts (354) and the second metal layer contacts (352).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the solder contact structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 15, Ong as modified by Kang, teaches claim 10 from which claim 15 depends. Ong further teaches
further comprising forming at least one ball grid array (BGA) ball
(154 – Fig. 1 – [0022] – “BGAs through direct contact between a connector (e.g., solder ball) 154”) on at least one of the pads (408).
Regarding claim 16, Ong as modified by Kang, teaches claim 10 from which claim 16 depends. Ong further teaches
wherein the pads comprise solder mask defined (SMD) pads ([0034] –
“FIG. 9 illustrates the example system after the solder resist development and surface finish on the semiconductor package 300. As shown, bump pads 902 and land side capacitor (LSC) Vss pads 904 may be exposed via a photolithography and etching process. In an embodiment, one or more surface finish metal layers e.g., gold (Au), nickel-palladium-gold (NiPdAu) may be deposited on bump pads 902 and LSC Vss pads 904 to prevent metal oxidation through example electroplating process” – “In an embodiment, one or more surface finish metal layers e.g., gold (Au), nickel-palladium-gold (NiPdAu) may be deposited on bump pads 902 and LSC Vss pads 904 to prevent metal oxidation through example electroplating process” this describes a mask process).
Regarding independent claim 17, Ong teaches:
An electronic device (100 – Fig. 1 – [0017] – “semiconductor package
100” – this is a device), comprising:
an integrated circuit (IC) package (100 – Fig. 1 – [0017] – “semiconductor
package 100”) that comprises:
a substrate (102 – Fig. 1 – [0017] – “substrate 102”);
a plurality of pads (408, 410 – Fig. 10 – [0029] – “The interconnect structure (similar to 120 of FIG. 1) may comprise metal routing 404 and a plated through hole (PTH) 406. The ACI structures 408, 410 (similar to 126, 128) may be formed using similar techniques” – these are interpreted as pads and there is a plurality) including at least two deep trench capacitor (DTC) pads (804 and 808 – Fig. 8 – [0033 – “contact pad 804 … contact pad 808” – these are pads for capacitors 116 and 118 – [0018] – “components 116, 118 may comprise integrated circuits (IC), or discrete components of different types, such as capacitors, inductors, resistors, or other types of electric components” which can be DTC) disposed on the substrate (102);
a plurality of first metal layer contacts disposed on the DTC pads;
a first solder resist (SR) layer (Fig. 1 annotated, see below – [0030] – “dielectric layer 124 (e.g., solder resist), which may be disposed on the second side 106 of the package substrate 102, as shown. The reference voltage, e.g., Vss (ground reference voltage) or Vcc (power reference voltage) may be generated by the die 108 and provided to the reference plane 112 via one or more conductive paths 120, 122. As shown, the conductive paths 120, 122 may extend between the sides 104 and 106 of the substrate 102 into the dielectric layer 124” – hereinafter ‘124-1’, this corresponds to the first solder resist layer) disposed on the substrate (102), the pads (804 and 808 – Fig. 5 shows this) and the first metal layer contacts;
a plurality of second metal layer contacts disposed on the first metal layer contacts;
a second SR layer (Fig. 1 annotated, see below – [0030] – “dielectric layer 124 (e.g., solder resist), which may be disposed on the second side 106 of the package substrate 102, as shown. The reference voltage, e.g., Vss (ground reference voltage) or Vcc (power reference voltage) may be generated by the die 108 and provided to the reference plane 112 via one or more conductive paths 120, 122. As shown, the conductive paths 120, 122 may extend between the sides 104 and 106 of the substrate 102 into the dielectric layer 124” – hereinafter ‘124-2’, this corresponds to the first solder resist layer) disposed on the first SR layer (502-1) and the second metal layer contacts; and
a DTC coupled to the second metal layer contacts.
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Ong does not expressly disclose the other limitations of claim 10.
However, in an analogous art, Kang teaches
a plurality of first metal layer contacts (211W – Fig. 3 – [0025] – ““conductive
pattern 216 may be in contact with a bottom surface of the first wire part 211W of the lowermost first redistribution pattern 211”) disposed on the DTC pads (211V – Fig. 3 – [0024] – “first via part 211V may be located on the first wire part 211W”);
a plurality of second metal layer contacts (352 – Fig. – 3 – [0030] – “the conductive connectors 350 may include a solder bump 351, a first bump pattern 352, a second bump pattern 353, and a third bump pattern 354”) disposed on the first metal layer contacts (211W);
a DTC (340 – Fig. 3 – [0027] – “capacitor chip 340”) coupled to the second metal layer contacts (352).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer contact and DTC structure as taught by Kang into Ong.
An ordinary artisan would have been motivated to use the known technique of Kang in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 18, Ong as modified by Kang, teaches claim 17 from which claim 18 depends. Ong further teaches
wherein the DTC (118) is spaced apart from the second SR layer (124
– Fig. 1 shows this).
Regarding claim 19, Ong as modified by Kang, teaches claim 17 from which claim 19 depends. Ong further teaches
wherein the IC package (100) further comprises at least one ball grid
array (BGA) ball (154 – Fig. 1 – [0022] – “BGAs through direct contact between a connector (e.g., solder ball) 154”) disposed on at least one of the pads (408).
Regarding claim 20, Ong as modified by Kang, teaches claim 17 from which claim 20 depends. Ong further teaches
The electronic device of claim 17, wherein the electronic device (100)
comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle ([0045] – “These other components may include, but are not limited to, volatile memory (e.g., dynamic random-access memory (DRAM)) 1307, static random access memory (SRAM) 1309, non-volatile memory (e.g., read-only memory (ROM)) 1310, flash memory 1311, a graphics central processing unit (CPU) 1312, a digital signal processor 1313, a chipset 1314, a display (e.g., a touchscreen display) 1318, a touchscreen controller 1320, a battery 1322, an audio codec, a video codec, a power amplifier (not shown), a global positioning system (GPS) device 1326, a compass 1328, a Geiger counter, an accelerometer, a gyroscope (not shown), a speaker 1330, a camera 1317, and a mass storage device 1332. These components may be included in IC packages, e.g., the package 100”).
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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