DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statements (IDS) filed on May 20th, 2024, and March 29th, 2025, have been previously considered by the Examiner.
Specification
The specification objection (e.g., title objection) as previously issued has been withdrawn due to Applicant’s title amendment dated August 7th, 2026.
The abstract is objected to for failing to be in narrative form. Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. See MPEP § 608.01(b).
Claim Objections
The claim objections as previously issued have been withdrawn due to Applicant’s claim amendments dated August 7th, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang, et al. (US 20210375857 A1; hereinafter referred to as Huang857).
Regarding Claim 20, Huang857 discloses a semiconductor device comprising:
an insulating base layer (backside multilayer interconnection 370, Figs. 20A-20D);
a plurality of semiconductor patterns (second semiconductor layers 124, [0017], Figs. 20A-20E; the semiconductor patterns of the instant application are channel regions of a transistor, analogous to the second semiconductor layers 124) stacked on the insulating base layer and spaced apart from each other (Figs. 20A-20E; the semiconductor layers are spaced apart from each other by first semiconductor layers);
a gate structure surrounding the plurality of semiconductor patterns (gate structures 260, [0043], Figs. 20A-20E; “the gate structures 260 encircle (wrap) the semiconductor layers 124”);
first and second source/drain patterns on the insulating base layer and connected to both side surfaces of the plurality of semiconductor patterns, respectively (top epitaxial structures 240, [0036], Figs. 20A-20E);
a contact structure connected to first source/drain patterns through the insulating base layer (backside via 360, [0062, 0063, 0065], Figs. 20A-20E);
a sidewall insulating film (sidewall spacers 310, [0067], Figs. 20A-20E) between an upper portion of the contact structure and an upper portion of the insulating base layer (Huang857: Figs. 20A-20E), the sidewall insulating film extending onto at least a portion of a side surface of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns (Figs. 20A-20E; the sidewall spacers [first sidewall insulating film] extends onto at least a portion of a lower side surface of the gate structures below the lowermost second semiconductor layer [semiconductor pattern]); and
a power transmission line on a surface of the insulating base layer and connected to the contact structure (vertical interconnects 372 and metal lines 374, [0063], Fig. 21B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-11 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang, et al. (US 20210375857 A1; hereinafter referred to as Huang857) and further in view of Xie, et al. (US 20230093101 A1; hereinafter referred to as Xie).
Regarding Claim 1, Huang857 discloses a semiconductor device (semiconductor device, [Abstract]), comprising:
an insulating base layer (backside multilayer interconnection 370, Figs. 20A-20E) having an insulating pattern (isolation materials 330, [0056], Figs. 20A-20E), the insulating pattern extending in a first direction (Figs. 20A-20E; the insulating patterns extend in a horizontal direction [x direction]);
a plurality of semiconductor patterns (second semiconductor layers 124, [0017], Figs. 20A-20E; the semiconductor patterns of the instant application are channel regions of a transistor, analogous to the second semiconductor layers 124) stacked on the insulating pattern and spaced apart from each other in a direction perpendicular to an upper surface of the insulating base layer (Figs. 20A-20E; the second semiconductor layers 124 are stacked on the isolation material [insulating pattern] and are spaced apart in the vertical direction);
a gate structure (gate structures 260, [0043], Figs. 20A-20E) extending in a second direction intersecting the first direction (Figs. 20A-20E), the gate structure surrounding the plurality of semiconductor patterns ([0043], Figs. 20A-20E; “the gate structures 260 encircle (wrap) the semiconductor layers 124”);
first and second source/drain patterns (top epitaxial structures 240, [0036], Figs. 20A-20E) on the insulating pattern and respectively connected to both side surfaces of the plurality of semiconductor patterns in the first direction (Figs. 20A-20E);
an interlayer insulating layer (front-side metal alloy layers 270) covering the first and second source/drain patterns ([0047], Figs. 20A-20E);
a first contact structure (backside via 360, [0065], Figs. 20A-20E) connected to the first source/drain pattern through the insulating base layer ([0062, 0063], Figs. 20A-20E); and
a first sidewall insulating film (sidewall spacers 310, [0067], Figs. 20A-20E) between an upper portion of the first contact structure and an upper portion of the insulating pattern ([0067], Figs. 20A-20E), the first sidewall insulating film extending to cover a side surface of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns (Figs. 20A-20E; the sidewall spacers [first sidewall insulating film] covers a portion of a lower side surface of the gate structures below the lowermost second semiconductor layer [semiconductor pattern]).
Huang857 fails to explicitly disclose the insulating base layer including a first insulating material layer and a second insulating material layer.
However, in analogous art, Xie discloses an insulating base laying including a first insulating material layer (Xie: buried oxide (BOX) layer 115, [0038], Fig. 8B) and a second insulating material layer (Xie: ILD layer 915, [0062, 0064], Fig. 9B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the insulating base layer of Huang857 such that it was made up of a first insulating material layer and a second insulating material layer as disclosed by Xie. It would have been obvious to one of ordinary skill in the art as there is a clear finding that the prior art includes each limitation stated, although not necessarily in a single reference (e.g., Xie discloses the additional features not disclosed by Huang857), with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. Further, one having ordinary skill in the art could have combined these teachings by known methods (as disclosed in Xie, the second insulating material layer is deposited above the BOX layer 115) and that each element merely performs the same function as it does separately (e.g., the insulating base material layer of Huang857 performs the same function as the insulating base material layer of Xie). Finally, one having ordinary skill in the art would have recognized that the introduction of a second insulating material layer would have the predictable result of a still functioning semiconductor device (e.g., the semiconductor device of Xie functions satisfactorily). Therefore, a prima facie case of obviousness has been made under MPEP 2143(I)(A).
Regarding Claim 2, Huang857/Xie discloses the semiconductor device of claim 1, wherein an upper end of the first sidewall insulating film is lower than a lower surface of the lowermost semiconductor pattern (Huang857: Fig. 20E).
Regarding Claim 3, Huang857/Xie discloses the semiconductor device of claim 2, wherein an upper surface of the first contact structure is at a level higher than a level of the upper end of the first sidewall insulating film (Huang857: Fig. 20E; the first portion of the backside via 362 extends to a level higher than the upper end of the sidewall spacers [sidewall insulating film]).
Regarding Claim 4, Huang857/Xie discloses the semiconductor device of claim 3, wherein a portion of the first contact structure adjacent to the upper end of the first sidewall insulating film is lower than the upper end of the first sidewall insulating film (Huang857: Fig. 20E; a portion of the backside via 360 that is adjacent to the upper end of the first sidewall insulating film is the first portion of the backside via 362 and said first portion extends to be lower than the upper end of the sidewall spacer).
Regarding Claim 5, Huang857/Xie discloses the semiconductor device of claim 3, wherein the upper surface of the first contact structure overlaps the lowermost semiconductor pattern in a horizontal direction or is higher than an upper surface of the lowermost semiconductor pattern (Huang857: Fig. 20E; the backside via [contact structure] has a portion, a backside CESL 340, which is along the upper surface of the backside via which overlaps the lowermost semiconductor pattern in the horizontal direction).
Regarding Claim 6, Huang857/Xie discloses the semiconductor device of claim 1, wherein
the upper portion of the insulating pattern covered by the first sidewall insulating film has a width in a range of 0.5 nm to 10 nm (Huang857: [0052], Fig. 20E; “height H1 of the sidewall spacers 310 is lower than about 40 nm, e.g., about 0 nm to about 40 nm”).
While the claimed width of the first sidewall insulating film (0.5 nm to 10 nm) narrows the upper-limit of the range of the width of the sidewall spacer as disclosed by Huang857 (about 0 nm to about 40 nm; 0.5 nm is about 0 nm), no criticality is established by the instant specification as to why 10 nm is the maximum width for an embodiment. While [0047] in the specification of the instant application explains the benefit to having a width within the range of 0.5 nm to 10 nm, no criticality is established as to the effects on the device if the width of the first sidewall insulating film goes beyond 10 nm. The same result of preventing (or reducing) loss of the first source/drain pattern when the substrate is removed is achieved when using the range as disclosed in Huang857. Therefore, a prima facie case of obviousness can be made that it would be obvious to optimize a first sidewall insulating film within the range as described in Huang857.
Regarding Claim 7, Huang857/Xie discloses the semiconductor device of claim 1, wherein the portion of the gate structure covered by the first sidewall insulating film is in a range of 0.5 nm to 5 nm (Huang857: [0051], Fig. 20E; sidewall spacers 310 have a thickness, T1, of about 2 nm to about 10 nm and, therefore, the portion of the gate structure that is covered by the sidewall spacers is about 2 nm to about 10 nm since the first sidewall insulating film is covering a lower surface of the gate structure).
While the claimed range of the portion of the gate structure being covered by the first sidewall insulating film overlaps with the disclosed range of Huang857, no criticality is established by the instant application as to the benefits of using this specific range. While [0048] of the specification of the instant application states a benefit of having the range be between 0.5 nm and 5 nm being that the sidewall insulating film may prevent (or reduce) damage to the vertical sacrificial pattern 240 when a dummy gate structure is removed, that same benefit is achieved in Huang857 in the overlapped range. No criticality is given to the specific end points of the claimed range in the instant application. Therefore, a prima facie case of obviousness can be made that since the claimed ranges overlap, it would be obvious to optimize the distance in which the first sidewall insulating film was covering the portion of the gate structure.
Regarding Claim 8, Huang857/Xie discloses the semiconductor device of claim 1, wherein a thickness of the first sidewall insulating film is in a range of 0.5 nm to 3 nm (Huang857: [0051], Fig. 20E; sidewall spacers 310 have a thickness, T1, of about 2 nm to about 10 nm and, therefore, the portion of the gate structure that is covered by the sidewall spacers is about 2 nm to about 10 nm).
While the claimed range of the portion of the gate structure being covered by the first sidewall insulating film overlaps with the disclosed range of Huang857, no criticality is established by the instant application as to the benefits of using this specific range. While [0049] of the specification of the instant application states a benefit of having the range be between 0.5 nm and 5 nm being that the sidewall insulating film may not interfere with the contact between the source/drain pattern and the lowermost semiconductor pattern, that same benefit is achieved in Huang857 in the overlapped range. No criticality is given to the specific end points of the claimed range in the instant application. Therefore, a prima facie case of obviousness can be made that since the claimed ranges overlap, it would be obvious to optimize the distance in which the first sidewall insulating film was covering the portion of the gate structure.
Regarding Claim 9, Huang857/Xie discloses the semiconductor device of claim 1, wherein a width of the first contact structure in the second direction corresponds to a width of the insulating pattern in the second direction (Huang857: [0065], Fig. 20E).
Regarding Claim 10, Huang857/Xie discloses the semiconductor device of claim 1, further comprising:
a device isolation layer on the insulating base layer and defining the insulating pattern (Huang857: isolation structure 130, [0022, 0056], Figs. 20A-20D),
wherein, in a cross-section in the second direction, a side surface of the first contact structure is in contact with the device isolation layer (Huang857: Fig. 20D) and the first sidewall insulating film has a portion between an upper portion of the device isolation layer and the first contact structure (Huang857: Fig. 20D).
Regarding Claim 11, Huang857/Xie discloses the semiconductor device of claim 1, further comprising:
a vertical insulating pattern connected to a lower surface of the second source/drain pattern, the vertical insulating pattern arranged in the insulating base layer (Huang857: isolation materials 330, Fig. 20C; isolation materials 330 are analogous to the vertical insulating pattern on the device where there is no contact structure formed); and
a second sidewall insulating film on a sidewall of an upper portion of the vertical insulating pattern, the second sidewall insulating film arranged on a level same as a level of the first sidewall insulating film (Huang857: sidewall spacers 310, Fig. 20D; said Figure depicts that the sidewall spacers are arranged on the same level).
Regarding Claim 13, Huang857/Xie discloses the semiconductor device of claim 11, wherein the vertical insulating pattern includes a material same as a material of the insulating base layer (Huang857: [0056, 0063]; the MLI 370 [insulating base layer] is made of any low-k dielectric material, which is the same as the isolation materials 330 [insulating pattern]).
Regarding Claim 14, Huang857/Xie discloses the semiconductor device of claim 11, wherein the vertical insulating pattern includes a material different from a material of the insulating base layer (Huang857: [0056, 0063]; the MLI 370 [insulating base layer] is made of any low-k dielectric material, but the isolation materials 330 [vertical insulating pattern] can also be made of ultra-low-k materials and, therefore, would have different materials in combination), and the vertical insulating pattern is embedded in the insulating base layer (Huang857: Fig. 21A).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang857/Xie as applied to claims 1-11 and 13-14 above, and further in view of Huang, et al. (US 20220352326 A1; hereinafter referred to as Huang326).
Regarding Claim 12, Huang857/Xie discloses the semiconductor device of claim 11.
Huang857 fails to disclose that a second contact structure is connected to the second source/drain pattern through the interlay insulating layer.
However, an analogous art, Huang326, discloses a second contact structure (backside source contact 268, [0042], Fig. 25) connected to the second source/drain pattern (source feature 232S, [0042], Fig. 25) through the interlayer insulating layer (silicide layer 266, [0042], Fig. 25; ““the backside source contact 268 is electrically coupled to the source feature 232S by way of the silicide layer 266”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the integrated circuit structure such that a second contact structure would be formed as taught in Huang326. One would be motivated to have the second contact structure formed away from the insulating pattern as this offers greater design flexibility and, since there is an absence of a frontside source contact via, this design reduces the parasitic capacitance between gate contact vias and the frontside contact constructures, which leads to increased performance of the device and increased reliability (Huang326: [0044]).
Claims 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang857 and further in view of Huang, et al. (US 20220352326 A1; hereinafter referred to as Huang326).
Regarding Claim 15, Huang857 discloses a semiconductor device comprising:
an insulating base layer (backside multilayer interconnection 370, Figs. 20A-20E);
a plurality of semiconductor patterns (second semiconductor layers 124, [0017], Figs. 20A-20E; the semiconductor patterns of the instant application are channel regions of a transistor, analogous to the second semiconductor layers 124) stacked on a protruding portion of the insulating base layer (base portion 112, [0021], Fig. 2) and spaced apart from each other in a vertical direction (Fig. 2);
first and second source/drain patterns respectively connected to both side surfaces of the plurality of semiconductor patterns in a first direction (top epitaxial structures 240, [0036], Figs. 20A-20E);
a gate structure (gate structures 260, [0043], Figs. 20A-20E) extending in a second direction intersecting the first direction (Figs. 20A-20E), the gate structure surrounding the plurality of semiconductor patterns ([0043], Figs. 20A-20E; “the gate structures 260 encircle (wrap) the semiconductor layers 124”);
an interlayer insulating layer (front-side metal alloy layers 270) covering the first and second source/drain patterns ([0047], Figs. 20A-20E);
a first contact structure (backside via 360, [0065], Figs. 20A-20E) connected to the first source/drain pattern through the insulating base layer ([0062, 0063], Figs. 20A-20E);
a first sidewall insulating film (sidewall spacers 310, [0067], Figs. 20A-20E) surrounding an upper portion of the first contact structure ([0067], Figs. 20A-20E), and extending from a side surface of the protruding portion of the insulating base layer (Figs. 20A-20E), the first sidewall insulating film having an upper end on a level lower than a level of a lower surface of a lowermost semiconductor pattern among the plurality of semiconductor patterns and extending to cover a side surface of a portion of the gate structure located below the lowermost semiconductor pattern (Figs. 20A-20E; the sidewall spacer 310 is at a level lower than a level of a lower surface of the lowermost semiconductor pattern and covers a bottom side surface of a portion of the gate structure located below the lowermost semiconductor pattern);
a vertical insulating pattern connected to a lower surface of the second source/drain pattern, the vertical insulating pattern arranged in the insulating base layer (isolation materials 330, Fig. 20C; isolation materials 330 are analogous to vertical insulating patterns as they are connected to the source/drain pattern when a contact structure is not in place as shown in Fig. 20C); and
a second sidewall insulating film surrounding an upper portion of the vertical insulating pattern, the second sidewall insulating film arranged on a level same as a level of the first sidewall insulating film (sidewall spacers 310, Fig. 20D; said Figure depicts that the sidewall spacers are arranged on the same level).
Huang857 fails to disclose a second contact structure connected to the second source/drain pattern through the interlayer insulating layer.
However, Huang326 discloses a second contact structure (backside source contact 268, [0042], Fig. 25) connected to the second source/drain pattern (source feature 232S, [0042], Fig. 25) through the interlayer insulating layer (silicide layer 266, [0042], Fig. 25; ““the backside source contact 268 is electrically coupled to the source feature 232S by way of the silicide layer 266”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the integrated circuit device of Huang857 such that the second contact structure comes through the interlayer insulating layer as disclosed by Huang326. One would be motivated to have the second contact structure formed away from the insulating pattern as this offers greater design flexibility and, since there is an absence of a frontside source contact via, this design reduces the parasitic capacitance between gate contact vias and the frontside contact constructures, which leads to increased performance of the device and increased reliability (Huang326: [0044]).
Regarding Claim 16, Huang857/Huang326 discloses the semiconductor device of claim 15, wherein an upper surface of the first contact structure is higher than an upper surface of the vertical insulating pattern (Figs. 20C; backside via contact 360 has an upper surface higher than the isolation materials 330).
Claims 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang857/ Huang326 as applied to claims 15-16 above, and further in view of Chen, et al (US 20240387732 A1; hereinafter referred to as Chen).
Regarding Claim 17, Huang857/Huang326 discloses the semiconductor device of claim 15.
Huang857/Huang326 fail to teach wherein the vertical insulating pattern has an upper surface at a level higher than a level of an upper end of the second sidewall insulating film, as they only teach that the insulating pattern is at a same level as the second sidewall insulating film.
However, Chen, an analogous art, discloses wherein the vertical insulating pattern (ILD layer 54 forms the vertical insulating pattern and is located under the source/drain contact 66 as shown in Fig. 13A) has an upper surface at a level higher than a level of an upper end of the second sidewall insulating film (barrier layer 62, Fig. 13A; showing that the contact and, therefore, the ILD layer is at a level higher than an upper end of the barrier layer [sidewall insulating film]).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the integrated circuit device as taught in Huang857/Huang326 with the modification to the vertical insulating pattern such that it was disposed at a level higher than the level of an upper end of the second sidewall insulating film as taught in Chen. One would be motivated to do so as this modification permits decreased capacitance between the source/drain region and the gate electrodes [Chen: 0014]. A decreased capacitance increases device performance and lessens the possibility of the device degrading.
Regarding Claim 18, Huang857/Huang326/Chen discloses the semiconductor device of claim 17.
The combination of Huang857/Huang326/Chen fails to disclose wherein an edge region of the upper surface of the vertical insulating pattern has a portion lower than the upper end of the second sidewall insulating film.
However, a prima facie case of obviousness can be made for this limitation in light of the specification of the instant application. More specifically, the instant application fails to disclose criticality regarding an edge region of the upper surface of the vertical insulating pattern having a portion lower than an upper end of the second sidewall insulating film. While [0065-0066] disclose this embodiment, no criticality is established. With this lack of criticality, it can be rendered obvious that one of ordinary skill in the art prior to the effective filing date of the instant application could optimize the proportion and shape of the upper surface of the vertical insulating pattern to have a portion that is lower than the upper end of the second sidewall insulating film in order to obtain the expected result of decreased capacitance between the source/drain region and gate electrodes.
Claim 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang857/Huang326 as applied to claims 15-16 above, and further in view of Zhang, et al (US 20250294860 A1; hereinafter referred to as Zhang).
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection (more specifically with regards to Zhang) because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Regarding Claim 19, Huang857/Huang326 discloses the semiconductor device of claim 15.
The combination of Huang857/Huang326 fails to disclose wherein the vertical insulating pattern has an upper surface at a level lower than a level of an upper end of the second sidewall insulating film.
However, Zhang, an analogous art, discloses a semiconductor device of claim 15 wherein the vertical insulating pattern (frontside ILD 170, [0127], Fig. 15 (A-cut); the frontside ILD is made of similar material to that of the vertical insulating pattern and connects to the source/drain region similarly to the vertical insulating pattern) has an upper surface at a level lower than a level of an upper end of the second sidewall insulating film (gate spacer 150, Fig. 15 (A-cut); the gate spacer is analogous to the sidewall insulating film as both act as a spacer for the formation of the contacts and protect the source/drain and active region during etching).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the integrated circuit device as taught by Huang857/Huang326 to resemble the modification to the vertical insulating pattern as taught by Zhang. One would be motivated to do so if, during the formation of the source/drain region, there was overgrowth during the crystallographic process and one wished to remove this overgrowth to increase device performance by exposing more of the source/drain region ([Zhang: 0094]).
Response to Arguments
Applicant’s arguments, see pages 10-14, filed August 7th, 2026, with respect to the rejection of Claims 1-20 under 35 U.S.C. § 102(a)(1) and 35 U.S.C. § 103 have been fully considered and are persuasive in part and unpersuasive in part. Applicant argues the following:
Regarding Claim 1, Applicant has made a claim amendment, adding the limitation, “… the insulating base layer including a first insulating material layer and a second insulating material layer;”. Applicant’s argument that the added limitation to Claim 1 overcomes the prior art rejection as previously applied is persuasive and, therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Huang857 and in view of Xie. While Huang857 fails to explicitly disclose that the insulating base layer may be two insulating material layers, Xie discloses an insulating base layer comprising a first insulating material layer (buried oxide layer 115) and a second insulating material layer (ILD layer 915). As such, Claim 1 is rejected as stated above.
Further, regarding independent Claims 1, 15, and 20, Applicant argues that Huang857’s sidewall spacer (310) is not analogous to the instant applicant’s first sidewall insulating film. Applicant argues this in three parts, all of which are unpersuasive.
As argued on pages 10-11, Applicant states, in substance, that Huang857’s sidewall spacer (310) “is proposed as a structure formed during a backside process (see FIGS. 16A and 16B of Huang ‘857…). In contrast, the claimed first sidewall insulating film (170) is formed, i.e., formed prior to formation of the source/drain pattern during a frontside process (see FIGS. 7F and 7G of the present application…). This argument is not persuasive for at least the following reasons. Pursuant to MPEP § 2113, “The patentability of a product does not depend on its method of production”. In the instant case, the claim invention is that of a product. As such, the formation method of Huang857’s sidewall spacer being different than the instant applications first sidewall insulating film has no bearing on patentability as both are structurally analogous (formed in a shared and defined space of the same material). Additionally, it is noted that the features upon which application relies (i.e., the sidewall insulating spacer (170) is formed prior to formation of the source/drain pattern during a frontside process) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In RE: Van Geuns, 988 F.2D 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The omission of said language from the claim limitations further establishes this argument as not persuasive.
As argued on pages 11-12, Applicant states, in substance, “The two configurations are also different in terms of their purpose of introduction. The sidewall spacer (310) of Huang 857 is a configuration introduced to widen the area of the lower portion of the space for a backside via, thereby reducing resistance. In contrast, the claimed sidewall spacer (170) of the present invention is a configuration introduced to prevent epitaxial damage to the sacrificial pattern (240) during the etching process of the dummy gate”. This argument is also not persuasive. Similarly, Examiner notes that the features upon which applicant relies (i.e., the intended use of the claimed sidewall spacer 170) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In RE: Van Geuns, 988 F.2D 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As argued on pages 12-14, Applicant states, in substance, “Due to these fundamental differences in process and purpose, the first sidewall insulating film as recited in Claim 1 is characterized in that it ‘extends to cover a side surface of a portion of the gate structure’, whereas the sidewall spacer (310) of Huang 857 has a structure that is necessarily incapable of covering the side surface of the gate structure…” This argument is also not persuasive. As shown in Huang857, Fig. 20E, the sidewall spacer (310) does extend to cover a side surface of a portion of the gate structure. More specifically, it extends to cover a bottom side surface of the gate structure. Therefore, under broadest reasonable interpretation of the claim language, the sidewall spacer (310) of Huang857 is capable of extending to cover a side surface of a portion of the gate structure. As such, said argument is not persuasive. Examiner encourages Applicant to amend said limitation to include, “an inner side surface…” or further define which side surface of the gate structure is being covered in order to overcome the instant prior art rejection and more appropriately read upon the disclosed invention.
In the interest of compact prosecution, Examiner respectfully requests that Applicant please consider a follow-up telephone interview with the Examiner to discuss proposed claim amendments to overcome the rejection of independent Claims 1, 15, and 20 before filing a written response to this Final Office Action. For example, Examiner suggests incorporating the proposed amendments as provided in the Proposed Interview Agenda from the interview which took place on June 16th, 2026. More specifically, Examiner suggests further defining the first contact structure as done in the Proposed Interview Agenda in order to overcome the instant prior art rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
(a) Zou, et al. (US 2024/0421037 A1); discloses a semiconductor device including a sidewall insulating film analogous to the instant application.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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